1. EE325, CMOS Design, Lab 7: Analog Switch
Colorado Technical University
L-Edit Designed & PSpice Simulation of an Analog Switch
Lab 7 Report
Submitted to Professor R. Hoffmeister
In Partial Fulfillment of the Requirements for
EE 325-CMOS Design
By
Loren Karl Robinson Schwappach
Student Number: 06B7050651
Colorado Springs, Colorado
Due: 16 June 2010
Completed: 16 June 2010
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2. EE325, CMOS Design, Lab 7: Analog Switch
Table of Contents
Lab Objectives ....................................................................................................................................................................................................3
Requirements and Design Approaches/Trade-Offs ..........................................................................................................................3
L-Edit Analog Switch ............................................................................................................................................................................... 4-10
Analog Switch Design Details ............................................................................................................................................... 4-6
Analog Switch L-Edit Model .......................................................................................................................................................7
Analog Switch Cross Sections....................................................................................................................................................8
Analog Switch Design Rule Check ..........................................................................................................................................8
Analog Switch L-Edit Extracted SW.SPC File ......................................................................................................................9
Analog Switch Modified SCNA.SPC File .............................................................................................................................. 10
Analog Switch Test Plan ........................................................................................................................................................... 10
Analog Switch Proof of Function ........................................................................................................................................................... 11
Circuit Layout ................................................................................................................................................................................ 11
PSpice Simulation Results........................................................................................................................................................ 11
Analog Switch Frequency Response / Bandwidth ......................................................................................................................... 12
Circuit Layout ................................................................................................................................................................................ 12
PSpice Simulation Results........................................................................................................................................................ 12
Analog Switch Resistance .......................................................................................................................................................................... 13
Circuit Layout ................................................................................................................................................................................ 13
PSpice Simulation Results........................................................................................................................................................ 13
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3. EE325, CMOS Design, Lab 7: Analog Switch
Lab Objectives
The objective of this lab is to create an analog switch using L-Edit and verify the switches
operation using PSpice. The Analog switch must be able to achieve an on-resistance of four
hundred ohms or less while the input voltage ranges from 0V to 5V. A formal lab report is
not required for this lab.
Requirements and Design Approaches / Trade-offs
The requirements for this lab are to design an analog switch with appropriate sizes
necessary for achieving an on-resistance of four hundred ohms or less. The design must
use the MORBN20 design rules, and use the default 2 micron, 11-mask CMOS SCNA
technology design constraints. After the design calculations determine the required W/L
for the pFET and nFET devices the model is built in L-Edit, and a design rule check must be
completed with zero DRC errors. Finally the device must be extracted for use in PSpice and
its’ switching operation, resistance, and bandwidth verified.
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4. EE325, CMOS Design, Lab 7: Analog Switch
L-Edit Analog Switch Design Details
In order to achieve the design specifications required by this lab the following procedures
and calculations were made in order to determine the required width and lengths of the L-
Edit Analog Switches pFET and nFET devices. The design approach and calculations follow
as illustrated by figures 1, 2, and 3.
Figure 1: Explanation of the Analog Switch and initial model and calculation plan for determining the
device (W/L)n and (W/L)p.
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5. EE325, CMOS Design, Lab 7: Analog Switch
Figure 2: Hand Calculations continued.
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6. EE325, CMOS Design, Lab 7: Analog Switch
Figure 3: Hand Calculations concluded. Final (W/L)n = 50/2, (W/L)p = 200/2 {4*50/2)
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7. EE325, CMOS Design, Lab 7: Analog Switch
L-Edit Analog Switch Layout
With the results from the hand calculations the design phase began using the Analog Switch
model proposed by figure 1 and the calculated W/Ls in figure 3.
Figure 4: L-Edit Analog Switch Design Layout.
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8. EE325, CMOS Design, Lab 7: Analog Switch
L-Edit CMOS NAND Gate Cross Section
Obtaining the Analog Switch’s cross section was accomplished by clicking Tools/Cross-
Section and clicking on the Analog Switch by using the “Pick” button.
Figure 5: L-Edit Analog Switch Cross Section, NMOS section is on left, PMOS section is on the right.
L-Edit Analog Switch Design Rule Check Results
-------------------- SW_DRC.DRC ---------------------
DRC Errors in cell Cell0 of file C:Documents and SettingsLorenDesktopLAB 7Lab7.
0 errors.
DRC Merge/Gen Layers Elapsed Time: 0.000000 seconds.
DRC Test Elapsed Time: 0.000000 seconds.
DRC Elapsed Time: 0 seconds.
-------------------------------------------------------
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9. EE325, CMOS Design, Lab 7: Analog Switch
L-Edit Analog Switch Extracted File
Some important things to not about this file, are the “Node Name Aliases”, these are the net
aliases names that must be used in PSpice. Also mentioned are PMOS and NMOS lengths
and widths.
-------------------- SW.SPC ---------------------
* Circuit Extracted by Tanner Research's L-Edit V7.12 / Extract V4.00 ;
* TDB File: C:Documents and SettingsLorenDesktopLAB 7Lab7, Cell: Cell0
* Extract Definition File: C:LEditmosismorbn20.ext
* Extract Date and Time: 06/07/2010 - 16:23
* WARNING: Layers with Unassigned AREA Capacitance.
* <Poly Resistor>
* <Poly2 Resistor>
* <N Diff Resistor>
* <P Diff Resistor>
* <N Well Resistor>
* <P Base Resistor>
* WARNING: Layers with Unassigned FRINGE Capacitance.
* <Pad Comment>
* <Poly Resistor>
* <Poly2 Resistor>
* <N Diff Resistor>
* <P Diff Resistor>
* <N Well Resistor>
* <P Base Resistor>
* <Poly1-Poly2 Capacitor>
* WARNING: Layers with Zero Resistance.
* <Pad Comment>
* <Poly1-Poly2 Capacitor>
* <NMOS Capacitor>
* <PMOS Capacitor>
* NODE NAME ALIASES
* 1 = VDD (-24,62)
* 2 = G (38,-8)
* 3 = GB (-24,-8)
* 4 = VSS (52,-8)
* 5 = A (10,62)
* 6 = Y (10,-8)
M1 A GB Y VDD PMOS L=2u W=50u AD=900p PD=336u AS=600p PS=224u
* M1 DRAIN GATE SOURCE BULK (13 5 15 55)
M2 Y GB A VDD PMOS L=2u W=50u AD=600p PD=224u AS=900p PS=336u
* M2 DRAIN GATE SOURCE BULK (5 5 7 55)
M3 A GB Y VDD PMOS L=2u W=50u AD=900p PD=336u AS=600p PS=224u
* M3 DRAIN GATE SOURCE BULK (-3 5 -1 55)
M4 Y GB A VDD PMOS L=2u W=50u AD=600p PD=224u AS=900p PS=336u
* M4 DRAIN GATE SOURCE BULK (-11 5 -9 55)
M5 Y G A VSS NMOS L=2u W=50u AD=300p PD=112u AS=300p PS=112u
* M5 DRAIN GATE SOURCE BULK (37 5 39 55)
* Total Nodes: 6
* Total Elements: 5
* Extract Elapsed Time: 0 seconds
.END
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10. EE325, CMOS Design, Lab 7: Analog Switch
Edited SCNA.CSE File Required for using L-Edit Analog Switch
Lines 2 and 11 of this file were edited to change CMOSN to NMOS and CMOSP to PMOS.
-------------------- SCNA.SPC ---------------------
* THESE ARE TYPICAL SCNA SPICE LEVEL 2 PARAMETERS
.MODEL NMOS NMOS LEVEL=2 LD=0.250000U TOX=417.000008E-10
+ NSUB=6.108619E+14 VTO=0.825008 KP=4.919000E-05 GAMMA=0.172
+ PHI=0.6 UO=594 UEXP=6.682275E-02 UCRIT=5000
+ DELTA=5.08308 VMAX=65547.3 XJ=0.250000U LAMBDA=6.636197E-03
+ NFS=1.98E+11 NEFF=1 NSS=1.000000E+10 TPG=1.000000
+ RSH=32.740000 CGDO=3.105345E-10 CGSO=3.105345E-10 CGBO=3.848530E-10
+ CJ=9.494900E-05 MJ=0.847099 CJSW=4.410100E-10 MJSW=0.334060 PB=0.800000
* Weff = Wdrawn - Delta_W
* The suggested Delta_W is -0.25 um
.MODEL PMOS PMOS LEVEL=2 LD=0.227236U TOX=417.000008E-10
+ NSUB=1.056124E+16 VTO=-0.937048 KP=1.731000E-05 GAMMA=0.715
+ PHI=0.6 UO=209 UEXP=0.233831 UCRIT=47509.9
+ DELTA=1.07179 VMAX=100000 XJ=0.250000U LAMBDA=4.391428E-02
+ NFS=3.27E+11 NEFF=1.001 NSS=1.000000E+10 TPG=-1.000000
+ RSH=72.960000 CGDO=2.822585E-10 CGSO=2.822585E-10 CGBO=5.292375E-10
+ CJ=3.224200E-04 MJ=0.584956 CJSW=2.979100E-10 MJSW=0.310807 PB=0.800000
* Weff = Wdrawn - Delta_W
* The suggested Delta_W is -1.14 um
--------------------------------------------------------
Analog Switch Test Plan
Now that the L-Edit Analog Switch has been created, passed its DRC, and extracted, we will
check whether or not the device works (Proof of functionality), check out its bandwidth
(Frequency Response), and verify the on-resistance.
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11. EE325, CMOS Design, Lab 7: Analog Switch
Analog Switch Proof of Function
To prove the analog switch functions correctly the circuit shown in figure 6 was created
and a time domain analysis simulation was completed. The results shown in figure 7
illustrate that the switch is on when G is high and off when G is low as required.
0
V1 = 0 TR = 1ns
V2 = 5 TF = 1ns
PER = 200us TD = 0
PW = 100us
V1
VGB
5Vdc
0
GB VDD
A Transmission Gate / Analog Switch Y
V2
Net Aliases {VDD, G, GB, VSS, A, Y}
V
VOFF = 2.5 RL
VAMPL = 1 G VSS 400
FREQ = 10k
0 V1 = 5 TR = 1ns Rg
V2 = 0 TF = 1ns VG 1
0
PER = 200us TD = 0
PW = 100us
0 0
Figure 6: PSpice Analog Switch Circuit Diagram for testing functionality.
V
o 3.0V (174.997u,1.5000) V(A) = 2 Vpp
l
t
s (124.996u,3.5000)
2.0V
V(A)
5.0V
V
o
l
t 2.5V
s
0V
V(G)
5.0V
V
o
l
t 2.5V
s
0V
V(GB)
V
o 2.0V Rsw = (RL/Gain) - RL = 209.18 (174.997u,901.561m) V(Y) = 1.313239 Vpp
l
t
1.0V
s (124.996u,2.2148)
SEL>> Gain = 656.6195mV/V
0V
0s 50us 100us 150us 200us 250us 300us 350us 400us
V(Y)
Time
Figure 7: PSpice Analog Switch Simulation Results. Notice that the switch is on (only passes the input V(A))
when V(G) is high (5V), and V(GB) is low. However, when V(G) is low (0V) and V(GB) is high the switch is
‘off” and V(Y) = 0V.
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12. EE325, CMOS Design, Lab 7: Analog Switch
Analog Switch Frequency Response / Bandwidth
To find the frequency response of the analog switch the circuit shown in figure 8 was
created and an AC Sweep simulation was ran to find the bandwidth as shown in figure 9.
This bandwidth was noted as 1.4GHz.
0
V1
VGB
5Vdc
0
0Vdc
GB VDD
A Transmission Gate / Analog Switch Y
VA
Net Aliases {VDD, G, GB, VSS, A, Y}
1Vac RL
2.5Vdc G VSS 400
0 VG Rg
5Vdc 1
0
0 0
Figure 8: PSpice Analog Switch Circuit Diagram for plotting frequency response.
0
G
a
i
n
Bandwidth = 1.4019GHz
LP Filter (1.4019G,-5.9542)
(
d Corner Frequency = f*3dB
B 1.4019GHz
) -10
-16.9368 dB/decade
-20
(14.019G,-22.891)
-30
-40
1.0Hz 10Hz 100Hz 1.0KHz 10KHz 100KHz 1.0MHz 10MHz 100MHz 1.0GHz 10GHz 100GHz
DB(V(Y)/V(A))
Frequency
Figure 9: PSpice Analog Switch Frequency Response Simulation Results. Bandwidth is approximately 1.4 GHz.
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13. EE325, CMOS Design, Lab 7: Analog Switch
Analog Switch Resistance
To find the on-resistance of the analog switch the circuit shown by figure 10 below was
created and a bias analysis simulation was ran. The voltage and current results showed
that Iswitch = 3.838 mA and Vswitch = 965mV. Thus the on-resistance was calculated to be
approximately 251 ohms. Thus, the design constraint was met.
Figure 10: PSpice Analog Switch Circuit and Voltage and Current Results. The On-Resistance is approximately
251 ohms which is less than 400 ohms. Thus the device meets all requirements.
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