1. Getting the Best Patterns
Using Cell-aware Fault Models
ITC Theater – 2011
Michael Reese, Jason Rivers
2. Previous Work
Many published papers have addressed the problem of improving defect
coverage
2007/2008: EMD method was introduced (ITC 2007, paper 30.3; ITC 2008,
paper 20.1)
2009: Cell-aware basic methodology (ITC 2009, paper 1.2)
2010: Cell-aware gross-delay methodology for cell-internal bridges and
opens (ITC 2010, paper 10.1)
2011: Gate-exhaustive versus Cell-aware pattern sets for industrial
designs (VLSI-DAT 2011, paper w22)
2011: Small-delay effects and production results (ITC 2011, paper
9.1)
– This year in ITC Session 9: Defects
2 | ITC 2011 Theater | September 2011
2
3. Fault Model Selection
Gate-Exhaustive
Which
model
shall we
use
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4. State-of-the-art Cell-Internal ATPG views
ATPG view
ATPG tools use a gate level
D0
Z description of the library cells
D1
They assume faults at the
D2
library cell ports and, optionally,
S0 on the gate-level primitives
S1
The layout of the library cell
often has significantly more
Layout faults
vdd But how should we map the
layout related faults to the
D2 S1 D0 S0 D1
ATPG view?
Z
gnd
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5. Cell-Aware Layout Extraction - Bridges & Opens
Open vdd
The resistors and parasitic capacitors
defect
are extracted from the layout
M11
c1 c3 Each capacitor results in a potential
4 c2 R3 6 bridge defect
c4D2 c5
Z
R4 Each resistor results in a potential
M1 open defect
Bridge
defect gnd The cell-aware tool will insert one
defect at a time into the transistor
Open
vdd
netlist
R
defect net4 net6
8
R3 = 1GΩ
R3
c1 c3
M11
The analog simulation is then started
net4 net6 net4 net6
c2
R with the defective netlist to analyze if
7
gnd Z
gnd
the defects (bridges and opens) can
D2 R1 R2
be detected
net4 net6 R
gnd gnd
6
Bridge R4
c4 c5
M1 The result of this analog fault
defect
R = 1Ω gnd
R simulation is a detection matrix
5
gnd
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6. The new Cell-Aware Methodology
Library
Characterization Flow
Cell-Aware — One time task per tech
Layout Analog Fault
Extraction Simulation Fault Model
Generation
Reports — The characterization is
Cell SPICE Defect typically done by a central
Layout parasitics Matrix UDFM
library organization
GDS2 netlist User — The generated cell-aware
defects Defined
view can be used for every
Fault
Library Characterization Flow Model design in that technology
— Flow automation tool is part
of the Tessent ® tool suite
Normal Design Flow
UDFM — The design flow is not
affected at all
— No layout data is needed
Normal Cell-Aware Test because the layout is taken
Synthesis ATPG System
RTL .V .STIL into account already during
the characterization flow
— The UDFM ATPG is a new
Normal Design Flow function in Tessent
FastScan ®
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8. Cell Library Cell-aware Defects
Cell-Aware Additional Defects
900
imux6 # Internal Defects
800
# SA and TR Faults
700
imux4
600
# Defects
imux3
500
400
300
200
100
0
Standard Cells
For some cells there are significant numbers of
faults that are not specifically targeted
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9. 32-nm Technology ATPG Test Flow
fail exit
TR N-det
At-speed pass
SA fail
Slow-
speed pass
continue on fail
log fails Topoff
CA-1 CA-2
At-speed Slow-speed
log fails Topoff
log fails log fails
Normal Production Test Faultmodel experiment
9 | ITC 2011 Theater | September 2011
