SlideShare a Scribd company logo

Define location of Preplaced cells(http://www.vlsisystemdesign.com/PD-Flow.php)

•
•
VLSI SYSTEM Design
VLSI SYSTEM Design

https://www.udemy.com/vlsi-academy During placement and routing, most of the placement tools, place/move logic cells based on floorplan specifications. Some of the important or critical cell's locations has to be pre-defined before actual placement and routing stages. The critical cells are mostly the cells related to clocks, viz. clock buffers, clock mux, etc. and also few other cells such as RAM's, ROM,s etc. Since, these cells are placed in to core before placement and routing stage, they are called 'preplaced cells'.

Education
1 of 61
Let us assume, the below are the dimensions of the chip Die Core www.vlsisystemdesign.com
Let’s explore how a city is planned www.vlsisystemdesign.com
Let’s explore how a city is planned Railway Hospital Station Water Playground Storage Tank www.vlsisystemdesign.com
Basic necessities and utilities are pre-planned and positioned, in a manner to have the best reachability by each citizen Railway Hospital Station Water Playground Storage Tank www.vlsisystemdesign.com
In a similar fashion, we start planning the chip area, by prioritizing the location of critical cells. Die Core www.vlsisystemdesign.com
Crtical cells can be IP’s (memories, ALU, etc.) or std cells (clock Buffer, clock inverter, etc ) Die Core www.vlsisystemdesign.com
Let us understand, what are IP’s, std cells and their architecture? Die Core www.vlsisystemdesign.com
IP is a reusable unit of logic, cell, or chip layout design that is the intellectual property designed by any individual.  IP are also sometimes offered as generic gate-level netlist. i.e. standard cells, and complex cells.  It consists of transistor level layout for logical cells and complex cells, which are implemented using layout tools.  Lets have a look into internal of IP’s www.vlsisystemdesign.com
Consider one of the most commonly used IP i.e. CMOS Inverter Vdd Vdd In Inverter Out In Out Vss Vss www.vlsisystemdesign.com
CMOS Inverter consist of P-MOS Transistor Vdd PMOS – P Diff In Out Vss www.vlsisystemdesign.com
CMOS Inverter consist of N-MOS Transistor Vdd PMOS – P Diff In Out NMOS – N Diff Vss www.vlsisystemdesign.com
CMOS Inverter consist of Polysilicon Gate. Vdd Poly Gate PMOS – P Diff In Out NMOS – N Diff Vss Note : At the component level, polysilicon has been used as the conducting gate material in MOSFET and CMOS processing technologies. www.vlsisystemdesign.com
CMOS Inverter IN/ OUT Lines Vdd Poly Gate PMOS – P Diff In Out In NMOS – N Diff Vss www.vlsisystemdesign.com
CMOS Inverter IN/ OUT Ports Vdd Poly Gate PMOS – P Diff In Out In Out NMOS – N Diff Vss www.vlsisystemdesign.com
CMOS Inverter Vdd & Vss Ports. Vdd Vdd Poly Gate PMOS – P Diff In Out In Out NMOS – N Diff Vss Vss www.vlsisystemdesign.com
Lets draw preliminary layout of inverter using stick diagram www.vlsisystemdesign.com
Lets draw preliminary layout of inverter using stick diagram Stick Diagrams are useful for planning the layout and routing of integrated circuits. Every Line of a conducting material layer is represented by a line of a distinct color. www.vlsisystemdesign.com
Lets draw preliminary layout of inverter using stick diagram Stick Diagrams are useful for planning the layout and routing of integrated circuits. Every Line of a conducting material layer is represented by a line of a distinct color. Polysilicon Gate P Diffusion N Diffusion Metal Contact www.vlsisystemdesign.com
P-MOS Transistor represented by Bottle Green Color line PMOS – P Diff P Diff www.vlsisystemdesign.com
N-MOS Transistor represented by a Apple Green Color line PMOS – P Diff P Diff NMOS – N Diff N Diff www.vlsisystemdesign.com
Polysilicon gates represented by Brown Color line Poly Gate Poly PMOS – P Diff P Diff NMOS – N Diff N Diff www.vlsisystemdesign.com
Metal is represented by Bottle Blue Color line Poly Gate Poly PMOS – P Diff P Diff In In NMOS – N Diff N Diff www.vlsisystemdesign.com
Contacts are represented by Black Cross Poly Gate Poly PMOS – P Diff P Diff In In NMOS – N Diff N Diff = Contact www.vlsisystemdesign.com
Metal is represented by Bottle Blue Color line Poly Gate Poly PMOS – P Diff P Diff In Out In Out NMOS – N Diff N Diff = Contact www.vlsisystemdesign.com
Contacts are represented by Black Cross Poly Gate Poly PMOS – P Diff P Diff In Out In Out NMOS – N Diff N Diff = Contact www.vlsisystemdesign.com
Metal is represented by Bottle Blue Color line Vdd Vdd Poly Gate Poly PMOS – P Diff P Diff In Out In Out NMOS – N Diff N Diff Vss Vss = Contact www.vlsisystemdesign.com
Metal is represented by Bottle Blue Color line Vdd Vdd Poly Gate Poly PMOS – P Diff P Diff In Out In Out NMOS – N Diff N Diff Vss Vss = Contact www.vlsisystemdesign.com
Stick Diagrams are converted to Cell Layout by assigning length and width to the Wire Vdd Vdd Poly Poly P Diff P Diff In Out In Out N Diff N Diff Vss Vss = Contact = Contact www.vlsisystemdesign.com
Stick Diagrams are converted to Cell Layout by assigning length and width to the Wire Vdd Width (w) Poly P Diff In Out N Diff Vss = Contact www.vlsisystemdesign.com
Stick Diagrams are converted to Cell Layout by assigning length and width to the Wire Vdd Width (w) Length (L) Poly P Diff In Out N Diff Vss = Contact www.vlsisystemdesign.com
Cell Layout is a Black Box for IP User. Vdd Vdd Width (w) Length (L) Poly Poly P Diff P Diff In Out In Out N Diff N Diff Vss Vss = Contact = Contact www.vlsisystemdesign.com
In Black Box, internal architecture counts less compared to IP Functionality Vdd Vdd Poly Poly P Diff P Diff In Out In Out N Diff N Diff Vss Vss = Contact = Contact www.vlsisystemdesign.com
IP’s serves the purpose of the Circuit design i.e. Inverter in this case Vdd Vdd Poly P Diff In Out In Out N Diff Vss Vss = Contact www.vlsisystemdesign.com
Similarly, other IP’s available as blocks : www.vlsisystemdesign.com
Similarly, other IP’s available as blocks : Vdd In1 AND Out In2 Vss www.vlsisystemdesign.com
Similarly, other IP’s available as blocks : Vdd Vdd In1 In1 AND Out OR Out In2 In2 Vss Vss www.vlsisystemdesign.com
Similarly, other IP’s available as blocks : Vdd Vdd Vdd In1 In1 In1 AND Out OR Out NAND Out In2 In2 In2 Vss Vss Vss www.vlsisystemdesign.com
Complex blocks are also offered as IP’s www.vlsisystemdesign.com
Complex blocks are also offered as IP’s Vdd In Out Vss www.vlsisystemdesign.com
Complex blocks are also offered as IP’s Buffer is nothing but two inverters connected back-to-back Vdd In Out Vss www.vlsisystemdesign.com
Complex blocks are also offered as IP’s Buffer is nothing but two inverters connected back-to-back Vdd Vdd Vdd In Out In Out Vss Vss Vss www.vlsisystemdesign.com
Complex blocks are also offered as IP’s Buffer is nothing but two inverters connected back-to-back Vdd Vdd In Out Vss Vss www.vlsisystemdesign.com
Complex blocks are also offered as IP’s Buffer is nothing but two inverters connected back-to-back Vdd Vdd Vdd Vdd Poly Poly P Diff P Diff In Out In In Out Out N Diff N Diff Vss Vss www.vlsisystemdesign.com
Complex blocks are also offered as IP’s Buffer is nothing but two inverters connected back-to-back Vdd Vdd Vdd In Out In Buffer Out Vss Vss Vss www.vlsisystemdesign.com
IP’s are offered in form of rectangular/square boxes www.vlsisystemdesign.com
IP’s are offered in form of rectangular/square boxes For E.g. The Buffer IP, will be represented as below www.vlsisystemdesign.com
IP’s are offered in form of rectangular/square boxes For E.g. The Buffer IP, will be represented as below Vdd In Buffer Out Buffer Vss www.vlsisystemdesign.com
IP’s are offered in form of rectangular/square boxes For E.g. The AND Gate IP, will be represented as below www.vlsisystemdesign.com
IP’s are offered in form of rectangular/square boxes For E.g. The AND Gate IP, will be represented as below Vdd In1 AND Out AND In2 Vss www.vlsisystemdesign.com
Commonly asked Question How do we differentiate between Vdd and Vss ? www.vlsisystemdesign.com
Commonly asked Question How do we differentiate between Vdd and Vss ? It is represented in below pattern. A Cross line on the bottom left of the Block represents Vss and top corner Vdd www.vlsisystemdesign.com
Commonly asked Question How do we differentiate between Vdd and Vss ? It is represented in below pattern. A Cross line on the bottom left of the Block represents Vss and top corner Vdd Vdd Buffer Buffer Vss Vdd AND AND Vss www.vlsisystemdesign.com
Complex blocks e.g. ALU ALU www.vlsisystemdesign.com
Complex blocks e.g. ALU will be represented as below IP Block ALU www.vlsisystemdesign.com
• Memory is also a Complex IP used commonly. • It is necessary to pre-define the geometrical location of these IP’s on a chip, so that the automated PNR tools do not modify their locations • These cells are referred to as Pre-placed cells www.vlsisystemdesign.com
Die Core www.vlsisystemdesign.com
Block a Die Core www.vlsisystemdesign.com
Block a Block b Die Core www.vlsisystemdesign.com
Block a Block b Block c Die Core www.vlsisystemdesign.com
Block a Block b Pre-placed Cells Block c Die Core www.vlsisystemdesign.com
Thus we have defined the Location of Pre-placed Cell in Chip Block a Block b Pre-placed Cells Block c Die Core www.vlsisystemdesign.com

Recommended

Define Width and Height of Core and Die (http://www.vlsisystemdesign.com/PD-F...
Define Width and Height of Core and Die (http://www.vlsisystemdesign.com/PD-F...Define Width and Height of Core and Die (http://www.vlsisystemdesign.com/PD-F...
Define Width and Height of Core and Die (http://www.vlsisystemdesign.com/PD-F...
VLSI SYSTEM Design
 
Crosstalk.pdf
Crosstalk.pdfCrosstalk.pdf
Crosstalk.pdf
Ahmed Abdelazeem
 
Chapter1.slides
Chapter1.slidesChapter1.slides
Chapter1.slides
Avinash Pillai
 
Timing and Design Closure in Physical Design Flows
Timing and Design Closure in Physical Design Flows Timing and Design Closure in Physical Design Flows
Timing and Design Closure in Physical Design Flows
Olivier Coudert
 
Synopsys Fusion Compiler-Comprehensive RTL-to-GDSII Implementation System
Synopsys Fusion Compiler-Comprehensive RTL-to-GDSII Implementation SystemSynopsys Fusion Compiler-Comprehensive RTL-to-GDSII Implementation System
Synopsys Fusion Compiler-Comprehensive RTL-to-GDSII Implementation System
Mostafa Khamis
 
Physical design
Physical design Physical design
Physical design
Mantra VLSI
 
VLSI Physical Design Flow(http://www.vlsisystemdesign.com)
VLSI Physical Design Flow(http://www.vlsisystemdesign.com)VLSI Physical Design Flow(http://www.vlsisystemdesign.com)
VLSI Physical Design Flow(http://www.vlsisystemdesign.com)
VLSI SYSTEM Design
 
Inputs of physical design
Inputs of physical designInputs of physical design
Inputs of physical design
Kishore Sai Addanki
 

Recommended

Define Width and Height of Core and Die (http://www.vlsisystemdesign.com/PD-F...
Define Width and Height of Core and Die (http://www.vlsisystemdesign.com/PD-F...Define Width and Height of Core and Die (http://www.vlsisystemdesign.com/PD-F...
Define Width and Height of Core and Die (http://www.vlsisystemdesign.com/PD-F...
VLSI SYSTEM Design
 
Crosstalk.pdf
Crosstalk.pdfCrosstalk.pdf
Crosstalk.pdf
Ahmed Abdelazeem
 
Chapter1.slides
Chapter1.slidesChapter1.slides
Chapter1.slides
Avinash Pillai
 
Timing and Design Closure in Physical Design Flows
Timing and Design Closure in Physical Design Flows Timing and Design Closure in Physical Design Flows
Timing and Design Closure in Physical Design Flows
Olivier Coudert
 
Synopsys Fusion Compiler-Comprehensive RTL-to-GDSII Implementation System
Synopsys Fusion Compiler-Comprehensive RTL-to-GDSII Implementation SystemSynopsys Fusion Compiler-Comprehensive RTL-to-GDSII Implementation System
Synopsys Fusion Compiler-Comprehensive RTL-to-GDSII Implementation System
Mostafa Khamis
 
Physical design
Physical design Physical design
Physical design
Mantra VLSI
 
VLSI Physical Design Flow(http://www.vlsisystemdesign.com)
VLSI Physical Design Flow(http://www.vlsisystemdesign.com)VLSI Physical Design Flow(http://www.vlsisystemdesign.com)
VLSI Physical Design Flow(http://www.vlsisystemdesign.com)
VLSI SYSTEM Design
 
Inputs of physical design
Inputs of physical designInputs of physical design
Inputs of physical design
Kishore Sai Addanki
 
Static_Time_Analysis.pptx
Static_Time_Analysis.pptxStatic_Time_Analysis.pptx
Static_Time_Analysis.pptx
Ahmed Abdelazeem
 
Physical Design Flow Challenges at 28nm on Multi-million Gate Blocks
Physical Design Flow Challenges at 28nm on Multi-million Gate BlocksPhysical Design Flow Challenges at 28nm on Multi-million Gate Blocks
Physical Design Flow Challenges at 28nm on Multi-million Gate Blocks
eInfochips (An Arrow Company)
 
Eco
EcoEco
Eco
Rajesh M
 
Understanding cts log_messages
Understanding cts log_messagesUnderstanding cts log_messages
Understanding cts log_messages
Mujahid Mohammed
 
Physical design
Physical design Physical design
Physical design
Manjunath hosmani
 
Back end[1] debdeep
Back end[1] debdeepBack end[1] debdeep
Back end[1] debdeep
Sandeep Patil
 
Routing.pdf
Routing.pdfRouting.pdf
Routing.pdf
Ahmed Abdelazeem
 
1. Introduction to PnR.pptx
1. Introduction to PnR.pptx1. Introduction to PnR.pptx
1. Introduction to PnR.pptx
Ahmed Abdelazeem
 
Floorplanning.pdf
Floorplanning.pdfFloorplanning.pdf
Floorplanning.pdf
Ahmed Abdelazeem
 
Implementing Useful Clock Skew Using Skew Groups
Implementing Useful Clock Skew Using Skew GroupsImplementing Useful Clock Skew Using Skew Groups
Implementing Useful Clock Skew Using Skew Groups
M Mei
 
Power Gating
Power GatingPower Gating
Power Gating
Mahesh Dananjaya
 
Timing closure document
Timing closure documentTiming closure document
Timing closure document
Alan Tran
 
Physical design-complete
Physical design-completePhysical design-complete
Physical design-complete
Murali Rai
 
Vlsi physical design (Back End Process)
Vlsi physical design (Back End Process)Vlsi physical design (Back End Process)
Vlsi physical design (Back End Process)
CHENCHU CHANDU PRASANTH NADELLA
 
Placement in VLSI Design
Placement in VLSI DesignPlacement in VLSI Design
Placement in VLSI Design
Team-VLSI-ITMU
 
VLSI-Physical Design- Tool Terminalogy
VLSI-Physical Design- Tool TerminalogyVLSI-Physical Design- Tool Terminalogy
VLSI-Physical Design- Tool Terminalogy
Murali Rai
 
Clock Tree Synthesis.pdf
Clock Tree Synthesis.pdfClock Tree Synthesis.pdf
Clock Tree Synthesis.pdf
Ahmed Abdelazeem
 
Placement
PlacementPlacement
Placement
yogesh kumar
 
STA vs DTA.pptx
STA vs DTA.pptxSTA vs DTA.pptx
STA vs DTA.pptx
Payal Dwivedi
 
Multi mode multi corner (mmmc)
Multi mode multi corner (mmmc)Multi mode multi corner (mmmc)
Multi mode multi corner (mmmc)
shaik sharief
 
Floorplan (http://www.vlsisystemdesign.com/PD-Flow.php)
Floorplan (http://www.vlsisystemdesign.com/PD-Flow.php)Floorplan (http://www.vlsisystemdesign.com/PD-Flow.php)
Floorplan (http://www.vlsisystemdesign.com/PD-Flow.php)
VLSI SYSTEM Design
 
Place decap
Place decapPlace decap
Place decap
VLSI SYSTEM Design
 

More Related Content

What's hot

Static_Time_Analysis.pptx
Static_Time_Analysis.pptxStatic_Time_Analysis.pptx
Static_Time_Analysis.pptx
Ahmed Abdelazeem
 
Physical Design Flow Challenges at 28nm on Multi-million Gate Blocks
Physical Design Flow Challenges at 28nm on Multi-million Gate BlocksPhysical Design Flow Challenges at 28nm on Multi-million Gate Blocks
Physical Design Flow Challenges at 28nm on Multi-million Gate Blocks
eInfochips (An Arrow Company)
 
Eco
EcoEco
Eco
Rajesh M
 
Understanding cts log_messages
Understanding cts log_messagesUnderstanding cts log_messages
Understanding cts log_messages
Mujahid Mohammed
 
Physical design
Physical design Physical design
Physical design
Manjunath hosmani
 
Back end[1] debdeep
Back end[1] debdeepBack end[1] debdeep
Back end[1] debdeep
Sandeep Patil
 
Routing.pdf
Routing.pdfRouting.pdf
Routing.pdf
Ahmed Abdelazeem
 
1. Introduction to PnR.pptx
1. Introduction to PnR.pptx1. Introduction to PnR.pptx
1. Introduction to PnR.pptx
Ahmed Abdelazeem
 
Floorplanning.pdf
Floorplanning.pdfFloorplanning.pdf
Floorplanning.pdf
Ahmed Abdelazeem
 
Implementing Useful Clock Skew Using Skew Groups
Implementing Useful Clock Skew Using Skew GroupsImplementing Useful Clock Skew Using Skew Groups
Implementing Useful Clock Skew Using Skew Groups
M Mei
 
Power Gating
Power GatingPower Gating
Power Gating
Mahesh Dananjaya
 
Timing closure document
Timing closure documentTiming closure document
Timing closure document
Alan Tran
 
Physical design-complete
Physical design-completePhysical design-complete
Physical design-complete
Murali Rai
 
Vlsi physical design (Back End Process)
Vlsi physical design (Back End Process)Vlsi physical design (Back End Process)
Vlsi physical design (Back End Process)
CHENCHU CHANDU PRASANTH NADELLA
 
Placement in VLSI Design
Placement in VLSI DesignPlacement in VLSI Design
Placement in VLSI Design
Team-VLSI-ITMU
 
VLSI-Physical Design- Tool Terminalogy
VLSI-Physical Design- Tool TerminalogyVLSI-Physical Design- Tool Terminalogy
VLSI-Physical Design- Tool Terminalogy
Murali Rai
 
Clock Tree Synthesis.pdf
Clock Tree Synthesis.pdfClock Tree Synthesis.pdf
Clock Tree Synthesis.pdf
Ahmed Abdelazeem
 
Placement
PlacementPlacement
Placement
yogesh kumar
 
STA vs DTA.pptx
STA vs DTA.pptxSTA vs DTA.pptx
STA vs DTA.pptx
Payal Dwivedi
 
Multi mode multi corner (mmmc)
Multi mode multi corner (mmmc)Multi mode multi corner (mmmc)
Multi mode multi corner (mmmc)
shaik sharief
 

What's hot (20)

Static_Time_Analysis.pptx
Static_Time_Analysis.pptxStatic_Time_Analysis.pptx
Static_Time_Analysis.pptx
 
Physical Design Flow Challenges at 28nm on Multi-million Gate Blocks
Physical Design Flow Challenges at 28nm on Multi-million Gate BlocksPhysical Design Flow Challenges at 28nm on Multi-million Gate Blocks
Physical Design Flow Challenges at 28nm on Multi-million Gate Blocks
 
Eco
EcoEco
Eco
 
Understanding cts log_messages
Understanding cts log_messagesUnderstanding cts log_messages
Understanding cts log_messages
 
Physical design
Physical design Physical design
Physical design
 
Back end[1] debdeep
Back end[1] debdeepBack end[1] debdeep
Back end[1] debdeep
 
Routing.pdf
Routing.pdfRouting.pdf
Routing.pdf
 
1. Introduction to PnR.pptx
1. Introduction to PnR.pptx1. Introduction to PnR.pptx
1. Introduction to PnR.pptx
 
Floorplanning.pdf
Floorplanning.pdfFloorplanning.pdf
Floorplanning.pdf
 
Implementing Useful Clock Skew Using Skew Groups
Implementing Useful Clock Skew Using Skew GroupsImplementing Useful Clock Skew Using Skew Groups
Implementing Useful Clock Skew Using Skew Groups
 
Power Gating
Power GatingPower Gating
Power Gating
 
Timing closure document
Timing closure documentTiming closure document
Timing closure document
 
Physical design-complete
Physical design-completePhysical design-complete
Physical design-complete
 
Vlsi physical design (Back End Process)
Vlsi physical design (Back End Process)Vlsi physical design (Back End Process)
Vlsi physical design (Back End Process)
 
Placement in VLSI Design
Placement in VLSI DesignPlacement in VLSI Design
Placement in VLSI Design
 
VLSI-Physical Design- Tool Terminalogy
VLSI-Physical Design- Tool TerminalogyVLSI-Physical Design- Tool Terminalogy
VLSI-Physical Design- Tool Terminalogy
 
Clock Tree Synthesis.pdf
Clock Tree Synthesis.pdfClock Tree Synthesis.pdf
Clock Tree Synthesis.pdf
 
Placement
PlacementPlacement
Placement
 
STA vs DTA.pptx
STA vs DTA.pptxSTA vs DTA.pptx
STA vs DTA.pptx
 
Multi mode multi corner (mmmc)
Multi mode multi corner (mmmc)Multi mode multi corner (mmmc)
Multi mode multi corner (mmmc)
 

Viewers also liked

Floorplan (http://www.vlsisystemdesign.com/PD-Flow.php)
Floorplan (http://www.vlsisystemdesign.com/PD-Flow.php)Floorplan (http://www.vlsisystemdesign.com/PD-Flow.php)
Floorplan (http://www.vlsisystemdesign.com/PD-Flow.php)
VLSI SYSTEM Design
 
Place decap
Place decapPlace decap
Place decap
VLSI SYSTEM Design
 
X$Tables And Sga Scanner, DOAG2009
X$Tables And Sga Scanner, DOAG2009X$Tables And Sga Scanner, DOAG2009
X$Tables And Sga Scanner, DOAG2009
Frank
 
Java 8 Streams And Common Operations By Harmeet Singh(Taara)
Java 8 Streams And Common Operations By Harmeet Singh(Taara)Java 8 Streams And Common Operations By Harmeet Singh(Taara)
Java 8 Streams And Common Operations By Harmeet Singh(Taara)
Harmeet Singh(Taara)
 
Buffer and scanner
Buffer and scannerBuffer and scanner
Buffer and scanner
Arif Ullah
 
java: basics, user input, data type, constructor
java: basics, user input, data type, constructorjava: basics, user input, data type, constructor
java: basics, user input, data type, constructor
Shivam Singhal
 
1 java - data type
1 java - data type1 java - data type
1 java - data type
vinay arora
 
Jnp
JnpJnp
Jnp
hj43us
 
Understanding java streams
Understanding java streamsUnderstanding java streams
Understanding java streams
Shahjahan Samoon
 
Java I/O
Java I/OJava I/O
Java I/O
Jussi Pohjolainen
 
Esoft Metro Campus - Certificate in java basics
Esoft Metro Campus - Certificate in java basicsEsoft Metro Campus - Certificate in java basics
Esoft Metro Campus - Certificate in java basics
Rasan Samarasinghe
 
Object-Oriented Analysis and Design
Object-Oriented Analysis and DesignObject-Oriented Analysis and Design
Object-Oriented Analysis and Design
RiazAhmad786
 
Structured Vs, Object Oriented Analysis and Design
Structured Vs, Object Oriented Analysis and DesignStructured Vs, Object Oriented Analysis and Design
Structured Vs, Object Oriented Analysis and Design
Motaz Saad
 
Vlsi interview questions1
Vlsi interview questions1Vlsi interview questions1
Vlsi interview questions1
SUKESH Prathap
 
Switching activity
Switching activitySwitching activity
Switching activity
VLSI SYSTEM Design
 
Object Oriented Analysis and Design
Object Oriented Analysis and DesignObject Oriented Analysis and Design
Object Oriented Analysis and Design
Haitham El-Ghareeb
 

Viewers also liked (16)

Floorplan (http://www.vlsisystemdesign.com/PD-Flow.php)
Floorplan (http://www.vlsisystemdesign.com/PD-Flow.php)Floorplan (http://www.vlsisystemdesign.com/PD-Flow.php)
Floorplan (http://www.vlsisystemdesign.com/PD-Flow.php)
 
Place decap
Place decapPlace decap
Place decap
 
X$Tables And Sga Scanner, DOAG2009
X$Tables And Sga Scanner, DOAG2009X$Tables And Sga Scanner, DOAG2009
X$Tables And Sga Scanner, DOAG2009
 
Java 8 Streams And Common Operations By Harmeet Singh(Taara)
Java 8 Streams And Common Operations By Harmeet Singh(Taara)Java 8 Streams And Common Operations By Harmeet Singh(Taara)
Java 8 Streams And Common Operations By Harmeet Singh(Taara)
 
Buffer and scanner
Buffer and scannerBuffer and scanner
Buffer and scanner
 
java: basics, user input, data type, constructor
java: basics, user input, data type, constructorjava: basics, user input, data type, constructor
java: basics, user input, data type, constructor
 
1 java - data type
1 java - data type1 java - data type
1 java - data type
 
Jnp
JnpJnp
Jnp
 
Understanding java streams
Understanding java streamsUnderstanding java streams
Understanding java streams
 
Java I/O
Java I/OJava I/O
Java I/O
 
Esoft Metro Campus - Certificate in java basics
Esoft Metro Campus - Certificate in java basicsEsoft Metro Campus - Certificate in java basics
Esoft Metro Campus - Certificate in java basics
 
Object-Oriented Analysis and Design
Object-Oriented Analysis and DesignObject-Oriented Analysis and Design
Object-Oriented Analysis and Design
 
Structured Vs, Object Oriented Analysis and Design
Structured Vs, Object Oriented Analysis and DesignStructured Vs, Object Oriented Analysis and Design
Structured Vs, Object Oriented Analysis and Design
 
Vlsi interview questions1
Vlsi interview questions1Vlsi interview questions1
Vlsi interview questions1
 
Switching activity
Switching activitySwitching activity
Switching activity
 
Object Oriented Analysis and Design
Object Oriented Analysis and DesignObject Oriented Analysis and Design
Object Oriented Analysis and Design
 

Similar to Define location of Preplaced cells(http://www.vlsisystemdesign.com/PD-Flow.php)

vlsi
vlsivlsi
vlsi
Jagathi Velpuri
 
lec23Concl.ppt
lec23Concl.pptlec23Concl.ppt
lec23Concl.ppt
BhuvanaEshwari1
 
Software Defined Data Centers - June 2012
Software Defined Data Centers - June 2012Software Defined Data Centers - June 2012
Software Defined Data Centers - June 2012
Brent Salisbury
 
MetroScientific Week 1.pptx
MetroScientific Week 1.pptxMetroScientific Week 1.pptx
MetroScientific Week 1.pptx
Bipin Saha
 
VLSI-mosfet-construction engineering ECE
VLSI-mosfet-construction engineering ECEVLSI-mosfet-construction engineering ECE
VLSI-mosfet-construction engineering ECE
jpradha86
 
CMOS Transistor
CMOS TransistorCMOS Transistor
CMOS Transistor
SubhamMukherjee33
 
Introduction to COMS VLSI Design
Introduction to COMS VLSI DesignIntroduction to COMS VLSI Design
Introduction to COMS VLSI Design
Eutectics
 
Ijetr011811
Ijetr011811Ijetr011811
Ijetr011811
ER Publication.org
 
CMOS Topic 6 -_designing_combinational_logic_circuits
CMOS Topic 6 -_designing_combinational_logic_circuitsCMOS Topic 6 -_designing_combinational_logic_circuits
CMOS Topic 6 -_designing_combinational_logic_circuits
Ikhwan_Fakrudin
 
Bicmos Technology - Overview
Bicmos Technology - OverviewBicmos Technology - Overview
Bicmos Technology - Overview
Ayush Mittal
 
CMOS VLSI PROJECT || CMOS 3-Bit Binary to Square of the given Input || MULTIP...
CMOS VLSI PROJECT || CMOS 3-Bit Binary to Square of the given Input || MULTIP...CMOS VLSI PROJECT || CMOS 3-Bit Binary to Square of the given Input || MULTIP...
CMOS VLSI PROJECT || CMOS 3-Bit Binary to Square of the given Input || MULTIP...
rameshreddybattini
 
VLSI DESIGN- MOS TRANSISTOR
VLSI DESIGN- MOS TRANSISTORVLSI DESIGN- MOS TRANSISTOR
VLSI DESIGN- MOS TRANSISTOR
Karthik Vivek
 
Khan and morrison_dq207
Khan and morrison_dq207Khan and morrison_dq207
Khan and morrison_dq207
Obsidian Software
 
VLSI-Module-3.pdf
VLSI-Module-3.pdfVLSI-Module-3.pdf
VLSI-Module-3.pdf
KarthiPoorni
 
Power
PowerPower
Power
AnimSarker
 
Ankita Gloria Kerketta (3)
Ankita Gloria Kerketta (3)Ankita Gloria Kerketta (3)
Ankita Gloria Kerketta (3)
rbvrfbv fbv gf
 
EC6601 VLSI Design CMOS Fabrication
EC6601 VLSI Design CMOS FabricationEC6601 VLSI Design CMOS Fabrication
EC6601 VLSI Design CMOS Fabrication
chitrarengasamy
 
OpenStack and OpenFlow Demos
OpenStack and OpenFlow DemosOpenStack and OpenFlow Demos
OpenStack and OpenFlow Demos
Brent Salisbury
 
vlsi dESIGN lETURE NOTES FOR ENGINEERING STUDENTS
vlsi dESIGN lETURE NOTES FOR ENGINEERING STUDENTSvlsi dESIGN lETURE NOTES FOR ENGINEERING STUDENTS
vlsi dESIGN lETURE NOTES FOR ENGINEERING STUDENTS
Niranjan Reddy
 
Asic backend design
Asic backend designAsic backend design
Asic backend design
kbipeen
 

Similar to Define location of Preplaced cells(http://www.vlsisystemdesign.com/PD-Flow.php) (20)

vlsi
vlsivlsi
vlsi
 
lec23Concl.ppt
lec23Concl.pptlec23Concl.ppt
lec23Concl.ppt
 
Software Defined Data Centers - June 2012
Software Defined Data Centers - June 2012Software Defined Data Centers - June 2012
Software Defined Data Centers - June 2012
 
MetroScientific Week 1.pptx
MetroScientific Week 1.pptxMetroScientific Week 1.pptx
MetroScientific Week 1.pptx
 
VLSI-mosfet-construction engineering ECE
VLSI-mosfet-construction engineering ECEVLSI-mosfet-construction engineering ECE
VLSI-mosfet-construction engineering ECE
 
CMOS Transistor
CMOS TransistorCMOS Transistor
CMOS Transistor
 
Introduction to COMS VLSI Design
Introduction to COMS VLSI DesignIntroduction to COMS VLSI Design
Introduction to COMS VLSI Design
 
Ijetr011811
Ijetr011811Ijetr011811
Ijetr011811
 
CMOS Topic 6 -_designing_combinational_logic_circuits
CMOS Topic 6 -_designing_combinational_logic_circuitsCMOS Topic 6 -_designing_combinational_logic_circuits
CMOS Topic 6 -_designing_combinational_logic_circuits
 
Bicmos Technology - Overview
Bicmos Technology - OverviewBicmos Technology - Overview
Bicmos Technology - Overview
 
CMOS VLSI PROJECT || CMOS 3-Bit Binary to Square of the given Input || MULTIP...
CMOS VLSI PROJECT || CMOS 3-Bit Binary to Square of the given Input || MULTIP...CMOS VLSI PROJECT || CMOS 3-Bit Binary to Square of the given Input || MULTIP...
CMOS VLSI PROJECT || CMOS 3-Bit Binary to Square of the given Input || MULTIP...
 
VLSI DESIGN- MOS TRANSISTOR
VLSI DESIGN- MOS TRANSISTORVLSI DESIGN- MOS TRANSISTOR
VLSI DESIGN- MOS TRANSISTOR
 
Khan and morrison_dq207
Khan and morrison_dq207Khan and morrison_dq207
Khan and morrison_dq207
 
VLSI-Module-3.pdf
VLSI-Module-3.pdfVLSI-Module-3.pdf
VLSI-Module-3.pdf
 
Power
PowerPower
Power
 
Ankita Gloria Kerketta (3)
Ankita Gloria Kerketta (3)Ankita Gloria Kerketta (3)
Ankita Gloria Kerketta (3)
 
EC6601 VLSI Design CMOS Fabrication
EC6601 VLSI Design CMOS FabricationEC6601 VLSI Design CMOS Fabrication
EC6601 VLSI Design CMOS Fabrication
 
OpenStack and OpenFlow Demos
OpenStack and OpenFlow DemosOpenStack and OpenFlow Demos
OpenStack and OpenFlow Demos
 
vlsi dESIGN lETURE NOTES FOR ENGINEERING STUDENTS
vlsi dESIGN lETURE NOTES FOR ENGINEERING STUDENTSvlsi dESIGN lETURE NOTES FOR ENGINEERING STUDENTS
vlsi dESIGN lETURE NOTES FOR ENGINEERING STUDENTS
 
Asic backend design
Asic backend designAsic backend design
Asic backend design
 

Recently uploaded

How to Make a Field Mandatory in Odoo 17
How to Make a Field Mandatory in Odoo 17How to Make a Field Mandatory in Odoo 17
How to Make a Field Mandatory in Odoo 17
Celine George
 
Chapter wise All Notes of First year Basic Civil Engineering.pptx
Chapter wise All Notes of First year Basic Civil Engineering.pptxChapter wise All Notes of First year Basic Civil Engineering.pptx
Chapter wise All Notes of First year Basic Civil Engineering.pptx
Denish Jangid
 
Présentationvvvvvvvvvvvvvvvvvvvvvvvvvvvv2.pptx
Présentationvvvvvvvvvvvvvvvvvvvvvvvvvvvv2.pptxPrésentationvvvvvvvvvvvvvvvvvvvvvvvvvvvv2.pptx
Présentationvvvvvvvvvvvvvvvvvvvvvvvvvvvv2.pptx
siemaillard
 
BBR 2024 Summer Sessions Interview Training
BBR 2024 Summer Sessions Interview TrainingBBR 2024 Summer Sessions Interview Training
BBR 2024 Summer Sessions Interview Training
Katrina Pritchard
 
How to deliver Powerpoint Presentations.pptx
How to deliver Powerpoint Presentations.pptxHow to deliver Powerpoint Presentations.pptx
How to deliver Powerpoint Presentations.pptx
HajraNaeem15
 
Leveraging Generative AI to Drive Nonprofit Innovation
Leveraging Generative AI to Drive Nonprofit InnovationLeveraging Generative AI to Drive Nonprofit Innovation
Leveraging Generative AI to Drive Nonprofit Innovation
TechSoup
 
คำศัพท์ คำพื้นฐานการอ่าน ภาษาอังกฤษ ระดับชั้น ม.1
คำศัพท์ คำพื้นฐานการอ่าน ภาษาอังกฤษ ระดับชั้น ม.1คำศัพท์ คำพื้นฐานการอ่าน ภาษาอังกฤษ ระดับชั้น ม.1
คำศัพท์ คำพื้นฐานการอ่าน ภาษาอังกฤษ ระดับชั้น ม.1
สมใจ จันสุกสี
 
How to Fix the Import Error in the Odoo 17
How to Fix the Import Error in the Odoo 17How to Fix the Import Error in the Odoo 17
How to Fix the Import Error in the Odoo 17
Celine George
 
MARY JANE WILSON, A “BOA MÃE” .
MARY JANE WILSON, A “BOA MÃE” .MARY JANE WILSON, A “BOA MÃE” .
MARY JANE WILSON, A “BOA MÃE” .
Colégio Santa Teresinha
 
Liberal Approach to the Study of Indian Politics.pdf
Liberal Approach to the Study of Indian Politics.pdfLiberal Approach to the Study of Indian Politics.pdf
Liberal Approach to the Study of Indian Politics.pdf
WaniBasim
 
writing about opinions about Australia the movie
writing about opinions about Australia the moviewriting about opinions about Australia the movie
writing about opinions about Australia the movie
Nicholas Montgomery
 
clinical examination of hip joint (1).pdf
clinical examination of hip joint (1).pdfclinical examination of hip joint (1).pdf
clinical examination of hip joint (1).pdf
Priyankaranawat4
 
Pengantar Penggunaan Flutter - Dart programming language1.pptx
Pengantar Penggunaan Flutter - Dart programming language1.pptxPengantar Penggunaan Flutter - Dart programming language1.pptx
Pengantar Penggunaan Flutter - Dart programming language1.pptx
Fajar Baskoro
 
Hindi varnamala | hindi alphabet PPT.pdf
Hindi varnamala | hindi alphabet PPT.pdfHindi varnamala | hindi alphabet PPT.pdf
Hindi varnamala | hindi alphabet PPT.pdf
Dr. Mulla Adam Ali
 
The History of Stoke Newington Street Names
The History of Stoke Newington Street NamesThe History of Stoke Newington Street Names
The History of Stoke Newington Street Names
History of Stoke Newington
 
ANATOMY AND BIOMECHANICS OF HIP JOINT.pdf
ANATOMY AND BIOMECHANICS OF HIP JOINT.pdfANATOMY AND BIOMECHANICS OF HIP JOINT.pdf
ANATOMY AND BIOMECHANICS OF HIP JOINT.pdf
Priyankaranawat4
 
RHEOLOGY Physical pharmaceutics-II notes for B.pharm 4th sem students
RHEOLOGY Physical pharmaceutics-II notes for B.pharm 4th sem studentsRHEOLOGY Physical pharmaceutics-II notes for B.pharm 4th sem students
RHEOLOGY Physical pharmaceutics-II notes for B.pharm 4th sem students
Himanshu Rai
 
BÀI TẬP DẠY THÊM TIẾNG ANH LỚP 7 CẢ NĂM FRIENDS PLUS SÁCH CHÂN TRỜI SÁNG TẠO ...
BÀI TẬP DẠY THÊM TIẾNG ANH LỚP 7 CẢ NĂM FRIENDS PLUS SÁCH CHÂN TRỜI SÁNG TẠO ...BÀI TẬP DẠY THÊM TIẾNG ANH LỚP 7 CẢ NĂM FRIENDS PLUS SÁCH CHÂN TRỜI SÁNG TẠO ...
BÀI TẬP DẠY THÊM TIẾNG ANH LỚP 7 CẢ NĂM FRIENDS PLUS SÁCH CHÂN TRỜI SÁNG TẠO ...
Nguyen Thanh Tu Collection
 
PIMS Job Advertisement 2024.pdf Islamabad
PIMS Job Advertisement 2024.pdf IslamabadPIMS Job Advertisement 2024.pdf Islamabad
PIMS Job Advertisement 2024.pdf Islamabad
AyyanKhan40
 
Your Skill Boost Masterclass: Strategies for Effective Upskilling
Your Skill Boost Masterclass: Strategies for Effective UpskillingYour Skill Boost Masterclass: Strategies for Effective Upskilling
Your Skill Boost Masterclass: Strategies for Effective Upskilling
Excellence Foundation for South Sudan
 

Recently uploaded (20)

How to Make a Field Mandatory in Odoo 17
How to Make a Field Mandatory in Odoo 17How to Make a Field Mandatory in Odoo 17
How to Make a Field Mandatory in Odoo 17
 
Chapter wise All Notes of First year Basic Civil Engineering.pptx
Chapter wise All Notes of First year Basic Civil Engineering.pptxChapter wise All Notes of First year Basic Civil Engineering.pptx
Chapter wise All Notes of First year Basic Civil Engineering.pptx
 
Présentationvvvvvvvvvvvvvvvvvvvvvvvvvvvv2.pptx
Présentationvvvvvvvvvvvvvvvvvvvvvvvvvvvv2.pptxPrésentationvvvvvvvvvvvvvvvvvvvvvvvvvvvv2.pptx
Présentationvvvvvvvvvvvvvvvvvvvvvvvvvvvv2.pptx
 
BBR 2024 Summer Sessions Interview Training
BBR 2024 Summer Sessions Interview TrainingBBR 2024 Summer Sessions Interview Training
BBR 2024 Summer Sessions Interview Training
 
How to deliver Powerpoint Presentations.pptx
How to deliver Powerpoint Presentations.pptxHow to deliver Powerpoint Presentations.pptx
How to deliver Powerpoint Presentations.pptx
 
Leveraging Generative AI to Drive Nonprofit Innovation
Leveraging Generative AI to Drive Nonprofit InnovationLeveraging Generative AI to Drive Nonprofit Innovation
Leveraging Generative AI to Drive Nonprofit Innovation
 
คำศัพท์ คำพื้นฐานการอ่าน ภาษาอังกฤษ ระดับชั้น ม.1
คำศัพท์ คำพื้นฐานการอ่าน ภาษาอังกฤษ ระดับชั้น ม.1คำศัพท์ คำพื้นฐานการอ่าน ภาษาอังกฤษ ระดับชั้น ม.1
คำศัพท์ คำพื้นฐานการอ่าน ภาษาอังกฤษ ระดับชั้น ม.1
 
How to Fix the Import Error in the Odoo 17
How to Fix the Import Error in the Odoo 17How to Fix the Import Error in the Odoo 17
How to Fix the Import Error in the Odoo 17
 
MARY JANE WILSON, A “BOA MÃE” .
MARY JANE WILSON, A “BOA MÃE” .MARY JANE WILSON, A “BOA MÃE” .
MARY JANE WILSON, A “BOA MÃE” .
 
Liberal Approach to the Study of Indian Politics.pdf
Liberal Approach to the Study of Indian Politics.pdfLiberal Approach to the Study of Indian Politics.pdf
Liberal Approach to the Study of Indian Politics.pdf
 
writing about opinions about Australia the movie
writing about opinions about Australia the moviewriting about opinions about Australia the movie
writing about opinions about Australia the movie
 
clinical examination of hip joint (1).pdf
clinical examination of hip joint (1).pdfclinical examination of hip joint (1).pdf
clinical examination of hip joint (1).pdf
 
Pengantar Penggunaan Flutter - Dart programming language1.pptx
Pengantar Penggunaan Flutter - Dart programming language1.pptxPengantar Penggunaan Flutter - Dart programming language1.pptx
Pengantar Penggunaan Flutter - Dart programming language1.pptx
 
Hindi varnamala | hindi alphabet PPT.pdf
Hindi varnamala | hindi alphabet PPT.pdfHindi varnamala | hindi alphabet PPT.pdf
Hindi varnamala | hindi alphabet PPT.pdf
 
The History of Stoke Newington Street Names
The History of Stoke Newington Street NamesThe History of Stoke Newington Street Names
The History of Stoke Newington Street Names
 
ANATOMY AND BIOMECHANICS OF HIP JOINT.pdf
ANATOMY AND BIOMECHANICS OF HIP JOINT.pdfANATOMY AND BIOMECHANICS OF HIP JOINT.pdf
ANATOMY AND BIOMECHANICS OF HIP JOINT.pdf
 
RHEOLOGY Physical pharmaceutics-II notes for B.pharm 4th sem students
RHEOLOGY Physical pharmaceutics-II notes for B.pharm 4th sem studentsRHEOLOGY Physical pharmaceutics-II notes for B.pharm 4th sem students
RHEOLOGY Physical pharmaceutics-II notes for B.pharm 4th sem students
 
BÀI TẬP DẠY THÊM TIẾNG ANH LỚP 7 CẢ NĂM FRIENDS PLUS SÁCH CHÂN TRỜI SÁNG TẠO ...
BÀI TẬP DẠY THÊM TIẾNG ANH LỚP 7 CẢ NĂM FRIENDS PLUS SÁCH CHÂN TRỜI SÁNG TẠO ...BÀI TẬP DẠY THÊM TIẾNG ANH LỚP 7 CẢ NĂM FRIENDS PLUS SÁCH CHÂN TRỜI SÁNG TẠO ...
BÀI TẬP DẠY THÊM TIẾNG ANH LỚP 7 CẢ NĂM FRIENDS PLUS SÁCH CHÂN TRỜI SÁNG TẠO ...
 
PIMS Job Advertisement 2024.pdf Islamabad
PIMS Job Advertisement 2024.pdf IslamabadPIMS Job Advertisement 2024.pdf Islamabad
PIMS Job Advertisement 2024.pdf Islamabad
 
Your Skill Boost Masterclass: Strategies for Effective Upskilling
Your Skill Boost Masterclass: Strategies for Effective UpskillingYour Skill Boost Masterclass: Strategies for Effective Upskilling
Your Skill Boost Masterclass: Strategies for Effective Upskilling
 

Define location of Preplaced cells(http://www.vlsisystemdesign.com/PD-Flow.php)

  • 1. Let us assume, the below are the dimensions of the chip Die Core www.vlsisystemdesign.com
  • 2. Let’s explore how a city is planned www.vlsisystemdesign.com
  • 3. Let’s explore how a city is planned Railway Hospital Station Water Playground Storage Tank www.vlsisystemdesign.com
  • 4. Basic necessities and utilities are pre-planned and positioned, in a manner to have the best reachability by each citizen Railway Hospital Station Water Playground Storage Tank www.vlsisystemdesign.com
  • 5. In a similar fashion, we start planning the chip area, by prioritizing the location of critical cells. Die Core www.vlsisystemdesign.com
  • 6. Crtical cells can be IP’s (memories, ALU, etc.) or std cells (clock Buffer, clock inverter, etc ) Die Core www.vlsisystemdesign.com
  • 7. Let us understand, what are IP’s, std cells and their architecture? Die Core www.vlsisystemdesign.com
  • 8. IP is a reusable unit of logic, cell, or chip layout design that is the intellectual property designed by any individual.  IP are also sometimes offered as generic gate-level netlist. i.e. standard cells, and complex cells.  It consists of transistor level layout for logical cells and complex cells, which are implemented using layout tools.  Lets have a look into internal of IP’s www.vlsisystemdesign.com
  • 9. Consider one of the most commonly used IP i.e. CMOS Inverter Vdd Vdd In Inverter Out In Out Vss Vss www.vlsisystemdesign.com
  • 10. CMOS Inverter consist of P-MOS Transistor Vdd PMOS – P Diff In Out Vss www.vlsisystemdesign.com
  • 11. CMOS Inverter consist of N-MOS Transistor Vdd PMOS – P Diff In Out NMOS – N Diff Vss www.vlsisystemdesign.com
  • 12. CMOS Inverter consist of Polysilicon Gate. Vdd Poly Gate PMOS – P Diff In Out NMOS – N Diff Vss Note : At the component level, polysilicon has been used as the conducting gate material in MOSFET and CMOS processing technologies. www.vlsisystemdesign.com
  • 13. CMOS Inverter IN/ OUT Lines Vdd Poly Gate PMOS – P Diff In Out In NMOS – N Diff Vss www.vlsisystemdesign.com
  • 14. CMOS Inverter IN/ OUT Ports Vdd Poly Gate PMOS – P Diff In Out In Out NMOS – N Diff Vss www.vlsisystemdesign.com
  • 15. CMOS Inverter Vdd & Vss Ports. Vdd Vdd Poly Gate PMOS – P Diff In Out In Out NMOS – N Diff Vss Vss www.vlsisystemdesign.com
  • 16. Lets draw preliminary layout of inverter using stick diagram www.vlsisystemdesign.com
  • 17. Lets draw preliminary layout of inverter using stick diagram Stick Diagrams are useful for planning the layout and routing of integrated circuits. Every Line of a conducting material layer is represented by a line of a distinct color. www.vlsisystemdesign.com
  • 18. Lets draw preliminary layout of inverter using stick diagram Stick Diagrams are useful for planning the layout and routing of integrated circuits. Every Line of a conducting material layer is represented by a line of a distinct color. Polysilicon Gate P Diffusion N Diffusion Metal Contact www.vlsisystemdesign.com
  • 19. P-MOS Transistor represented by Bottle Green Color line PMOS – P Diff P Diff www.vlsisystemdesign.com
  • 20. N-MOS Transistor represented by a Apple Green Color line PMOS – P Diff P Diff NMOS – N Diff N Diff www.vlsisystemdesign.com
  • 21. Polysilicon gates represented by Brown Color line Poly Gate Poly PMOS – P Diff P Diff NMOS – N Diff N Diff www.vlsisystemdesign.com
  • 22. Metal is represented by Bottle Blue Color line Poly Gate Poly PMOS – P Diff P Diff In In NMOS – N Diff N Diff www.vlsisystemdesign.com
  • 23. Contacts are represented by Black Cross Poly Gate Poly PMOS – P Diff P Diff In In NMOS – N Diff N Diff = Contact www.vlsisystemdesign.com
  • 24. Metal is represented by Bottle Blue Color line Poly Gate Poly PMOS – P Diff P Diff In Out In Out NMOS – N Diff N Diff = Contact www.vlsisystemdesign.com
  • 25. Contacts are represented by Black Cross Poly Gate Poly PMOS – P Diff P Diff In Out In Out NMOS – N Diff N Diff = Contact www.vlsisystemdesign.com
  • 26. Metal is represented by Bottle Blue Color line Vdd Vdd Poly Gate Poly PMOS – P Diff P Diff In Out In Out NMOS – N Diff N Diff Vss Vss = Contact www.vlsisystemdesign.com
  • 27. Metal is represented by Bottle Blue Color line Vdd Vdd Poly Gate Poly PMOS – P Diff P Diff In Out In Out NMOS – N Diff N Diff Vss Vss = Contact www.vlsisystemdesign.com
  • 28. Stick Diagrams are converted to Cell Layout by assigning length and width to the Wire Vdd Vdd Poly Poly P Diff P Diff In Out In Out N Diff N Diff Vss Vss = Contact = Contact www.vlsisystemdesign.com
  • 29. Stick Diagrams are converted to Cell Layout by assigning length and width to the Wire Vdd Width (w) Poly P Diff In Out N Diff Vss = Contact www.vlsisystemdesign.com
  • 30. Stick Diagrams are converted to Cell Layout by assigning length and width to the Wire Vdd Width (w) Length (L) Poly P Diff In Out N Diff Vss = Contact www.vlsisystemdesign.com
  • 31. Cell Layout is a Black Box for IP User. Vdd Vdd Width (w) Length (L) Poly Poly P Diff P Diff In Out In Out N Diff N Diff Vss Vss = Contact = Contact www.vlsisystemdesign.com
  • 32. In Black Box, internal architecture counts less compared to IP Functionality Vdd Vdd Poly Poly P Diff P Diff In Out In Out N Diff N Diff Vss Vss = Contact = Contact www.vlsisystemdesign.com
  • 33. IP’s serves the purpose of the Circuit design i.e. Inverter in this case Vdd Vdd Poly P Diff In Out In Out N Diff Vss Vss = Contact www.vlsisystemdesign.com
  • 34. Similarly, other IP’s available as blocks : www.vlsisystemdesign.com
  • 35. Similarly, other IP’s available as blocks : Vdd In1 AND Out In2 Vss www.vlsisystemdesign.com
  • 36. Similarly, other IP’s available as blocks : Vdd Vdd In1 In1 AND Out OR Out In2 In2 Vss Vss www.vlsisystemdesign.com
  • 37. Similarly, other IP’s available as blocks : Vdd Vdd Vdd In1 In1 In1 AND Out OR Out NAND Out In2 In2 In2 Vss Vss Vss www.vlsisystemdesign.com
  • 38. Complex blocks are also offered as IP’s www.vlsisystemdesign.com
  • 39. Complex blocks are also offered as IP’s Vdd In Out Vss www.vlsisystemdesign.com
  • 40. Complex blocks are also offered as IP’s Buffer is nothing but two inverters connected back-to-back Vdd In Out Vss www.vlsisystemdesign.com
  • 41. Complex blocks are also offered as IP’s Buffer is nothing but two inverters connected back-to-back Vdd Vdd Vdd In Out In Out Vss Vss Vss www.vlsisystemdesign.com
  • 42. Complex blocks are also offered as IP’s Buffer is nothing but two inverters connected back-to-back Vdd Vdd In Out Vss Vss www.vlsisystemdesign.com
  • 43. Complex blocks are also offered as IP’s Buffer is nothing but two inverters connected back-to-back Vdd Vdd Vdd Vdd Poly Poly P Diff P Diff In Out In In Out Out N Diff N Diff Vss Vss www.vlsisystemdesign.com
  • 44. Complex blocks are also offered as IP’s Buffer is nothing but two inverters connected back-to-back Vdd Vdd Vdd In Out In Buffer Out Vss Vss Vss www.vlsisystemdesign.com
  • 45. IP’s are offered in form of rectangular/square boxes www.vlsisystemdesign.com
  • 46. IP’s are offered in form of rectangular/square boxes For E.g. The Buffer IP, will be represented as below www.vlsisystemdesign.com
  • 47. IP’s are offered in form of rectangular/square boxes For E.g. The Buffer IP, will be represented as below Vdd In Buffer Out Buffer Vss www.vlsisystemdesign.com
  • 48. IP’s are offered in form of rectangular/square boxes For E.g. The AND Gate IP, will be represented as below www.vlsisystemdesign.com
  • 49. IP’s are offered in form of rectangular/square boxes For E.g. The AND Gate IP, will be represented as below Vdd In1 AND Out AND In2 Vss www.vlsisystemdesign.com
  • 50. Commonly asked Question How do we differentiate between Vdd and Vss ? www.vlsisystemdesign.com
  • 51. Commonly asked Question How do we differentiate between Vdd and Vss ? It is represented in below pattern. A Cross line on the bottom left of the Block represents Vss and top corner Vdd www.vlsisystemdesign.com
  • 52. Commonly asked Question How do we differentiate between Vdd and Vss ? It is represented in below pattern. A Cross line on the bottom left of the Block represents Vss and top corner Vdd Vdd Buffer Buffer Vss Vdd AND AND Vss www.vlsisystemdesign.com
  • 53. Complex blocks e.g. ALU ALU www.vlsisystemdesign.com
  • 54. Complex blocks e.g. ALU will be represented as below IP Block ALU www.vlsisystemdesign.com
  • 55. • Memory is also a Complex IP used commonly. • It is necessary to pre-define the geometrical location of these IP’s on a chip, so that the automated PNR tools do not modify their locations • These cells are referred to as Pre-placed cells www.vlsisystemdesign.com
  • 56. Die Core www.vlsisystemdesign.com
  • 57. Block a Die Core www.vlsisystemdesign.com
  • 58. Block a Block b Die Core www.vlsisystemdesign.com
  • 59. Block a Block b Block c Die Core www.vlsisystemdesign.com
  • 60. Block a Block b Pre-placed Cells Block c Die Core www.vlsisystemdesign.com
  • 61. Thus we have defined the Location of Pre-placed Cell in Chip Block a Block b Pre-placed Cells Block c Die Core www.vlsisystemdesign.com