Define location of Preplaced cells(http://www.vlsisystemdesign.com/PD-Flow.php)

Let us assume, the below are the dimensions of the chip

Die

Core

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Let’s explore how a city is planned


Let’s explore how a city is planned

Railway
Hospital
Station

Water
Playground
Storage Tank


Basic necessities and utilities are pre-planned and positioned,
in a manner to have the best reachability by each citizen

Railway
Hospital
Station

Water
Playground
Storage Tank


In a similar fashion, we start planning the chip area, by prioritizing the location
of critical cells.

Die

Core


Crtical cells can be IP’s (memories, ALU, etc.) or std cells (clock Buffer, clock inverter, etc )

Die

Core


Let us understand, what are IP’s, std cells and their architecture?

Die

Core


IP is a reusable unit of logic, cell, or chip layout design that is the intellectual
property designed by any individual.

 IP are also sometimes offered as generic gate-level netlist. i.e. standard cells,
and complex cells.

 It consists of transistor level layout for logical cells and complex cells, which
are implemented using layout tools.

 Lets have a look into internal of IP’s


Consider one of the most commonly used IP i.e. CMOS Inverter

Vdd Vdd

In Inverter Out In Out

Vss Vss


CMOS Inverter consist of P-MOS Transistor

Vdd

PMOS – P Diff

In Out

Vss


CMOS Inverter consist of N-MOS Transistor

Vdd

PMOS – P Diff

In Out

NMOS – N Diff

Vss


CMOS Inverter consist of Polysilicon Gate.

Vdd
Poly Gate
PMOS – P Diff

In Out

NMOS – N Diff

Vss

Note : At the component level, polysilicon has been used as the conducting gate
material in MOSFET and CMOS processing technologies.

CMOS Inverter IN/ OUT Lines

Vdd
Poly Gate
PMOS – P Diff

In Out In

NMOS – N Diff

Vss


CMOS Inverter IN/ OUT Ports

Vdd
Poly Gate
PMOS – P Diff

In Out In Out

NMOS – N Diff

Vss


CMOS Inverter Vdd & Vss Ports.

Vdd

Vdd
Poly Gate
PMOS – P Diff

In Out In Out

NMOS – N Diff

Vss
Vss


Lets draw preliminary layout of inverter using stick diagram



Stick Diagrams are useful for planning the layout and routing of integrated circuits.

Every Line of a conducting material layer is represented by a line of a distinct color.



Stick Diagrams are useful for planning the layout and routing of integrated circuits.

Every Line of a conducting material layer is represented by a line of a distinct color.

Polysilicon Gate

P Diffusion

N Diffusion

Metal

Contact


P-MOS Transistor represented by Bottle Green Color line

PMOS – P Diff P Diff


N-MOS Transistor represented by a Apple Green Color line


NMOS – N Diff N Diff


Polysilicon gates represented by Brown Color line

Poly Gate Poly



Metal is represented by Bottle Blue Color line

Poly Gate Poly

In In



Contacts are represented by Black Cross

Poly Gate Poly

In In


= Contact



Poly Gate Poly

In Out In Out


= Contact


Contacts are represented by Black Cross

Poly Gate Poly

In Out In Out


= Contact



Vdd Vdd

Poly Gate Poly

In Out In Out


Vss Vss

= Contact


Stick Diagrams are converted to Cell Layout by assigning length and width to the Wire

Vdd Vdd

Poly Poly
P Diff P Diff

In Out In Out

N Diff N Diff

Vss Vss

= Contact = Contact



Vdd
Width (w)

Poly
P Diff

In Out

N Diff

Vss

= Contact



Vdd
Width (w)
Length (L)
Poly
P Diff

In Out

N Diff

Vss

= Contact


Cell Layout is a Black Box for IP User.

Vdd
Vdd
Width (w)
Length (L)
Poly Poly
P Diff P Diff

In Out In Out

N Diff N Diff

Vss

Vss
= Contact = Contact


In Black Box, internal architecture counts less compared to IP Functionality

Vdd Vdd

Poly Poly
P Diff P Diff

In Out In Out

N Diff N Diff

Vss Vss
= Contact = Contact


IP’s serves the purpose of the Circuit design
i.e. Inverter in this case
Vdd

Vdd
Poly
P Diff

In Out In Out

N Diff

Vss

Vss
= Contact


Similarly, other IP’s available as blocks :



Vdd

In1
AND Out
In2

Vss



Vdd Vdd

In1 In1
AND Out OR Out
In2 In2

Vss Vss



Vdd Vdd Vdd

In1 In1 In1
AND Out OR Out NAND Out
In2 In2 In2

Vss Vss Vss


Complex blocks are also offered as IP’s



Vdd

In Out

Vss



Buffer is nothing but two inverters connected back-to-back

Vdd

In Out

Vss




Vdd Vdd Vdd

In Out In Out

Vss Vss Vss




Vdd Vdd

In Out

Vss Vss




Vdd Vdd Vdd Vdd

Poly Poly
P Diff P Diff
In Out In In Out Out
N Diff N Diff

Vss Vss




Vdd Vdd Vdd

In Out In Buffer Out

Vss Vss Vss


IP’s are offered in form of rectangular/square boxes


For E.g. The Buffer IP, will be represented as below


For E.g. The Buffer IP, will be represented as below

Vdd

In Buffer Out Buffer

Vss


For E.g. The AND Gate IP, will be represented as below


For E.g. The AND Gate IP, will be represented as below

Vdd

In1
AND Out AND
In2

Vss


Commonly asked Question
How do we differentiate between Vdd and Vss ?



It is represented in below pattern.
A Cross line on the bottom left of the Block represents Vss and top corner Vdd



It is represented in below pattern.
A Cross line on the bottom left of the Block represents Vss and top corner Vdd

Vdd

Buffer Buffer

Vss

Vdd

AND AND

Vss


Complex blocks e.g. ALU

ALU

Complex blocks e.g. ALU will be represented as below IP Block

ALU

• Memory is also a Complex IP used commonly.

• It is necessary to pre-define the geometrical location of these IP’s on a chip,
so that the automated PNR tools do not modify their locations

• These cells are referred to as Pre-placed cells


Die

Core


Block a

Die

Core


Block a Block b

Die

Core


Block a Block b

Block c

Die

Core


Block a Block b
Pre-placed
Cells
Block c

Die

Core


Thus we have defined the Location of Pre-placed Cell in Chip

Block a Block b
Pre-placed
Cells
Block c

Die

Core


Define location of Preplaced cells(http://www.vlsisystemdesign.com/PD-Flow.php)

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