The document describes designing and simulating various combinational circuits using Verilog HDL. It includes the design of an 8-bit adder, 4-bit multiplier, 3-to-8 address decoder, and 2-to-1 multiplexer. Verilog code and test benches are provided for each circuit. The circuits are simulated and waveforms are generated to verify the design and functionality.

1. Ex. No: 1 DESIGN AND SIMULATION OF COMBINATIONAL CIRCUITS
Date: USING VERILOG HDL
AIM:
To design the following combinational circuits using Verilog HDL and simulate them by
creating the test benches
a) 8 bit adder
b) 4 bit multiplier
c) 3 to 8 address decoder
d) 2 to 1 multiplexer
SOFTWARE REQUIRED:
·Xilinx 13.4 ISE– A project navigator software tool
PROCEDURE:
•Double click Xilinx ISE Design Suite 13.4 on the desktop or Go to Start–> All programs
–>Xilinx ISE Design Suite 13.4–>ISE Design tools.
•Click on File–>New project. A new project wizard will open. Type the name of the project
and select the location. The top-level source type should be selected as HDL. Click next.
•A new project wizard opens.
Product category :All
Family :Spartan 6
Device :XC6SLX45
Package :CSG324
Speed :-2
Top-level source type :HDL
Synthesis tool :XST(VHDL/Verilog)
Simulator :Isim(VHDL/Verilog)
Preferred language :Verilog
•Click next–>finish–>Right click on the project name shown in hierarchy and select new
source.
•New source wizard open. Select Verilog module and give program name as the file name
and click next and finish.
•Write the program and save it.
•In the process tab click on ‘+’ sign of synthesis and double click on check syntax.
•In the hierarchy tab right click on the program and select new source.
•In the opened new source wizard select Verilog test fixture and then give file name and click
next and select the associate source and click next and then finish.
•Write the test bench code save it and select the simulation in design tab.
•Select the test bench file in hierarchy tab and in process tab click on ‘+’ sign of Isim
simulator and double click on simulate behavioral model .The waveform displays.
•Save the waveform.
VLSI Lab Manual, Prepared by Komala Vani Challa, AP/ECE, VVCOE

2. CODING:
Date: a) 8 BIT ADDER
1 BIT ADDER
Verilog Code:
module fulladder(sum,carry,a,b,cin);
input a,b;
input cin;
output sum;
output carry;
assign sum=a^b^cin;
assign carry=((a&b)|(b&cin)|(cin&a));
endmodule
8 BIT ADDER
Verilog Code:
module adder8bit(sum,carry,a,b,cin);
input [7:0] a,b;
input cin;
output [7:0] sum;
output carry;
wire c1,c2,c3,c4,c5,c6,c7;
fulladder fa0(sum[0],c1,a[0],b[0],cin);
fulladder fa1(sum[1],c2,a[1],b[1],c1);
fulladder fa2(sum[2],c3,a[2],b[2],c2);
fulladder fa3(sum[3],c4,a[3],b[3],c3);
fulladder fa4(sum[4],c5,a[4],b[4],c4);
fulladder fa5(sum[5],c6,a[5],b[5],c5);
fulladder fa6(sum[6],c7,a[6],b[6],c6);
fulladder fa7(sum[7],carry,a[7],b[7],c7);
endmodule
Test Bench:
module fatb;
// Inputs
reg [7:0] a;
reg [7:0] b;
reg cin;
// Outputs
wire [7:0] sum;
wire carry;
// Instantiate the Unit Under Test (UUT)
fa8bit uut (
.sum(sum),
.carry(carry),
.a(a),
.b(b),
.cin(cin)
);
initial begin
VLSI Lab Manual, Prepared by Komala Vani Challa, AP/ECE, VVCOE

3. // Initialize Inputs
a=8'b00000001;b=8'b00000111;cin=1'b0;
$display("sum=%b,carry=%b",sum,carry);
#50 a=8'b00000001;b=8'b00000111;
$display("sum=%b,carry=%b",sum,carry);
#50 a=8'b01110001;b=8'b01100111;
$display("sum=%b,carry=%b",sum,carry);
#50 a=8'b11100001;b=8'b11000100;cin=1'b1;
$display("sum=%b,carry=%b",sum,carry);
#50 a=8'b00110001;b=8'b000011000;cin=1'b0;
$display("sum=%b,carry=%b",sum,carry);
#50 a=8'b10001001;b=8'b00110001;
$display("sum=%b,carry=%b",sum,carry);
#50 a=8'b11101101;b=8'b11111111;
$display("sum=%b,carry=%b",sum,carry);
#50 $finish;
end
endmodule
8-bit Adder Block Diagram
1-bit Full adder Logic Diagram:
Fig. Full adder
Waveform:
VLSI Lab Manual, Prepared by Komala Vani Challa, AP/ECE, VVCOE

4. Date: b) 4 BIT MULTIPLIER:
Verilog Code:
module mul4bit(a,b,out);
input [3:0] a;
input [3:0] b;
output [7:0] out;
reg [7:0] out;
always @ (a or b)
begin
out <= a*b;
end
endmodule
Testbench:
module multb;
// Inputs
reg [3:0] a;
reg [3:0] b;
// Outputs
wire [7:0] out;
// Instantiate the Unit Under Test (UUT)
mul4bit uut (
.a(a),
.b(b),
.out(out)
);
initial begin
a = 0;
b = 0;
// Wait 100 ns for global reset to finish
#100 $display("out=%b",out);
a=4'b0000;b=4'b1100;
#100 $display("out=%b",out);
a=4'b1000;
#100 $display("out=%b",out);
a=4'b1010;b=4'b0101;
#100 $display("out=%b",out);
#100 $finish;
end
endmodule
Waveform:
VLSI Lab Manual, Prepared by Komala Vani Challa, AP/ECE, VVCOE

5. Date: c) ADDRESS DECODER
3 to 8 Address Decoder Logic Diagram:
Fig.3 to 8 decoder
Verilog Code:
module decoder_3to8(Y7, Y6, Y5, Y4, Y3, Y2, Y1, Y0, A, B, C, en);
output Y7, Y6, Y5, Y4, Y3, Y2, Y1, Y0;
input A, B, C;
input en;
assign {Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0} = ( {en,A,B,C} == 4'b1000) ? 8'b1111_1110 :
( {en,A,B,C} == 4'b1001) ? 8'b1111_1101 :
( {en,A,B,C} == 4'b1010) ? 8'b1111_1011 :
( {en,A,B,C} == 4'b1011) ? 8'b1111_0111 :
( {en,A,B,C} == 4'b1100) ? 8'b1110_1111 :
( {en,A,B,C} == 4'b1101) ? 8'b1101_1111 :
( {en,A,B,C} == 4'b1110) ? 8'b1011_1111 :
( {en,A,B,C} == 4'b1111) ? 8'b0111_1111 :
8'b1111_1111;
endmodule
Testbench:
module Test_decoder_3to8;
wire Y7, Y6, Y5, Y4, Y3, Y2, Y1, Y0;
reg A, B, C;
reg en;
// Instantiate the Decoder (named DUT {device under test})
decoder_3to8 DUT(Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0, A, B, C, en);
initial begin
VLSI Lab Manual, Prepared by Komala Vani Challa, AP/ECE, VVCOE

6. $timeformat(-9, 1, " ns", 6); #1;
A = 1'b0; // time = 0
B = 1'b0;
C = 1'b0;
en = 1'b0;
#9;
en = 1'b1; // time = 10
#10;
A = 1'b0;
B = 1'b1;
C = 1'b0; // time = 20
#10;
A = 1'b1;
B = 1'b0;
C = 1'b0; // time = 30
#10;
A = 1'b1;
B = 1'b1;
C = 1'b0; // time = 40
#5;
en = 1'b0; // time = 45
#5;
end
always @(A or B or C or en)
$display("t=%t en=%b ABC=%b%b%b Y=%b%b%b%b%b%b%b%b",
$time,en,A,B,C,Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0);
endmodule
Waveform:
VLSI Lab Manual, Prepared by Komala Vani Challa, AP/ECE, VVCOE

7. Date: d) MULTIPLEXER
2 to 1 Multiplexer Logic Diagram:
Fig. 2 to 1 Mux
Verilog Code:
module mux(y,a,b,sel);
input [3:0] a,b;
input sel;
output [3:0] y;
reg [3:0] y;
always @(a or b or sel)
if (sel == 1'b0)
y=a;
else
y=b;
endmodule
Testbench:
module muxtb;
// Inputs
reg [3:0] a;
reg [3:0] b;
reg sel;
// Outputs
wire [3:0] y;
// Instantiate the Unit Under Test (UUT)
mux uut (
.y(y),
.a(a),
.b(b),
.sel(sel)
);
VLSI Lab Manual, Prepared by Komala Vani Challa, AP/ECE, VVCOE

8. initial begin
// Initialize Inputs
a = 0;
b = 0;
sel = 0;
// Wait 100 ns for global reset to finish
#100;
a=1111;b=0001;sel=0;
#100 $display("a=%b b=%b sel=%d y=%b",a,b,sel,y);
a=4'b1010;
#100 $display("a=%b b=%b sel=%d y=%b",a,b,sel,y);
sel=1;
#100 $display("a=%b b=%b sel=%d y=%b",a,b,sel,y);
b=1110;
#100 $display("a=%b b=%b sel=%d y=%b",a,b,sel,y);
sel=0;
#100 $finish;
end
endmodule
Waveform:
RESULT:
The Verilog code for combinational circuits were designed, simulated and waveforms were
generated using test bench.
VLSI Lab Manual, Prepared by Komala Vani Challa, AP/ECE, VVCOE