98788885 ic-lab-maual

IC APPLICATIONS LAB MANUAL
[TYPE THE COMPANY ADDRESS]
z

FOR

III BTECH, ECE-Ist SEMESTER

By

KUMAR GOUD.K
Asst.Professor

DEPARTMENT OF ELECTRONICS & COMMUNICATION
ENGINEERING

RVR INSTITUTE OF ENGINEERING & TECHNOLOGY
[Type text]

IC APPLICATION LAB MANUAL 2

IC APPLICATIONS LAB
III ECE (I SEM)
LIST OF EXPERIMENTS (As per JNTU Syllabus)

PART-1

1. Adder, Subtractor ,Comparator using IC 741 op-amp
2. Integrator and Differentiator using IC 741 op-amp
3. Active Filters – LPF, HPF(Butterworth second order)
4. RC phase shift ,Wein Bridge Oscillators using IC 741 op-amp
5. IC 555 Timer in Monostable Operation
6. Schmitt trigger Circuits using IC 741 and IC 555
7. IC 565 –PLL Applications
8. Voltage regulator using IC 723,three terminal voltage regulators-7805,7809,7912
9. Sample and Hold LF 398 IC

PART-2

1. D- Flip Flop(74LS74)and JK Master Slave Flip Flop (74LS73)
2. Decade Counter (74LS90)and UP-Down Counter (74LS192)
3. Universal Shift Register(74LS194/195)
4. 3-8 Decoder (74LS138)
5. 4-bit Comparator(74LS85)
6. 8×1 Multiplexer(74151) and 2×4 Demux(74155)
7. RAM (16×4)-74189(read and write operations)
8. Stack and Queue implementation using RAM,74189

RVR INSTITUTE OF ENGINEERING & TECHNOLOGY (IBRAHIM PATAN, HYDERABAD) Ω ECE Ω


IC APPLICATIONS LAB

DO’S DON’TS
1. Be regular to the lab. 1. Do not exceed the voltage Rating.
2. Follow proper Dress Code. 2. Do not inter change the IC’s while doing the
3. Maintain Silence. experiment.
4. Know the theory behind the experiment before 3. Avoid loose connections and short circuits.
coming to the lab. 4. Do not throw the connecting wires to floor.
5. Identify the different leads or terminals or pins of 5. Do not come late to the lab.
the IC before making connection. 6. Do not panic if you don’t get the output.
6. Know the Biasing Voltage required for different
families of IC’s and connect the power supply
voltage and ground terminals to the respective
pins of the IC’s.
7. Know the Current and Voltage rating of the IC’s
before using them in the experiment.
8. Avoid unnecessary talking while doing the
experiment.
9. Handle the IC Trainer Kit properly.
10. Mount the IC Properly on the IC Zif Socket.
11. Keep the Table clean.
12. Take a signature of the in charge before taking the
kit/components.
13. After the completion of the experiments switch
off the power supply and return the apparatus.
14. Arrange the chairs/stools and equipment properly
before leaving the lab.



1. ADDER, SUBTRACTOR, COMPARATOR USING IC 741 OP-AMP

AIM: To verify Adder, Subtractor, and Comparator using op-amp.

COMPONENTS REQUIRED:

Name of the
Specifications Quantity
Component/Equipment
IC 741 Refer Appendix A 1
Resistors 3.3 KΩ,2.2KΩ 1
Resistors 1KΩ 2
Resistor 10kΩ 4
Regulated Power Supply (0 – 30V),1A 2
Function Generator (0.1 – 1MHz),20Vp-p 1
Cathode Ray Oscilloscope (0 – 20MHz) 1
Multimeter 3 ½ digit display 1
Bread Board 1
Probes & Connecting wires

THEORY:

Adder: A two input summing amplifier may be constructed using the inverting mode. The adder can be
obtained by using either non-inverting mode or differential amplifier. Here the inverting mode is used. So
the inputs are applied through resistors to the inverting terminal and non-inverting terminal is grounded.
This is called “virtual ground”, i.e. the voltage at that terminal is zero. The gain of this summing amplifier is
1; any scale factor can be used for the inputs by selecting proper external resistors.

Subtractor: A basic differential amplifier can be used as a subtractor. If all resistors are equal in value then
output voltage can be derived by using superposition principle. To find V01 due to V1 alone make V2=0.Then
the circuit becomes a non inverting amplifier having input voltage V1/2 at the non inverting input terminal
and output becomes V01=V1/2[1+R/R]
=V1

Similarly the output V02 = -V2

Thus the output voltage V0 due to both the inputs can be written as V0= V01+V02

= V1-V2

Comparator: It is a circuit which compares a signal voltage applied at one input terminal of op-amp with a
known reference voltage at the other input. Non inverting comparator circuit is shown in figure. A fixed
reference voltage is applied to (-) input and time varying signal Vi is applied to (+) input.
The output voltage is at –Vsat for Vi<Vref.
And Vo goes to +Vsat for Vi>Vref.
The output waveform for a sin input signal applied to (+) input as shown.



CIRCUIT DIAGRAMS:

Fig1.1: Adder

Fig1.2: Subtractor

Fig1.3: Comparator



PROCEDURE:

Adder:

1. Connect the circuit as per the diagram shown in fig 1.1.

2. Apply the supply voltages of +15V to pin7 and -15V to pin4 of IC 741 respectively.

3. Apply the DC inputs V1 and V2.

4. Vary the input voltages and note down the corresponding outputs at pin 6 of the IC 741

5. Notice that the output is equal to the sum of the two inputs.

Subtractor:


2. Apply the supply voltages of +15V to pin7 and -15V to pin4 of IC741 respectively.

3. Apply the DC inputs V1 and V2.

4. Vary the input voltages and note down the corresponding output at pin 6 of the IC 741

5. Notice that the output is equal to the difference of two inputs

Comparator:


2. Apply the supply voltages of +15V to pin7 and -15V to pin4 of IC741 respectively.

3. Apply the input Vi as sin wave of 1k HZ, 10V p-p amplitude and Vref as show in fig1.3.

4. Note down the corresponding output at pin 6 of the IC 741.

5. Note down the Square wave output amplitudes.

OBSERVATION TABLES:

Adder:

i/p1 (v) i/p2(v) V0(v) practical V0(v) Theoretical



Subtractor:

i/p1 (v) i/p2(v) V0(v) Practical V0(v) Theoretical

COMPARATOR MODEL WAVE FORMS:

PRECAUTIONS:

1. Check the connections before giving the power supply.

2. Readings should be taken carefully.

RESULT:

VIVA VOCE QUESTIONS:

1. What is an op-amp?

2. What are the applications of op-amp?



2. INTEGRATOR & DIFFERENTIATOR USING IC741 OP-AMP

AIM: To verify Integrator and Differentiator using IC 741 op-amp.


Name of the
Component/Equipment
Capacitors 0.1µf, 0.01µf Each one
Resistors 159Ω, 1.5kΩ Each one
Function Generator (0.1 – 1MHz), 20V p-p 1
Bread Board 1

THEORY:

Integrator: In an integrator circuit, the output voltage is the integration of the input voltage. The output
t
voltage of an integrator is given by Vo = -1/R1Cf Vidt.
∫
0

At low frequencies the gain becomes infinite, so the capacitor is fully charged and behaves like an open
circuit. The gain of an integrator at low frequency can be limited by connecting a resistor in shunt with
capacitor.

Differentiator: In the differentiator circuit the output voltage is the differentiation of the input voltage. The
output voltage of a differentiator is given by Vo = - RfC1 dVin/df .The input impedance of this circuit
decreases with increase in frequency, thereby making the circuit sensitive to high frequency noise. At high
frequencies circuit may become unstable. For pin configuration and specifications of op amp (IC 741).



CIRCUIT DIAGRAMS:

Fig2.1: Integrator

Fig2.2: Differentiator

CALCULATIONS (Theoretical):

Integrator:

Choose T = 2πRfCf

Where T= Time period of the input signal

Assume Cf and find Rf

Select Rf = 10R1

t/2
Vo (p-p) = -1/ R1Cf ∫ Vi (p-p) dt
0



Differentiator

Select given frequency fa = 1/ (2π Rf C1), Assume C1 and find Rf

Select fb = 10 fa = 1/2π R1C1 and find R1

From R1C1 = Rf Cf, find Cf

PROCEDUER:

Integrator

1. Connect the circuit as per the diagram shown
2. Apply a square wave/sine input of 4V (p-p) of 1 KHz
3. Observe the o/p at pin 6.
4. Draw input and output waveforms as shown.
5. Observe that theoretical & practical values are equal.

Differentiator

1. Connect the circuit as per the diagram shown
2. Apply a square wave/sine input of 4V (p-p) of 1 KHz
3. Observe the output at pin 6
4. Draw the input and output waveforms as shown
5 Observe that theoretical & practical values are equal.

WAVE FORMS:

Integrator



Differentiator



OBSERVATION TABLES:

Integrator

Input –Square wave Output - Triangular
Amplitude(Vp-p) Time period Amplitude(Vp-p) Time period
(V) (ms) (V) (ms)

Input –sine wave Output - cosine
(V) (ms) (V) (ms)

Differentiator

Input –Square wave Output - Triangular
(V) (ms) (V) (ms)

Input –sine wave Output - cosine
(V) (ms) (V) (ms)

MODEL CALCULATIONS:

Integrator:

For T= 1 msec

fa = 1/T = 1 KHz

fa = 1 KHz = 1/(2πRfCf)

Assuming Cf= 0.1µf, Rf is found from Rf=1/(2π fa Cf)

Rf =1.59 KΩ

Rf = 10 R1

R1= 159Ω



Differentiator:

For T = 1 msec

f= 1/T = 1 KHz

fa = 1 KHz = 1/ (2πRfC1)

Assuming C1= 0.1µf, Rf is found from Rf=1/(2πfaC1)

Rf=1.59 KΩ

Fb = 10 fa = 1/2π R1C1

for C1= 0.1µf;

R1 =159Ω

PRECAUTIONS:


RESULT:


1. What is an op-amp?

2. What are the applications of op-amp?

3. What is meant by integrator and differentiator?



3. ACTIVE FILTERS – LPF, HPF (SECOND ORDER)

AIM: To obtain the frequency response of i) Second order Low Pass Filter (LPF)

ii) Second order High Pass Filter (HPF)


Name of the
Component/Equipment
Resistors 10kΩ 3
Resistors 3.3kΩ 2
Capacitors 0.01µf 2
Function Generator (1Hz – 1MHz) 1
Bread Board 1

THEORY:

a) LPF:

A LPF allows frequencies from 0 to higher cut of frequency fH. At fH the gain is 0.707 Amax, and after fH
gain decreases at a constant rate with an increase in frequency. The gain decreases 40dB each time the
frequency is increased by 10. Hence the rate at which the gain rolls off after fH is 40dB/decade or 12 dB/
octave, where octave signifies a two fold increase in frequency. The frequency f=fH is called the cut off
frequency because the gain of the filter at this frequency is down by 3 dB from 0 Hz. Other equivalent terms
for cut-off frequency are -3dB frequency, break frequency, or corner frequency.

b) HPF:

The frequency at which the magnitude of the gain is 0.707 times the maximum value of gain is called low
cut off frequency. Obviously, all frequencies higher than fL are pass band frequencies with the highest
frequency determined by the closed loop band width all of the op-amp.



CIRCUIT DIAGRAMS:

Fig 3.1: Low pass filter

Fig 3.2: High pass filter

DESIGN:

Assume pass band gain Av=2, Cut off frequency fc=5 KHz

1. Amplifier: Av=1+(Rf/R)=2 , then Rf=R, Choose Rf=R=10K
2. Filter Circuit: Cut off frequency fc=1/2II R1C1 = 5kHz
Choose C1=0.01uf then R1=3.3K



PROCEDURE:

1. Connections are made as shown in the circuit diagram

2. Apply sine wave i/p signal of peak amplitude 5 volts.

3. Check the gain of non-inverting amplifier by keeping the frequency of the input signal in the pass

band of the filter. Note down the output voltage Vo max.

4. Keeping the input signal amplitude constant, vary the frequency until the output voltage reduces to

0.707 Vo max, the corresponding frequency is the cut-off frequency (fc) of the filter.

To find the Roll-off factor:-

1. For LPF: - Keeping the input signal amplitude constant, adjust the input frequency at 10fc gives the
Roll-off factor.
2. For HPF: - Keeping the input signal amplitude constant, adjust the input frequency at 0.1fc note down
the output signal amplitude. The difference in the gain of the filter at fc and 0.1 fc gives the Roll-off
factor.

OBSERVATION TABLES:

High Pass Filter: - Vi(p-p) = Volts (Constant)

i/p frequency in(Hz) o/p Voltage Vo p-p (v) Gain magnitude Gain magnitude in
(Vo/Vi) db =20log(Vo/Vi)

Roll off = - (G1 - G2) db/decade =



Frequency Response for High Pass Filter:

Low Pass Filter: - Vi (p-p) = Volts (Constant)

i/p frequency in(Hz) o/p Voltage Vo p-p (v) Gain magnitude Gain magnitude in
(Vo/Vi) db =20log(Vo/Vi)

Roll off = - (G1-G2) db/decade =



Frequency Response for Low Pass Filter:

PRECAUTIONS:

3. VCC and VEE must be given to the corresponding pins.

RESULT:


1. What is meant by Low pass filter?
2. What is meant by High pass filter?
3. What is meant by Active filters?
4. How many types of filters are there?



4. RC PHASE SHIFT & WEIN BRIDGE OSCILLATORS

AIM: To Design a RC Phase Shift & Wein Bridge Oscillators of output frequency 200 Hz.

EQUIPMENTS AND COMPONENTS:

Name of apparatus& Component Specification Quantity

Resistor 3.3 KΩ 3
Resistor 33KΩ 2
Resistor 12KΩ 1
Variable Resistor 1.2MΩ,50KΩ Each one
Capacitor 0.1µf 3
Capacitor 0.05 µf 2
741 IC Refer Appendix -A 1
Bread Board 1
Dual Channel Power Supply (0-30V) 1
Connecting wires &Probes

CIRCUIT DIAGRAMS:

Fig 4.1: RC Phase shift Oscillator



Fig2: Wein Bridge Oscillator

THEORY:

RC Phase shift oscillator:

The op-amp is used in inverting mode and so it provides 1800 phase shift. The additional phase 1800deg
provided by RC feedback network to obtain total phase shift of 3600.The feedback network consists of three
identical RC stages. Each RC stage provides 600phase shift ,so that total phase shift provided by feed back
network is 1800. Here the gain of the inverting op-amp should be at least 29, or Rf = 29R1.Frequency of
oscillation fo = 1/ (2πRC 6)

Wien Bridge Oscillator:

It is a audio frequency oscillator. Feed back signal in this circuit is connected to non inverting input
terminal so that op-amp is working as a non inverting amplifier. So the feed back network need not provide
any phase shift. The circuit can be viewed as a Wein-Bride with a series RC network in one arm and parallel
RC network in ad joint arm.R1 and Rf are connected in the remaining two arms. Here Rf = 2R1.

CALCULATIONS (theoretical):

RC Phase shift Oscillator:

i. The frequency of oscillation fo is given by fo = 1/(2π )

ii. The gain Av at the above frequency must be at least 29 i.e Rf/R1=29

iii. fo= 200Hz

Let C = 0.1µf , Then R= 3.25K (choose 3.3k)

To prevent the loading of the amplifier because of RC networks it is necessary that

R1≥10R Therefore R1=10R=33 k Then Rf= 29 (33 k) = 957 k (choose Rf=1M)



Wein Bridge Oscillator:

The frequency of oscillation fo is exactly the resonant frequency of the balanced Wein Bridge and is given by

fo = 1/(2π )

The gain required for sustained oscillations is given by Av= 3. i.e., Rf=2R1

Let C = 0.05uf Then fo = 1/ (2π ) => R=3.3K

Now let R1=12K, then Rf =2R1=24K

Use Rf =50K potentiometer

PROCEDURE:

1. Construct the circuits as shown in the circuit diagrams.

2. Adjust the potentiometer Rf that an output wave form is obtained.

3. Calculate the output wave form frequency and peak to peak voltage

4. Compare the theoretical and practical values of the output waveform frequency

OBSERVATIONS:

1. The frequency of oscillation = ______ (RC Phase shift Oscillator)

2. The frequency of oscillation = ______ (Wein Bridge Oscillator)

MODEL WAVE FORMS:

RC Phase shift Oscillator:



Wein Bridge Oscillator:

RESULT:

1. The frequency of oscillation of the RC phase shift oscillator = --------Hz

2. The frequency of oscillation of the Wein Bridge oscillator = --------Hz

VIVA-VOICE:

1. State the two condition of oscillations
2. Classify the oscillators
3. What is the phase shift in case of the RC phase shift oscillator?
4. In phase shift oscillator what phase shift does the op-amp provide?
5. In what mode the op-amp is used in the phase shift oscillator?
6. What phase shift is provided by the feedback network?
7. What is the minimum gain that the inverting op-amp should have?
8. For high frequencies which kind of op-amp should be used?
9. What is the condition so that the oscillations will not die out?
10. In Wein bridge oscillator what phase shift does the op-amp provide?
11. In what mode the op-amp is used in the Wein bridge oscillator.



5. IC 555 TIMER-MONOSTABLE MULTIVIBRATOR

AIM: To generate a pulse from monostable multivibrator using IC555.


Name of the
Component/Equipment
IC 555 Refer Appendix B 1
Resistor 10kΩ 1
Capacitors 0.1µf,0.01µf Each one
Bread Board 1

THEORY:

A Monostable Multivibrator, often called a one-shot Multivibrator, is a pulse-generating circuit in which the
duration of the pulse is determined by the RC network connected externally to the 555 timer. In a stable or
stand by mode the output of the circuit is approximately Zero or at logic-low level. When an external trigger
pulse is obtained, the output is forced to go high (VCC). The time the output remains high is determined
by the external RC network connected to the timer. At the end of the timing interval, the output
automatically reverts back to its logic-low stable state. The output stays low until the trigger pulse is again
applied. Then the cycle repeats. The Monostable circuit has only one stable state (output low), hence the
name monostable. Normally the output of the Monostable Multivibrator is low. When the power supply
VCC is connected, the external timing capacitor ‘C” charges towards VCC with a time constant (RA+RB)
C. During this time, pin 3 is high (≈VCC) as Reset R=0, Set S=1 and this combination makes Q =0 which
has unclamped the timing capacitor ‘C’. For pin configuration and specifications, see Appendix-B



CIRCUIT DIAGRAMS:

Fig 5.1: Monostable Multivibrator using IC 555

Design:

Consider Vcc = 5V, for given tp

Output pulse width tp = 1.1 RAC

Assume C in the order of microfarads & Find RA

Model calculations:

If C=0.1 µF , RA = 10k then tp = 1.1 mSec

Trigger Voltage = 4V

PROCEDURE:

1. Connect the circuit as shown in the circuit diagram as shown in Fig.

2. Apply Negative triggering pulses at pin 2 of frequency 1 KHz as shown in Fig

3. Observe the output waveform and capacitor voltage as shown and measure the pulse duration.

4. Theoretically calculate the pulse duration as tp=1.1. RaC

5. Compare it with experimental values.



MODEL WAVEFORMS:

Fig 5.3 (a): Trigger signal (b): Output Voltage (c): Capacitor Voltage

Sample Readings:

Trigger Output wave Capacitor output
0 to 5V range 0 to 5V range 0 to 3.33 V range
1)1V,0.09msec 4.6V, 0.5msec 3V, 0.88 msec

PRECAUTIONS

Check the connections before giving the power supply.

Readings should be taken carefully.

RESULT:


1. What is meant by a multivibrator?
2. What is the other name for Mono Stable Multivibrator?
3. What is meant by a quasi stable state?
4. Monostable Multivibrator contains how many quasi stable states?



6. SCHMITT TRIGGER CIRCUITS USING IC 741 & 555

AIM: To verify the function of Schmitt trigger circuit using IC 741,555.


Name of the
Component/Equipment
IC 555 Refer Appendix B 1
Resistor 100 Ω 2
Resistor 56 KΩ 1
Resistor 100 KΩ 2
Capacitors 0.01µf 2
Multimeter 3 ½ digit display 1
Bread Board 1

THEORY:

Schmitt trigger circuit using IC 741

The circuit shows an inverting comparator with positive feed back. This circuit converts arbitrary wave
forms to a square wave or pulse. The circuit is known as the Schmitt trigger (or) squaring circuit. The input
voltage Vin changes the state of the output Vo every time it exceeds certain voltage levels called the upper
threshold voltage Vut and lower threshold voltage Vlt. When Vo = - Vsat, the voltage across R1 is referred to
as lower threshold voltage, Vlt. When Vo=+Vsat, the voltage across R1 is referred to as upper threshold
voltage Vut. The comparator with positive feed back is said to exhibit hysteresis, a dead band condition.

Schmitt trigger circuit using IC555

Apart from the timing functions, the two comparators of the 555 timer can be used independently for other
applications. One example is a Schmitt Trigger shown here. The two comparator inputs (pin 2 & 6) are tied
together and biased at 1/2 Vcc through a voltage divider R1 and R2.Since the threshold comparator will trip
at 2/3 Vcc and the trigger comparator will trip at 1/3Vcc,the bias provided by the resistors R1 & R2 are
centered within the comparators trip limits. By modifying the input time constant on the circuit, reducing the
value of input capacitor (C1) 0.001 uf so that the input pulse get differentiated, the arrangement can also
be used either as a bistable device or to invert pulse wave forms. In the later case, the fast time combination
of C1 with R1 & R2 causes only the edges of the input pulse or rectangular waveform to be passed. These
pulses set and reset the flip-flop and a high level inverted output is the result.



CIRCUIT DIAGRAMS:

Fig 6.1: Schmitt trigger circuit using IC 741

Fig 6.2: Schmitt trigger circuit using IC555



Design:

Vutp = [R1/ (R1+R2)] (+Vsat)

Vltp = [R1/ (R1+R2)] (-Vsat)

Vhy = Vutp – Vltp

= [R1/ (R1+R2)] [+Vsat – (-Vsat)]

PROCEDURE:

1. Connect the circuit as shown in figures.

2. Apply an arbitrary waveform (sine/triangular) of peak voltage greater than UTP to the input of a

Schmitt trigger.

3. Observe the output at pin6 of the IC 741 and at pin3 for IC 555 Schmitt trigger circuits by

varying the input and note down the readings as shown in Table 1 and Table 2

4. Find the upper and lower threshold voltages (Vutp, VLtp) from the output wave form.

WAVE FORMS:



OBSERVATIONS:

Table 1:

IC 741 IC 555
Parameter Input Output Input Output

Voltage( Vp-p),V

Time period(ms)

Table 2:

Parameter IC 741 IC 555

Vutp

Vltp

PRECAUTIONS:



RESULTS:


1. What is meant by Hysteresis in Schmitt Trigger?

2. What are the other names for Schmitt Trigger?

3. What are the applications of Schmitt Trigger?

4. What are the advantages of Schmitt Trigger?

5. Schmitt Trigger contains how many stable states?



8. VOLTAGE REGULATOR USING IC 723

AIM: To design a low voltage variable regulator of 2 to 7V using IC 723.


Name of the
Component/Equipment
IC 723 Refer Appendix C Each one
IC 7805
IC7809
IC7912
Resistor 3.3KΩ,4.7KΩ,100 Ω Each one
Variable Resistors 1KΩ, 5.6KΩ Each one
Bread Board 1

THEORY:

A voltage regulator is a circuit that supplies a constant voltage regardless of changes in load current and
input voltage variations. Using IC 723, we can design both low voltage and high voltage regulators with
adjustable voltages. For a low voltage regulator, the output VO can be varied in the range of voltages VO
<Vref, where as for high voltage regulator, it is VO > Vref. The voltage Vref is generally about 7.5V.Although
voltage regulators can be designed using Op-amps, it is quicker and easier to use IC voltage Regulators.IC
723 is a general purpose regulator and is a 14-pin IC with internal short circuit current limiting, thermal
shutdown, current/voltage boosting etc. Furthermore it is an adjustable voltage regulator which can be varied
over both positive and negative voltage ranges. By simply varying the connections made externally, we can
operate the IC in the required mode of operation. Typical performance parameters are line and load
regulations which determine the precise characteristics of a regulator. The pin configuration and
specifications are shown in the Appendix-c.



CIRCUIT DIAGRAM:

Fig1: Voltage Regulator

Design of Low voltage Regulator:

Assume Io= 1mA, VR=7.5V

RB = 3.3 KΩ

For given Vo

R1 = (VR – Vo) / Io

R2 = Vo / Io

PROCEDURE:

a) Line Regulation:

1. Connect the circuit as shown in fig 1.

2. Obtain R1 and R2 for Vo=5V

3. By varying Vn from 2 to 10V, measure the output voltage Vo.

4. Draw the graph between Vn and Vo as shown in model graph (a)

5. Repeat the above steps for Vo=3V



b) Load Regulation: For VO=5V

1. Set Vi such that Vo= 5 V

2. By varying RL, measure IL and Vo

3. Plot the graph between IL and Vo as shown in model graph (b)

4. Repeat above steps 1 to 3 for Vo=3V.

Sample Readings

a) Line Regulation:
Vo set to 5V Vo set to 3V

Vi (v) Vo(v) Vi (v) Vo(v)

b) Load Regulation:

Vo set to 5V Vo set to 3V

IL (mA) Vo(v) IL (mA) Vo(v)

MODEL GRAPHS:

a) Line Regulation b) Load Regulation



PRECAUTIONS:


RESULTS:


1) What is meant by a voltage regulator?
2) What is meant by line and load regulation?



1. D FLIP - FLOP- 7474

AIM: To verify the truth table of D-flip-flop using IC 7474.

APPARATUS:

1. IC 74LS74.
2. Bread board IC trainer kit.
3. Patch cords.

PIN DIAGRAM:

LOGIC SYMBOL:



LOGIC DIAGRAM:



TRUTH TABLE:

THEORY:

The D flip-flop is also known as the Data flip-flop or the Delay flip-flop. It is used to either store
the data or introduce a delay. If a ‘0’ is given at Din, then S is ‘0’ and R will be ‘1’. This resets the flip-flop.
If a ‘1’ is given at Din, and then S is ‘1’ and R ‘0’. This sets the flip-flop. Thus we find that D out is always
equal to Din. Hence this flip-flop can be used to store a binary digit. So it is known as the Data flip-flop. The
D flip-flop can also be clocked similar to the RS flip-flop. In the clocked D flip-flop D out will be made
equal to D in only when the clock arrives. Thus the data bit is sent to the output after a delay. Therefore, the
D flip-flop is also known as the Delay flip-flop.

PROCEDURE:

1. Connections are made as per the circuit diagram.
2. Connect the preset terminal to logic ‘1’ and then clear the circuit by connecting the clear terminal to
1
logic ‘0’. Observe Q and Q .
3. Connect the preset terminal to logic ‘0’ and clear terminal to logic ‘1’.
1
4. Observe Q and Q .
5. Now apply +ve edge triggered circuit clock and change the values of D to ‘0’ and ‘1’.
1
6. Now verify the values of Q and Q .

PRECAUTIONS:

1. Avoid loose connections.
2. Identify correctly the pin numbers.

VIVA QUESTIONS:

2. What is D-FF?
3. Define a latch?
4. Define a FF?
5. What is the difference b/w latch & FF?
6. In flip-flop how many stable states are there?
7. What is edge triggering
8. What is level triggering
9. I/P of D-F/F =’1’, then what is the O/P value Q=

RESULT: Truth table of D-flip-flop is verified



2. DECADE COUNTER-7490

AIM: To study the operation of decade counter using IC7490.

APPARATUS:

1. IC 7490
3. Connecting wires.
4. Patch cords.

PIN DIAGRAM:

LOGIC DIGRAM:



LOGIC SYMBOL:

OBSERVATIONS:

Decimal
QD QC QB QA Equivalent
output

0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
1 0 0 0 8
1 0 0 1 9

THEORY:
The decade counter (mod-10 counter) is used most often. In order to count from 0 through 9, a
counter with 3 flip-flops is not sufficient. With 4 flip-flops one can count from 0 to15 (16 states). Out of
these 16 states, we should skip any 6 states. In the decade counter, when the output is 1010(for the 10th
clock pulse), all the flip-flops should be reset. Thus the outputs Q3 and Q1 are given directly to the inputs of
the AND gate and the outputs Q2 and Q0 are given through inverters. Therefore, for the 10th clock pulse,
the counter output would be 1010 for a moment. This sends the output of the AND gate to HIGH clearing all
the flip-flops. Thus a decade counter has been developed.

PROCEDURE:

1. Connect the circuit as shown in the figure.
2. The clock pulse is given to pin-14 of IC 7490.
3. The Vcc supply is given to pin-5 of IC 7490.



4. Pin-12 and pin-1 to be shorted.
5. Pins-2, 3 are Master Reset (MR) inputs and pins-6, 7 are Master Set (MS) inputs.
6. Pins-13, 14 has no connections.
7. Pins-2, 3, 6, 7 are inputs and is always ‘0’.
8. Pins-12, 9,8,11 are outputs.
9. Feed MR terminal with ‘1’ and MS terminals with ‘0’ then the display shows ‘0’.
10. Feed MR terminal with ‘0’ and MS terminals with ‘1’ then the display shows ‘9’.
11. Feed MR terminal with ‘0’ and MS terminals with ‘0’,now apply clock then the output varies
between the values‘0’ and ‘9’.

PRECAUTIONS:

1. Avoid loose connections on the bread board.
2. No connections are to be given to pins-13, 14.
3. Vcc should not exceed +5v.

VIVA QUESTIONS:

1. What is a counter?
2. what are the asynchronous inputs
3. To restrict the count value of a counter, if takes the help of inputs.
4. To restrict the count value of a counter, if takes the help of inputs.
5. Define mod –up counter.
6. Define mod –down counter.
7. Difference b/w mod-up counter and mod-down counter.

RESULT: The working of the decade counter is studied.



3. SHIFT REGISTER - 7495

AIM: To verify the following functions of shift register using IC7495.

1. Clearing the register.
2. Serial input/parallel output.
3. Parallel input/ parallel output.
4. Parallel input/serial output.

APPARATUS:

1. Bread board.
2. IC 7495.
3. Patch cords.

PIN DIAGRAM:

LOGIC SYMBOL:



THEORY:

A shift register is an n-bit register with a provision for shifting its stored data by one bit position
at each tick of the clock. The serial input, SERIN, specifies a new bit to be shifted into one end at each clock
tick. This bit appears at the serial output, SEROUT, after ‘n’ clock ticks, and is lost one tick later. Thus, an
n-bit serial-in, serial-out shift register can be used to delay a signal by n clock ticks. A serial-in, parallel-out
shift register has outputs for all of its stored bits, making them available to other circuits. Such a shift
register can be used to perform serial-to-parallel conversion. Conversely, it is possible to build a parallel-in,
serial-out shift register. At each clock tick the register either loads new data from inputs 1D-ND or it shifts
its current contents, depending on the value of the LOAD/SHIFT control input. The device uses a 2-input
multiplexer on each flip-flop’s D input to select between the two cases. A parallel-in, serial-out shift register
can be used to perform parallel-to-serial conversion. By providing outputs for all of the stored bits in a
parallel-in shift register, we obtain the parallel-in, parallel-out shift register. Such a device is general enough
to be used in any of the applications of the previous shift registers.

PROCEDURE:

1. Mount the IC 7495 on logic trainer and make the required connections.
2. Connect pins-2, 3, 4, 5 of the IC to logic switches SW1, SW2, SW3 and SW4 for applying low
and high logic levels at this input.
3. The serial input is given to pin-1 and mode control to pin-6.
4. Pins-8 and 9 are shorted and connected to clock pulse.
5. Connect Vcc=+5v to pin-14.
6. Pin-7 is grounded.

CLEARING FUNCTION:

1. Set the mode control switch to low.
2. Set the serial input switch SW3 to low.
3. Set parallel inputs A, B, C and D to logic ‘0’.
4. To clear the registers apply clock pulses till the output is “0000”.

SERIAL INPUT/PARALLEL OUTPUT:

1. After the register has been cleared, any 4-bit serial number can be loaded into the register.
2. Set mode control switch to low.
3. Set the serial input to high.
4. Apply a clock pulse which will shift the serial input ‘1’ into the register, in this case QA is ‘1’.
5. Return serial input switch SW3 to low and apply three clock pulses. The register will show an
output of “00001”.We can load any 4-bit number into the register in this way.

PARALLEL INPUT/ PARALLEL OUTPUT:

1. Set the Mode Control to high.
2. Apply the following inputs at A,B,C and D
A B C D
1 0 1 1
3. If we apply a clk pulse the word will be loaded into the register.

PARALLEL INPUT/SERIAL OUTPUT:

1. If the loaded input is “1011”.Set the Mode Control to low.
2. Set the serial input pin-1 to low.
3. As you apply clk pulse, the word will be shifted out serially from QD and after four clock pulses
the register will be cleared



PRECAUTIONS:

1. All the pins should be identified properly.
2. Supply voltage should not exceed +5v.

VIVA QUESTIONS:

1. What is a register?
2. What is a shift register?
3. What are the operations performed by a shift register?
4. Applications of SISO shift register.
5. Applications of PISO shift register.
6. Applications of SIPO shift register.
7. Applications of PIPO shift register.
8. What is the IC package?
9. What is a universal shift register?
10. What are the operations performed by a universal shift register?
11. Applications of SISO universal shift register.
12. Applications of PISO universal shift register.
13. Applications of SIPO universal shift register.
14. Applications of PIPO universal shift register.
15. What is the IC package?
16. Difference b/w shift register and universal shift register.

RESULT: Various functions of shift register using IC 7495 are verified.



4. 3 - 8 DECODER- 74138
AIM: To verify the operation of 3 to 8 line decoder using IC 74138.

APPARATUS:

1. IC 74138.
2. Bread board trainer kit
3. Patch cords

PIN DIAGRAM:

LOGIC SYMBOL:



LOGIC DIAGRAM:

TRUTH TABLE:

THEORY:
n
Decoder is the combinational circuit which contains ‘n’ input lines to 2 output lines. The decoder
is used for converting the binary code into the octal code. The IC74138 is the 3*8 decoder which contains
three inputs and eight outputs and also three enables out of them two are active low and one is active high.
Decoders are used in the circuit where required to get more outputs than that of the inputs which also used in
the chip designing process for reducing the IC chip area.

PROCEDURE:

1. Connect the circuit as shown in the figure.
2. Apply Vcc=+5v to the Pin-16 of IC 74138.
3. Connect the inputs to Pins-1, 2&3.
4. Pins-4, 5, 6 are the enable inputs.
5. When E11 is high and E21, E3 are low then all the outputs are high irrespective of inputs A0 ,A1 ,A2
6. Similarly when E21is high, all the outputs are high irrespective of the inputs.



7. When E3 is low all the outputs are high irrespective of E11 and E21 and high
8. If E11 and E21 are low and E31 is high, the inputs are low, the outputs O01 will be low with all the
other outputs are low.
9. Similarly by changing the inputs we get (one) 1 output as low and all other outputs as high.
10. When all inputs are high O71 will be low and all other will be high

PRECAUTIONS:


VIVA QUESTIONS:

1. What is decoder?
2. What is a encoder?
3. For a 2- I/P decoder how many O/P’s are produced
4. A decoder with ‘n’ input produces max. of __ no.of minterms.
5. The general representation of an encoder is
6. Draw the 2 to 4 line decoder with only nor gates.
7. Difference b/w de multiplexer and decoder
8. The general representation of an encoder is for economical realization, decoder is used to realize a
function which contain ( Less no. of don’t cares)
9. A 16 to 64 decoder can be obtained by cascading of
10. Can more than one decoder O/P be activated at one time?

RESULT: The working of the 3 to 8 decoder is verified using IC 74138



5. 4-BIT COMPARATOR- 7485
AIM: To verify the operation of 4-bit magnitude comparator using IC 7485.

APPARATUS:

1. IC 7485.
3. Patch cords.

PIN DIAGRAM:

LOGIC SYMBOL:



LOGIC DIAGRAM:

FUNCTION TABLE;



THEORY:

Comparing two binary words for equality is a commonly used operation in computer systems and
device interfaces. A circuit that compares two binary words and indicates whether they are equal is called a
comparator. Some comparators interpret their input words as signed or unsigned numbers and also indicate
an arithmetic relationship (greater or less than) between the words. These devices are often called magnitude
comparators. A 1-bit Comparator is designed using Ex-OR and Ex-NOR gates. The outputs of 4 XOR gates
are ORed to create a 4-bit comparator. The IC 7485 is 4-bit magnitude comparator. With respect to the 8
inputs 3 inputs are cascaded inputs. After the 8 input operations are performed further the outputs are based
on the cascaded inputs.

PROCEDURE:

1. Connect the circuit as per Pin diagram.
2. Give the inputs A [A3, A2, A1, A0] and B [B3,B2,B1,B0] according to function table.

3. Give the cascaded inputs IA>B, IA=B, IA<B and verify the outputs.

4. Tabulate the inputs and outputs according to function table.

PRECAUTIONS:


VIVA QUESTIONS:

1. What is Magnitude Comparator?

2. To form a 12 – bit comparator how many 4-bit comparators are connected in cascaded form.
3. The IC 7485 is a package and is a ____ comparator.
4. How many cascaded input are there for a 4-bit comparator.

RESULT: The operation of 4-bit magnitude comparator is verified using IC7485.



6. 8 x 1 MULTIPLEXER-74150

AIM: To verify the operation of 8*1 multiplexer using IC 74150.

APPARATUS:

1. IC74150.
3. Patch cords.

PIN DIAGRAM:



LOGIC SYMBOL:

TRUTH TABLE



THEORY:

A multiplexer is a digital switch- it connects data from one of n sources to its output. An 8*1 is
multiplexer consists of 3 input lines as select lines and 8 input lines and 1 output line. A multiplexer is a
unidirectional device which follows the data from input lines to output lines. Multiplexers are obviously
useful device in any application in which data must be multiple source to destination. A common application
in computers is the mux between the processors registers and its ALU.

PROCEDURE:

1. Connections are made as per logic diagram.
2. Connect the inputs D0 to D7 .
3. Give data select inputs and verify outputs according to truth table.

PRECAUTIONS:

VIVA QUESTIONS:

1. Mux is an implementation of –
2. Multiplexer is represented by –
3. De multiplexer is represented by –
RESULT: 8*1 multiplexer is verified using IC74150.



7. RAM (16 x 4) – IC 74189

AIM: To verify the operation of (16 x 4) RAM using IC 74189 (Read and Write operations)

APPARATUS:

1. IC74189.
3. Patch cords.

PIN DIAGRAM:

LOGIC SYMBOL:



LOGIC DIAGRAM:

FUNCTION TABLE:

MEMORY ENABLE WRITE ENABLE OPERATION

H X All data outputs are high
L H Read mode (data outputs are
compliment of the RAM content)
L L Write mode (data inputs are written
on to the memory; data outputs are
compliment of the RAM content)

THEORY:

The 74LS189 is a high speed 64-bit Ram organized as a 16- word by 4-bit array. Address inputs are buffered
to minimize loading and are fully decoded on-chip. The outputs are 3-state and are in the high impedance
state whenever the Memory Enable (ME) input is HIGH. The outputs are active only in the Read mode and
the output data is the complement of the stored data. Here A0-A3 are the Address Inputs, D1-D4 are Data
inputs, O1-O4 are Inverted Data Outputs.

PROCEDURE:

This experiment has 3 stages – Clearing the memory, data entry (Write operation) and data
verification (Read operation).

1) The memory Enable pin is used to select 1- of-n ICs i.e. like a Chip Select signal.
For simply city, the memory enable pin is permanently held low.
2) The address lines are given through an up /down counter with preset capability.
3) The set address switch is held high to allow the user choose any location in the RAM, using the address
bits.
4) The address and data bits are used to set an address and enter the data.
5) The ‘Read/Write ‘switch is used to write data on to the RAM.



CLEARING THE MEMORY:

The RAM IC 7489 is a volatile memory. This means that it will lose the data
stored in it, on loss of power. However, this dose not means that the content of the memory becomes 0h, but
not always. The RAM IC 7489 does not come with a ‘Clear Memory ‘signal. The memory has to
be cleared manually.

1) Position the ‘Stack/Queue’ switch in the ‘Queue’ position.
2) Position the ‘Set Address’ switch in the ‘1’ position.
3) Set the address bits to 0h (first byte in the memory)
4) Position the ‘Set Address’ switch in the ‘0’ position to disable random access and enable the counter.
5) Position the’ Read/Write ‘switch in the’ Write’ position to write data on to the memory.
6) Set the data bits to 0h (clearing the content).
7) Observe that the LEDs (D3 to D0) glow. This is to indicate that the content is 0h. Refer the truth table
above and observe that the data outputs of the RAM will be compliments of the data inputs.
8) Position the ‘Increment/Decrement ‘switch in the ‘Increment’ position.
9) Press the ‘Clock’ to increment the counter to the next address. As the ‘Read /Write ‘switch is already in
the ‘Write’ position, and the data bits are set to the 0h, the content in the new location is also replaced
with 0h.
10) Repeat step 8 until the data in all the memory locations have been cleared.

WRITE OPERATION:

ADDRESS DATA
0h - 0000 Ah - 1010
1h - 0001 Bh - 1011
2h - 0010 4h - 0100
3h - 0011 7h - 0111
4h - 0100 Ch - 1100
5h - 0101 1h - 0001
6h - 0110 Fh - 1111
7h - 0111 5h - 0101
8h - 1000 8h - 1000
9h - 1001 3h - 0011
10h - 1010 Eh - 1110
11h - 1011 9h - 1001
12h - 1100 Dh - 1101
13h - 1101 0h - 0000
14h - 1110 2h - 0010
15h - 1111 6h - 0110

1. Assume that the following data has to be written on to the RAM. The address and data are given in the
hexadecimal format.
2. Position the ‘Stack/Queue’ switch in the ‘Queue’ position.
3. Position the’ Read/Write ‘switch in the’ Write’ position to enable the entry of data in to the RAM.
4. Position the ‘Set Address’ switch in the ‘1’ position to allow random access of memory.
5. Set the desired address (any address at random) using the address bit switches.
6. Set the desired data (refer table for the data to be entered in each location) using the data bit Switches.
7. Observe that the data is indicated by the LEDs (D3 toD0). This is because the data is written on to the
RAM.
8. Also observe that the data is indicated by the data outputs is the compliment of the data input (refer truth
table condition ME =L and WE=L).


9. After each data entry, make a note of the location where data is entered. This is to make sure that we are
not re –entering data in the same location.
10. Repeat steps 4 and 5 until data has been entered in all the addresses listed in the above table
11. Position the’ Read/Write ‘switch in the’ Read’ position, to disable data entry.
12. This completes data entry.

READ OPERATION: -

1. Position the ‘Stack/Queue’ switch in the ‘Queue’ position.
2. Position the ‘Set Address’ switch in the ‘0’ position to allow random access of memory.
3. Position Read/Write ‘switch in the’ Read’ position, to disable unauthorized entry of data.
4. Set the desired address (any address at random).
5. Observe that the data entered in the location is indicated by the LEDs (D3 toD0). This is because the
data was written during the data entry procedure.
6. Also observe that the data indicated by the data out puts is the compliment of the data input (refer truth
table condition ME=L and WE=H).

RESULT: Operation of the RAM Ic74LS189 has been verified.

QUESTIONS:

1. What is the RAM?
2. Give the applications of the RAM?
3. What is the difference between RAM &ROM?
4. What is the difference between static RAM &dynamic RAM?
5. Which can be used as 1-bit memory?
6. What are the different types of the ROM?
7. What are the parameters of the RAM?
8. What is refreshing of memory? And where it is required?
9. What are sequential access memories?
10. What are charge-coupled devices?



APPENDIX –A

IC 741

Pin Configuration:

Specifications:

1. Voltage gain A = α typically 2, 00,000

2. I/P resistance RL = α Ω, practically 2MΩ

3. O/P resistance R1 =0, practically 75Ω

4. Bandwidth = α Hz. It can be operated at any frequency

5. Common mode rejection ratio = α (Ability of op amp to reject noise voltage)

6. Slew rate + α V/µsec(Rate of change of O/P voltage)

7. When V1 = V2, VD=0

8. Input offset voltage (Rs ≤ 10KΩ) max 6 mv

9. Input offset current = max 200nA

10. Input bias current: 500nA

11. Input capacitance: type value 1.4PF

12. Offset voltage adjustment range: ± 15mV

13. Input voltage range: ± 13V

14. Supply voltage rejection ratio : 150 µr/V

15. Output voltage swing: + 13V and – 13V for RL > 2KΩ



16. Output short-circuit current: 25mA

17. Supply current: 28mA

18. Power consumption: 85MW

19. Transient response: rise time= 0.3 µs

20. Overshoot= 5%

APPENDIX – B

IC 555

Pin Configuration:

Specifications:

1. Operating temperature : SE 555 -55oC to 125oC

NE 555 0o to 70oC

2. Supply voltage : +5V to +18V

3. Timing : µSec to Hours

4. Sink current : 200mA

5. Temperature stability : 50 PPM/oC change in temp or 0-005% /oC.



APPENDIX – C

IC723

Pin Configuration:

Specifications of 723:

Power dissipation : 1W

Input Voltage : 9.5 to 40V

Output Voltage : 2 to 37V

Output Current : 150mA for Vin-Vo = 3V

10mA for Vin-Vo = 38V

Load regulation : 0.6% Vo

Line regulation : 0.5% Vo



REFERENCES

1. Anand Kumar, Pulse and Digital Circuits, PHI

2. David A. Bell, Solid State Pulse circuits, PHI

3. D.Roy Choudhury and Shail B.Jain, Linear Integrated Circuits, 2nd edition, New Age International.

4. James M. Fiore, Operational Amplifiers and Linear Integrated Circuits: Theory and Application, WEST.

5. J.Milliman and H.Taub, Pulse and digital circuits, McGraw-Hill.

6. Ramakant A. Gayakwad, Operational and Linear Integrated Circuits, 4th edition, PHI.

7. Roy Mancini, OPAMPs for Everyone, 2nd edition, Newnes.

8. S. Franco, Design with Operational Amplifiers and Analog Integrated Circuits, 3rd edition, TMH.

9. William D. Stanley, Operational Amplifiers with Linear Integrated Circuits, 4th edition, Pearson.

10. www.analog.com.

11. www.datasheetarchive.com

12. www.ti.com


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