1. ISSN: 2277 – 9043
International Journal of Advanced Research in Computer Science and Electronics Engineering
Volume 1, Issue 5, July 2012
Design & Analysis of Matrix Arbiter for NoC
Architecture
Mr. Suyog K.Dahule #1 Dr. M.A.Gaikwad*2
Abstract: Network-on-Chip (NoC) is a general purpose on- Dr. M.A.Gaikwad, Dean (R&D) Department of Electronics,
BDCOE,SevagramWardha,(M.H)India(e-mail:
chip communication concept that offers high throughput, gaikmaor@rediffmail.com)
which is the basic requirement to deal with complexity of .
modern systems. Arbiter is used in NoC Router when
number of input port are request for same output port. In
II. NoC ROUTER
this paper we are design Matrix Arbiter for NoC
architecture. When all input port are request for same
output port in this situation matrix arbiter first form a
matrix 5*5 After that matrix arbiter assign the Priority to
all input request and generate the grant signal. In this
input port a output port a
paper we are analyze the Area, power.
input port b output port b
Keywords- Network on–Chip, Matrix Arbiter
input port c output port c
FIFO Buffers Crossbar
I.INTRODUCTION input port d output port d
As the area and speed on a single chip now faces
input port e output port e
the big challenge on a single chip, more and more
processing elements now are placed on System on chip. Write
Network-on-chip (NoC) is on a chip becomes a primary So S1 S2 S3 S4
factor which limits the performance and power
consumption. As the switch speed of crossbar switch
increases rapidly, on big problem we should a new Read
method for on chip communication to solve the problem
that challenges the system on chip. The physical
Arbiter
interconnection resolve is to implement a fast and fairness
arbiter to maximize the switch throughput and timing
performance for Network-on-chips.
NoC has advantages on architecture, Fig 1: Block diagram of NOC Router
performance, reusability and scalability than traditional
bus-based system-on-chip. Among these basic modules, The design of router mainly consists of three parts:
the data flow control of virtual channel play an important
role to alleviate the package congestion. The architecture 1. FIFO
and dataflow control will affect the design of arbiter of 2. Arbiter
NOC significantly. The arbitration should guaranteed the 3. Crossbar
fairness in scheduling, avoid starvation, and provide high
throughput [ 1]. FiFo is used in NoC Router for storage of packet of input
The NoC's switches should provide high speed port. Arbiter is used to trap the source and destination
and cost-effective contention resolution scheme when address of input and output port. Arbiter generate the
multiple packets from different input ports compete for control signal according to priority so that crossbar
the same output port. A fast arbiter is one of the most switch transmit data from source to destination.
dominant factors for high performance NoC switches [4].
For the above reasons, the analysis of the performance of In this paper we are design Arbiter block and work on
the arbiters are significantly meaningfulness in the design Priority based Matrix Arbiter.
of Network-on-chips.
Manuscript received June 15, 2012.
Mr. Suyog K.Dahule, M-tech Student Department of Electronics,
BDCOE,Sevagram Wardha,(M.H) (e-mail: dahulesuyog@gmail.com).
Wardha ,India, Mobile No:+919096429403
100
All Rights Reserved © 2012 IJARCSEE

2. ISSN: 2277 – 9043
International Journal of Advanced Research in Computer Science and Electronics Engineering
Volume 1, Issue 5, July 2012
III ARBITER output port. In that matrix arbiter set the corresponding
bit which is requested for same output port. Now matrix
The arbiter trap the source and destination address from
arbiter check the priority if input a has highest priority
the output 0f buffer and generate the control signal so that
input data from source side sending to the output port. and input e has lowest priority then matrix arbiter gives
priority to input a and input e will get lowest
priority.Matrix Arbiter generate a control signal so
particular select line is selected and source packet is
transmitted to destination
Fig: 2 Diagram of Arbiter
Arbiter controls the arbitration of the ports and
resolve contention problem. It keeps the updated status of
all the ports and knows which ports are free and which
Where L:LOW, H:HIGH
ports are communicating with each other. Packets with
the same priority and destined for the same output port
Fig: 3 Priority matrix of arbiter
are scheduled with a matrix arbiter. The arbiter will
release the output port which is connected to the crossbar
once the last packet has finished transmission. So that V SIMULATION RESULT
other waiting packets could use the output by the
arbitration of arbiter. In proposed work, round robin A) Without contention
arbitration algorithm use to assign priorities when many
input ports request the same output. Output signal
generated by arbiter is read, external clock, three bit Sr. I/p SA DA Grant Select line O/p
No port
select lines for crossbar switch to select output channel.
port [4:0]
External clock signals which is indication for next
connecting router that data is now available on output
1. Port a 000 001 Ma(01000) Selb(000) Port
port of source router. When it is high, it means data is b
now available on output port of that router. Read signal
generated by considering current status of signal of that 2. Port b 001 010 Mb(00100) Selc(001) Port
port only. Read signal is high only when FiFo empty. c
Signal is low it means buffer is not empty , some data
is store in Arbiter generates three bit select lines to select 3. Port c 010 011 Mc(00010) Seld(010) Port
output channel for outputting data out of router. Steps d
follow to generate three bit select lines to properly route
in coming packet out of router given as below. First 4. Port d 011 100 Md(00001) Sele(011) Port
compare three bit destination address to select output e
channel for dataflow out of router. Next three bit are
source address indicate the input channel from where 5. Port e 100 000 Me(10000) Sela(100) Port
a
packet is Transmitted
IV MATRIX ARBITERATION
Fig No. 4 without contention Table
In matrix arbitration when all input packet have
From above table all the input port are requested
the same priority request for same output port then matrix for different output port so matrix generator first generate
arbiter generate the matrix depending upon input and matrix of dimension 5*5 and set corresponding bit one. In
101
All Rights Reserved © 2012 IJARCSEE

3. ISSN: 2277 – 9043
International Journal of Advanced Research in Computer Science and Electronics Engineering
Volume 1, Issue 5, July 2012
this case the destination address is not same so every
input port getting a priority so they have to transfer data
from source to destination.
Fig 8.matrix generator
Fig 5.Priority matrix after receiving request
Fig 6.Without contention Waveform
B) With contention
Fig 9.Changes of priority matrix after receiving
request
S I/p SA DA Grant Select line O/p port
r. Here we have given matrix generator for four
N port [4:0] inputs similarly it will generate matrix for fifth input.
o
1. Port 000 001 Ma(01000) Selb(000) Port b
a
2. Port 001 001 Mb(01000) Selb(001) Port b
b
3. Port 010 001 Mc(01000) Selb(010) Port b
c
4. Port 011 001 Md(01000) Selb(011) Port b
d
5. Port 100 001 Me(01000) Selb(100) Port b
e
Fig.7.With contention Table Fig10:Contention waveform
In above table there is contention for output port so that In this paper after synthesize we found the area
the Matrix generated shown in figure gate count is 32,352 and power consumption is 7mW.
102
All Rights Reserved © 2012 IJARCSEE

4. ISSN: 2277 – 9043
International Journal of Advanced Research in Computer Science and Electronics Engineering
Volume 1, Issue 5, July 2012
CONCLUSION
In this paper we are design matrix arbiter. this
arbiter uses same arbitration algorithm as Round Robin
Arbiter. this arbiter fairly treated with each input request
so that every input transmit packet to the output.
REFRENCES
[1]Yun-Lung Lee, Jer Min Jou and Yen-Yu Chen,a High Speed and
decentralized arbiter Design for NoC[J],350-353
[2] .Gao Xiaopeng ,Zhang z,he,Long Xiang ,Round Robin Arbiter
for Virtual Channel Router ,IMACS Multiconferences on
“Computational”Engineering in System application”1610-1614
[3]Li-shiuan Peh,William J.Dally .A.Delay Modeland Speculative
Architecture for Pipe line Router[J],the 7th International
Symposium on High Performances Computer Architecture.255-
266
[4] Eung S.Shin,Vincent 1.Mooney III and George f.Riley ,Round
Robin arbiter .Arbiter Design And Generation,ISSS’02
[5]H,J,Chao,C.H.Lam, and E.Oki Broadband Packet Switching
Technology,John Wiley & sons Inc,2001.
[6]Chang Wu,Yubai Li,Song Chai ,Zhongming Yang-Lottery
Router
A Customized Abritral Priority NOC Router[J].200S International
Conferences on Computer Sciences and Software Engineering
411-414
103
All Rights Reserved © 2012 IJARCSEE