The document discusses modules and ports in Verilog. It describes that a module defines distinct parts including module name, port list, port declarations, and optional parameters. Ports provide the interface for a module to communicate with its environment. There are two methods for connecting ports to external signals - by ordered list where signals must appear in the same order as ports, and by name where the order does not matter as long as port names match. Hierarchical names provide unique names for every identifier by denoting the design hierarchy with identifiers separated by periods.
Verilog Tutorial - Verilog HDL Tutorial with ExamplesE2MATRIX
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Simulation tools typically accept full set of Verilog language constructs
Some language constructs and their use in a Verilog description make simulation efficient and are ignored by synthesis tools
Synthesis tools typically accept only a subset of the full Verilog language constructs
In this presentation, Verilog language constructs not supported in Synopsys FPGA Express are in red italics
There are other restrictions not detailed here, see [2].
The Module Concept
Basic design unit
Modules are:
Declared
Instantiated
Modules declarations cannot be nested
Verilog Tutorial - Verilog HDL Tutorial with ExamplesE2MATRIX
E2MATRIX Research Lab
Opp Phagwara Bus Stand, Backside Axis Bank,
Parmar Complex, Phagwara Punjab (India).
Contact : +91 9041262727
web: www.e2matrix.com -- email: support@e2matrix.com
Simulation tools typically accept full set of Verilog language constructs
Some language constructs and their use in a Verilog description make simulation efficient and are ignored by synthesis tools
Synthesis tools typically accept only a subset of the full Verilog language constructs
In this presentation, Verilog language constructs not supported in Synopsys FPGA Express are in red italics
There are other restrictions not detailed here, see [2].
The Module Concept
Basic design unit
Modules are:
Declared
Instantiated
Modules declarations cannot be nested
Those slides describe digital design using Verilog HDL,
starting with Design methodologies for any digital circuit then difference between s/w (C/C++) and H/w (Verilog) and the most important constructs that let us start hardware design using Verilog HDL.
Verilog HDL is a hardware description language used to design and document electronic systems. Verilog HDL allows designers to design at various levels of abstraction. It is the most widely used HDL with a user community of more than 50,000 active designers.
A brief history
Verilog HDL originated at Automated Integrated Design Systems (later renamed as Gateway Design Automation) in 1985. The company was privately held at that time by Dr. Prabhu Goel, the inventor of the PODEM test generation algorithm. Verilog HDL was designed by Phil Moorby, who was later to become the Chief Designer for Verilog-XL and the first Corporate Fellow at Cadence Design Systems. Gateway Design Automation grew rapidly with the success of Verilog-XL and was finally acquired by Cadence Design Systems, San Jose, CA in 1989.
Verilog was invented as simulation language. Use of Verilog for synthesis was a complete afterthought. Rumors abound that there were merger discussions between Gateway and Synopsys in the early days, where neither gave the other much chance of success..
In the late 1980's it seemed evident that designers were going to be moving away from proprietary languages like n dot, HiLo and Verilog towards the US Depatment of Defense standard H.D.L., known as the VHSIC Hardware Description Language. VHSIC it self stands for "Very High Speen Intergrated Circuit" BTW).
Perhaps due to such market pressure, Cadence Design Systems decided to open the Verilog language to the public in 1990, and thus OVI (Open Verilog International) was born. Until that time, Verilog HDL was a proprietary language, being the property of Cadence Design Systems. When OVI was formed in 1991, a number of small companies began working on Verilog simulators, including Chronologic Simulation, Frontline Design Automation, and others. The first of these came to market in 1992, and now there are mature Verilog simulators available from many sources.
As a result, the Verilog market has grown substantially. The market for Verilog related tools in 1994 was well over $75,000,000, making it the most commercially significant hardware description language on the market.
An IEEE working group was established in 1993 under the Design Automation Sub-Committee to produce the IEEE Verilog standard 1364. Verilog became IEEE Standard 1364 in 1995.
As an international standard, the Verilog market continued to grow. In 1998 the market for Verilog simulators alone was well over $150,000,000; continuing its dominance.
The IEEE working group released a revised standard in March of 2002, known as IEEE 1364-2001. Significant publication errors marred this release, and a revised version was released in 2003, known as IEEE 1364-2001 Revision C.
Notes: Verilog Part 2 - Modules and Ports - Structural Modeling (Gate-Level M...Jay Baxi
The Notes Verilog Part 2 includes the notes and keypoints of a reference book "Verilog HDL by Samir Palnitkar.
This is the second part out of the total six parts.
Those slides describe digital design using Verilog HDL,
starting with Design methodologies for any digital circuit then difference between s/w (C/C++) and H/w (Verilog) and the most important constructs that let us start hardware design using Verilog HDL.
Verilog HDL is a hardware description language used to design and document electronic systems. Verilog HDL allows designers to design at various levels of abstraction. It is the most widely used HDL with a user community of more than 50,000 active designers.
A brief history
Verilog HDL originated at Automated Integrated Design Systems (later renamed as Gateway Design Automation) in 1985. The company was privately held at that time by Dr. Prabhu Goel, the inventor of the PODEM test generation algorithm. Verilog HDL was designed by Phil Moorby, who was later to become the Chief Designer for Verilog-XL and the first Corporate Fellow at Cadence Design Systems. Gateway Design Automation grew rapidly with the success of Verilog-XL and was finally acquired by Cadence Design Systems, San Jose, CA in 1989.
Verilog was invented as simulation language. Use of Verilog for synthesis was a complete afterthought. Rumors abound that there were merger discussions between Gateway and Synopsys in the early days, where neither gave the other much chance of success..
In the late 1980's it seemed evident that designers were going to be moving away from proprietary languages like n dot, HiLo and Verilog towards the US Depatment of Defense standard H.D.L., known as the VHSIC Hardware Description Language. VHSIC it self stands for "Very High Speen Intergrated Circuit" BTW).
Perhaps due to such market pressure, Cadence Design Systems decided to open the Verilog language to the public in 1990, and thus OVI (Open Verilog International) was born. Until that time, Verilog HDL was a proprietary language, being the property of Cadence Design Systems. When OVI was formed in 1991, a number of small companies began working on Verilog simulators, including Chronologic Simulation, Frontline Design Automation, and others. The first of these came to market in 1992, and now there are mature Verilog simulators available from many sources.
As a result, the Verilog market has grown substantially. The market for Verilog related tools in 1994 was well over $75,000,000, making it the most commercially significant hardware description language on the market.
An IEEE working group was established in 1993 under the Design Automation Sub-Committee to produce the IEEE Verilog standard 1364. Verilog became IEEE Standard 1364 in 1995.
As an international standard, the Verilog market continued to grow. In 1998 the market for Verilog simulators alone was well over $150,000,000; continuing its dominance.
The IEEE working group released a revised standard in March of 2002, known as IEEE 1364-2001. Significant publication errors marred this release, and a revised version was released in 2003, known as IEEE 1364-2001 Revision C.
Notes: Verilog Part 2 - Modules and Ports - Structural Modeling (Gate-Level M...Jay Baxi
The Notes Verilog Part 2 includes the notes and keypoints of a reference book "Verilog HDL by Samir Palnitkar.
This is the second part out of the total six parts.
1.5 Legal Labels in Verilog areSystem Verilog extends it and al.pdfankit482504
1.
5 Legal Labels in Verilog are:
System Verilog extends it and allows one to add named blocks to reserve word end and join.
Also SystemVerilog allows to add the LABLE or NAMED BLOCK before begin, fork as below.
1.\"MY NAMED_ BLOCK\":Begin
2..\"MY NAMED_ BLOCK\":End
3..\"MY NAMED_ BLOCK\":Fork
4..\"MY NAMED_ BLOCK\":Join
5..\"MY NAMED_ BLOCK\":Initial Begin
It is illegal to have both a label before a begin or fork and a block name after the begin or fork. A
label cannot appear before the end, join, join_any or join_none, as these keywords do not form a
statement.
2.Verilog Provides in-built primitives for basic gate and switch level modeling. Any circuit can
be modeled by using continuous assignment of gate and switch level primitives.
and (strong1, weak0)#(1,2) gate1(out, in1, in2);
This is an and gate with output \'out\' and two inputs in1 and in2. Strong1 and weak0 are
optional driving strengths and gate1 is optional instance name that can be used while debugging.
First parameter in the bracket is output and you can have any number of inputs after that. This is
how you use a 3 input and gate without instance name, delay and driving strengths:
3.verilog has built in primitives like gates,transmission gates,and switches.if we need complex
primitives then verilog provides UDP or simply user defined primitives using UDP we can
model:
1.Combinational Logic
2.Sequential Logic
Verilog has 2 primitives
1.User Defined primitives
2.HDL gate primitive
4.
UDP definitions are independent of modules; they are at the same level as module definitions in
the syntax hierarchy. They can appear anywhere in the source text, either before or after they are
used inside a module. They may not appear between the keywords module and endmodule.
User-Defined Primitives(UDP) :
5. Yes it is True
One of the advanced concepts in verilog
non synthesizable
single output many iput
consume very less memory
I/Os must be scalar (i.e. bit)
1) UDPs can take only scalar input terminals (1 bit). Multiple input terminals are permitted.
2) UDPs can have only one scalar output terminal (1 bit). The output terminal must
always appear first in the terminal list. Multiple output terminals are not allowed.
3) In the declarations section, the output terminal is declared with the keyword output. Since
sequential UDPs store state, the output terminal must also be declared as a reg.
4) The inputs are declared with the keyword input.
5) The state in a sequential UDP can be initialized with an ‘initial’ statement. This statement is
optional. A 1-bit value is assigned to the output, which is declared as reg.
6) The state table entries can contain values 0,1,or x . UDPs do not handle z values. Z values
passed to a UDP are treated x values.
7)UDPs are defined at the same level as modules. UDPs can not be defined inside modules.
They can be instantiated only inside modules. UDPs are instantiated exactly like
gate primitives.
8)UDPs do not support inout ports.
6
The module is the basic unit of hier.
Introduction to Verilog HDL. This class notes present basic HDL structures, data types, operators, and expressions in Verilog. It also describes three typical modeling style for HDL design; behavioral, dataflow, and structural.
AN IC THAT CONTAINS LARGE NUMBERS OF GATES, FLIP-FLOPS, ETC.
THAT CAN BE CONFIGURED BY THE USER TO PERFORM DIFFERENT
FUNCTIONS IS CALLED A PROGRAMMABLE LOGIC DEVICE (PLD). A
PROGRAMMABLE LOGIC DEVICE IS AN ELECTRONIC COMPONENT USED TO
BUILD RECONFIGURABLE DIGITAL CIRCUITS. UNLIKE INTEGRATED CIRCUITS
WHICH CONSIST OF LOGIC GATES AND HAVE A FIXED FUNCTION, A PLD HAS
AN UNDEFINED FUNCTION AT THE TIME OF MANUFACTURE. IT PERMITS
ELABORATE DIGITAL LOGIC DESIGNS TO BE IMPLEMENTED BY THE USER ON
A SINGLE DEVICE. THE INTERNAL LOGIC GATES AND/OR CONNECTIONS OF
PLDS CAN BE CHANGED/CONFIGURED BY A PROGRAMMING PROCESS.
Yaser Khalifa introduces you to VHDL (VHSIC Hardware Description Language), a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits.
Transducers and sensors
Sensors in robotics
Tactile sensors
Proximity and range sensors
Miscellaneous sensors and sensor based system
Use of sensors in Robotics
Methods of robot programming
Leadthrough programming methods
A robot program as a path in space
Motion interpolation
WAIT, SIGNAL and DELAY commands
Branching
File system and IOCS
Files and file organization
Fundamentals of file organizations
Directory structures
File protection
Interface between file system and IOCS
Allocation of disk space
Implementation of file access
Managing the memory hierarchy
Static and dynamic memory allocations
Memory allocation to a process
Reuse of memory
Contiguous and non contiguous memory allocation
Paging
Segmentation
Segmentation with paging
Definition
Embedded systems vs. General Computing Systems
Core of the Embedded System
Memory
Sensors and Actuators
Communication Interface
Embedded Firmware
Other System Components
PCB and Passive Components
Introduction
Types of end effectors
Mechanical gripper
Other types of grippers
Tools as end effectors
The Robot/End effectors interface
Considerations in gripper selection and design
Operation of an O.S
Structure of an operating system,
Operating systems with monolithic structure
Layered design of an operating system
Virtual machine operating systems
Kernel based operating systems
Fundamentals of Robotics and Machine Vision Systemanand hd
Automation and Robotics
Robotics in science Fiction
A brief history of robotics
Robot Anatomy & Work volume
Robot drive systems
Control systems and Dynamic performance
Precision of movement
End effectors
Robotic sensors,
Robot programming and work cell control
Robot applications
Efficiency, system performance and user convenience
Classes of operating systems
Batch processing system,
Multi programming systems
Time sharing systems
Real time operating systems
Hierarchical Digital Twin of a Naval Power SystemKerry Sado
A hierarchical digital twin of a Naval DC power system has been developed and experimentally verified. Similar to other state-of-the-art digital twins, this technology creates a digital replica of the physical system executed in real-time or faster, which can modify hardware controls. However, its advantage stems from distributing computational efforts by utilizing a hierarchical structure composed of lower-level digital twin blocks and a higher-level system digital twin. Each digital twin block is associated with a physical subsystem of the hardware and communicates with a singular system digital twin, which creates a system-level response. By extracting information from each level of the hierarchy, power system controls of the hardware were reconfigured autonomously. This hierarchical digital twin development offers several advantages over other digital twins, particularly in the field of naval power systems. The hierarchical structure allows for greater computational efficiency and scalability while the ability to autonomously reconfigure hardware controls offers increased flexibility and responsiveness. The hierarchical decomposition and models utilized were well aligned with the physical twin, as indicated by the maximum deviations between the developed digital twin hierarchy and the hardware.
Sachpazis:Terzaghi Bearing Capacity Estimation in simple terms with Calculati...Dr.Costas Sachpazis
Terzaghi's soil bearing capacity theory, developed by Karl Terzaghi, is a fundamental principle in geotechnical engineering used to determine the bearing capacity of shallow foundations. This theory provides a method to calculate the ultimate bearing capacity of soil, which is the maximum load per unit area that the soil can support without undergoing shear failure. The Calculation HTML Code included.
Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdffxintegritypublishin
Advancements in technology unveil a myriad of electrical and electronic breakthroughs geared towards efficiently harnessing limited resources to meet human energy demands. The optimization of hybrid solar PV panels and pumped hydro energy supply systems plays a pivotal role in utilizing natural resources effectively. This initiative not only benefits humanity but also fosters environmental sustainability. The study investigated the design optimization of these hybrid systems, focusing on understanding solar radiation patterns, identifying geographical influences on solar radiation, formulating a mathematical model for system optimization, and determining the optimal configuration of PV panels and pumped hydro storage. Through a comparative analysis approach and eight weeks of data collection, the study addressed key research questions related to solar radiation patterns and optimal system design. The findings highlighted regions with heightened solar radiation levels, showcasing substantial potential for power generation and emphasizing the system's efficiency. Optimizing system design significantly boosted power generation, promoted renewable energy utilization, and enhanced energy storage capacity. The study underscored the benefits of optimizing hybrid solar PV panels and pumped hydro energy supply systems for sustainable energy usage. Optimizing the design of solar PV panels and pumped hydro energy supply systems as examined across diverse climatic conditions in a developing country, not only enhances power generation but also improves the integration of renewable energy sources and boosts energy storage capacities, particularly beneficial for less economically prosperous regions. Additionally, the study provides valuable insights for advancing energy research in economically viable areas. Recommendations included conducting site-specific assessments, utilizing advanced modeling tools, implementing regular maintenance protocols, and enhancing communication among system components.
Saudi Arabia stands as a titan in the global energy landscape, renowned for its abundant oil and gas resources. It's the largest exporter of petroleum and holds some of the world's most significant reserves. Let's delve into the top 10 oil and gas projects shaping Saudi Arabia's energy future in 2024.
Explore the innovative world of trenchless pipe repair with our comprehensive guide, "The Benefits and Techniques of Trenchless Pipe Repair." This document delves into the modern methods of repairing underground pipes without the need for extensive excavation, highlighting the numerous advantages and the latest techniques used in the industry.
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Water scarcity is the lack of fresh water resources to meet the standard water demand. There are two type of water scarcity. One is physical. The other is economic water scarcity.
1. Prepared by Prof. Anand H. D., Dept. of ECE, Dr. AIT, Bengaluru-56
Modules and Ports
Mr. Anand H. D.
1
Modules and ports
Department of Electronics & Communication Engineering
Dr. Ambedkar Institute of Technology
Bengaluru-56
2. Prepared by Prof. Anand H. D., Dept. of ECE, Dr. AIT, Bengaluru-56 2
Topics to be covered
Modules
Ports
Hierarchical Names.
Modules and ports
3. Prepared by Prof. Anand H. D., Dept. of ECE, Dr. AIT, Bengaluru-56 3
Let us discuss about
Modules and ports
Modules
Ports
Hierarchical Names.
4. Prepared by Prof. Anand H. D., Dept. of ECE, Dr. AIT, Bengaluru-56 4
Modules
The module name, port list, port
declarations, and optional parameters
must come first in a module definition.
A module in Verilog consists of distinct parts, as shown in Figure
A module definition always begins with
the keyword module.
Port list and port declarations are
present only if the module has any ports
to interact with the external environment.
Modules and ports
The five components within a module
are: variable declarations, dataflow
statements, instantiation of lower
modules, behavioral blocks, and tasks
or functions. These components can be in
any order and at any place in the module
definition.
5. Prepared by Prof. Anand H. D., Dept. of ECE, Dr. AIT, Bengaluru-56 5
Modules
All components except module,
module name, and endmodule are
optional and can be mixed and matched
as per design needs.
The endmodule statement must always come last in a module definition.
A module definition always begins with
the keyword module.
Verilog allows multiple modules to
be defined in a single file. The modules
can be defined in any order in the file..
Modules and ports
6. Prepared by Prof. Anand H. D., Dept. of ECE, Dr. AIT, Bengaluru-56 6
Modules
// Module name and port list
// SR_latch module
module SR_latch(Q, Qbar, Sbar, Rbar);
//Port declarations
output Q, Qbar;
input Sbar, Rbar;
To understand the components of a module shown above, let us consider a simple example of an
SR latch, as shown in Figure below.
Modules and ports
// Instantiate lower-level modules
// In this case, instantiate Verilog primitive nand gates
// Note, how the wires are connected in a cross coupled fashion.
nand n1(Q, Sbar, Qbar);
nand n2(Qbar, Rbar, Q);
// endmodule statement
endmodule
7. Prepared by Prof. Anand H. D., Dept. of ECE, Dr. AIT, Bengaluru-56 7
Modules
Modules and ports
// Module name and port list
// Stimulus module
module Top;
// Declarations of wire, reg, and other variables
wire q, qbar;
reg set, reset;
// Instantiate lower-level modules
// In this case, instantiate SR_latch
// Feed inverted set and reset signals to the SR latch
SR_latch m1(q, qbar, ~set, ~reset);
// Behavioral block, initial
initial
begin
$monitor($time, " set = %b, reset= %b, q= %bn",set,reset,q);
set = 0; reset = 0;
#5 reset = 1;
#5 reset = 0;
#5 set = 1;
end
// endmodule statement
endmodule
8. Prepared by Prof. Anand H. D., Dept. of ECE, Dr. AIT, Bengaluru-56 8
Modules
module SR_latch(Q, Qbar, Sbar, Rbar);
output Q, Qbar;
input Sbar, Rbar;
nand n1(Q, Sbar, Qbar);
nand n2(Qbar, Rbar, Q);
endmodule
module Top;
wire q, qbar;
reg set, reset;
SR_latch m1(q, qbar, ~set, ~reset);
initial
begin
$monitor($time, " set = %b, reset= %b, q= %bn",set,reset,q);
set = 0; reset = 0;
#5 reset = 1;
#5 reset = 0;
#5 set = 1;
end
endmodule
Modules and ports
Notice the following characteristics about the modules defined above:
• In the SR latch definition above , notice that all components described in Figure
need not be present in a module. We do not find variable declarations,
dataflow (assign) statements, or behavioral blocks (always or initial).
• However, the stimulus block for the SR latch contains module name, wire, reg,
and variable declarations, instantiation of lower level modules, behavioral block
(initial), and endmodule statement but does not contain port list, port declarations, and data flow
(assign) statements.
• Thus, all parts except module, module name, and endmodule are optional and can be mixed and
matched as per design needs.
9. Prepared by Prof. Anand H. D., Dept. of ECE, Dr. AIT, Bengaluru-56 9
Let us discuss about
Modules and ports
Modules
Ports
Hierarchical Names.
10. Prepared by Prof. Anand H. D., Dept. of ECE, Dr. AIT, Bengaluru-56 10
Ports
Ports provide the interface by which a module can communicate with its environment.
For example, the input/output pins of an IC chip are its ports. The environment can interact
with the module only through its ports.
The internals of the module are not visible to the environment. This provides a very powerful
flexibility to the designer. The internals of the module can be changed without affecting the
environment as long as the interface is not modified.
Modules and ports
Ports are also referred to as terminals.
1. List of Ports
A module definition contains an optional list of ports.
If the module does not exchange any signals with the environment, there are no ports in the
list.
Consider a 4-bit full adder that is instantiated inside a top-level module Top.
11. Prepared by Prof. Anand H. D., Dept. of ECE, Dr. AIT, Bengaluru-56 11
Ports
The diagram for the input/output ports is shown in Figure.
Notice that in the above figure, the module Top is a top-
level module.
The module fulladd4 is instantiated below Top. The
module fulladd4 takes input on ports a, b, and c_in and
produces an output on ports sum and c_out.
Thus, module fulladd4 performs an addition for its
environment.
Modules and ports
The module Top is a top-level module in the simulation and does not need to pass signals to
or receive signals from the environment. Thus, it does not have a list of ports
The module names and port lists for both module declarations in Verilog are as shown in
Example.
module fulladd4(sum, c_out, a, b, c_in); //Module with a list of ports
module Top; // No list of ports, top-level module in simulation
12. Prepared by Prof. Anand H. D., Dept. of ECE, Dr. AIT, Bengaluru-56 12
Ports
Modules and ports
2. Port Declaration
All ports in the list of ports must be declared in the module. Ports can be declared as follows:
Each port in the port list is defined as input,
output, or inout, based on the direction of the
port signal. Thus, for the example of the fulladd4
in Example, the port declarations will be as
shown
module fulladd4(sum, c_out, a, b, c_in);
//Begin port declarations section
output[3:0] sum;
output c_cout;
input [3:0] a, b;
input c_in;
//End port declarations section
...
<module internals>
...
endmodule
Note that all port declarations are implicitly declared as wire
in Verilog. Thus, if a port is intended to be a wire, it is
sufficient to declare it as output, input, or inout. Input or
inout ports are normally declared as wires.
However, if output ports hold their value, they must be
declared as reg. For example, in the definition of DFF, in
Example, we wanted the output q to retain its value until
the next clock edge. The port declarations for DFF will look
as shown in following Example
13. Prepared by Prof. Anand H. D., Dept. of ECE, Dr. AIT, Bengaluru-56 13
Ports
Modules and ports
Port Declarations for DFF
module DFF(q, d, clk, reset);
output q;
reg q; // Output port q holds value; therefore it is declared as reg.
input d, clk, reset;
...
...
endmodule
Ports of the type input and inout cannot be declared as reg because reg variables store
values and input ports should not store values but simply reflect the changes in the
external signals they are connected to.
Note that the module fulladd4 Example can be declared using an ANSI C style syntax to
specify the ports of that module. Each declared port provides the complete information
about the port.
14. Prepared by Prof. Anand H. D., Dept. of ECE, Dr. AIT, Bengaluru-56 14
Ports
Modules and ports
Following Example shows this alternate syntax.
This syntax avoids the duplication of naming the ports in both the module definition
statement and the module port list definitions.
If a port is declared but no data type is specified, then, under specific circumstances, the
signal will default to a wire data type.
Example ANSI C Style Port Declaration Syntax
module fulladd4(output reg [3:0] sum,
output reg c_out,
input [3:0] a, b, //wire by default
input c_in); //wire by default
...
<module internals>
...
endmodule
module fulladd4(sum, c_out, a, b, c_in);
//Begin port declarations section
output[3:0] sum;
output c_cout;
input [3:0] a, b;
input c_in;
//End port declarations section
...
<module internals>
...
endmodule
15. Prepared by Prof. Anand H. D., Dept. of ECE, Dr. AIT, Bengaluru-56 15
Ports
Modules and ports
3. Port Connection Rules
The internal and external units are connected.
There are rules governing port connections when
modules are instantiated within other modules.
The Verilog simulator complains if any port connection
rules are violated. These rules are summarized in Figure
Inputs: Internally, input ports must always be of the
type net. Externally, the inputs can be connected to a
variable which is a reg or a net.
Outputs: Internally, outputs ports can be of the type reg or net. Externally, outputs must
always be connected to a net. They cannot be connected to a reg.
One can visualize a port as consisting of two units, one unit that is internal to the module
and another that is external to the module
Inouts: Internally, inout ports must always be of the type net. Externally, inout ports must
always be connected to a net.
16. Prepared by Prof. Anand H. D., Dept. of ECE, Dr. AIT, Bengaluru-56 16
Ports
Modules and ports
Width matching
It is legal to connect internal and external items of different sizes when making intermodule
port connections. However, a warning is typically issued that the widths do not match.
Unconnected ports
Verilog allows ports to remain unconnected.
For example, certain output ports might be simply for debugging, and you might not be
interested in connecting them to the external signals.
You can let a port remain unconnected by instantiating a module as shown below.
fulladd4 fa0(SUM, , A, B, C_IN); // Output port c_out is unconnected
module Top;
//Declare connection variables
reg [3:0]A,B;
reg C_IN;
reg [3:0] SUM;
wire C_OUT;
//Instantiate fulladd4, call it fa0
fulladd4 fa0(SUM, C_OUT, A, B, C_IN);
.
<stimulus>
.
endmodule
/* Illegal connection because output port sum in
module fulladd4 is connected to a register variable
SUM in module Top. */
Illegal Port Connection
17. Prepared by Prof. Anand H. D., Dept. of ECE, Dr. AIT, Bengaluru-56 17
Ports
Modules and ports
4. Connecting Ports to External Signals
There are two methods of making connections between signals specified in the module
instantiation and the ports in a module definition.
These two methods cannot be mixed.
These methods are discussed in the following sections.
Connecting by ordered list
Connecting by ordered list is the most intuitive method for most beginners.
The signals to be connected must appear in the module instantiation in the same order as
the ports in the port list in the module definition.
Once again, consider the module fulladd4 defined. To connect signals in module Top by
ordered list, the Verilog code is shown.
Notice that the external signals SUM, C_OUT, A, B, and C_IN appear in exactly the same
order as the ports sum, c_out, a, b, and c_in in module definition of fulladd4..
18. Prepared by Prof. Anand H. D., Dept. of ECE, Dr. AIT, Bengaluru-56 18
Ports
Modules and ports
Connection by Ordered List
module Top;
//Declare connection variables
reg [3:0]A,B;
reg C_IN;
wire [3:0] SUM;
wire C_OUT;
//Instantiate fulladd4, call it fa_ordered.
//Signals are connected to ports in order
//(by position)
fulladd4 fa_ordered(SUM, C_OUT, A, B, C_IN);
...
<stimulus>
...
endmodule
module fulladd4(sum, c_out, a, b, c_in);
//Begin port declarations section
output[3:0] sum;
output c_cout;
input [3:0] a, b;
input c_in;
//End port declarations section
...
<module internals>
...
endmodule
Notice that the external signals SUM, C_OUT, A, B, and
C_IN appear in exactly the same order as the ports sum,
c_out, a, b, and c_in in module definition of fulladd4..
19. Prepared by Prof. Anand H. D., Dept. of ECE, Dr. AIT, Bengaluru-56 19
Ports
Modules and ports
Another advantage of
connecting ports by name is
that as long as the port name
is not changed, the order of
ports in the port list of a
module can be rearranged
without changing the port
connections in module
instantiations.
Connecting ports by name
For large designs where modules have, say, 50 ports, remembering the order of the ports in the
module definition is impractical and error-prone.
Verilog provides the capability to connect external signals to ports by the port names, rather than
by position.
We could connect the ports by name in Example above by instantiating the module fulladd4, as
follows. Note that you can specify the port connections in any order as long as the port name in the
module definition correctly matches the external signal
// Instantiate module fa_byname and connect signals to ports by name
fulladd4 fa_byname(.c_out(C_OUT), .sum(SUM), .b(B), .c_in(C_IN), .a(A),);
Note that only those ports that are to be connected to external signals must be specified in port
connection by name. Unconnected ports can be dropped.
For example, if the port c_out were to be kept unconnected, the instantiation of fulladd4 would look
as follows. The port c_out is simply dropped from the port list.
//Instantiate module fa_byname and connect signals to ports by name
fulladd4 fa_byname(.sum(SUM), .b(B), .c_in(C_IN), .a(A),);
20. Prepared by Prof. Anand H. D., Dept. of ECE, Dr. AIT, Bengaluru-56 20
Let us discuss about
Modules and ports
Modules
Ports
Hierarchical Names
21. Prepared by Prof. Anand H. D., Dept. of ECE, Dr. AIT, Bengaluru-56 21
Hierarchical Names
Modules and ports
Every module instance, signal, or variable is defined with an identifier. A particular
identifier has a unique place in the design hierarchy.
Hierarchical name referencing allows us to denote every identifier in the design hierarchy
with a unique name.
A hierarchical name is a list of identifiers separated by dots (".") for each level of hierarchy.
Thus, any identifier can be addressed from any place in the design by simply specifying the
complete hierarchical name of that identifier.
The top-level module is called the root module
because it is not instantiated anywhere. It is the
starting point.
To assign a unique name to an identifier, start from
the top-levelmodule and trace the path along the
design hierarchy to the desired identifier.
To clarify this process, let us consider the
simulation of SR latch. The design hierarchy is
shown in Figure.
22. Prepared by Prof. Anand H. D., Dept. of ECE, Dr. AIT, Bengaluru-56 22
Hierarchical Names
For this simulation, stimulus is the top-level module. Since the top-level module is not
instantiated anywhere, it is called the root module. The identifiers defined in this module
are q, qbar, set, and reset.
The root module instantiates m1, which is a module of type SR_latch. The module m1
instantiates nand gates n1 and n2. Q, Qbar, S, and R are port signals in instance m1.
Modules and ports
Hierarchical name referencing assigns a unique name
to each identifier. To assign hierarchical names, use
the module name for root module and instance
names for all module instances below the root
module.
Following Example shows hierarchical names for all
identifiers in the above simulation.
Notice that there is a dot (.) for each level of hierarchy
from the root module to the desired identifier.
23. Prepared by Prof. Anand H. D., Dept. of ECE, Dr. AIT, Bengaluru-56 23
Hierarchical Names
Modules and ports
Each identifier in the design is uniquely specified by
its hierarchical path name. To the level of hierarchy,
use the special character %m in the $display task.
24. Prepared by Prof. Anand H. D., Dept. of ECE, Dr. AIT, Bengaluru-56 24
Hierarchical Names
Modules and ports
Assignment1 Questions:
1. A 4-bit parallel shift register has I/O pins as
shown in the figure below. Write the module
definition for this module shift_reg. Include the
list of ports and port declarations. You do not
need to show the internals. .
2. Declare a top-level module stimulus. Define REG_IN (4 bit) and CLK (1 bit) as reg register
variables and REG_OUT (4 bit) as wire. Instantiate the module shift_reg and call it sr1.
Connect the ports by ordered list.
3. Declare a top-level module stimulus. Define REG_IN (4 bit) and CLK (1 bit) as reg register
variables and REG_OUT (4 bit) as wire. Instantiate the module shift_reg and call it sr1.
Connect the ports by name.
4. Write the hierarchical names for variables REG_IN, CLK, and REG_OUT, instance sr1 for
its ports clock and reg_in .
25. Prepared by Prof. Anand H. D., Dept. of ECE, Dr. AIT, Bengaluru-56 20
Reference
Samir Palnitkar, “Verilog HDL – A guide to Digital
Design and Synthesis”, Pearson, 2003
For Further Studies
Modules and ports
26. Prof. Anand H. D.
M. Tech. (PhD.)
Assistant Professor,
Department of Electronics & Communication Engineering
Dr. Ambedkar Institute of Technology, Bengaluru-56
Email: anandhd.ec@drait.edu.in
Phone: 9844518832