VLSI lab manual

VV COLLEGE OF ENGINEERING
VV Nagar, Arasoor, Sathankulam (TK)
Tisaiyanvillai (Via), Tuticorin-628 656.
Ph: 04637-273312
www.vvcoe.org
LAB MANUAL
SUBJECT : VLSI DESIGN LABORATORY
SUBJECT CODE : EC6612
CLASS/SEM : III/VI
EC6612 VLSI Lab Manual 1 Komala Vani Challa, AP/ECE, VVCOE

VV COLLEGE OF ENGINEERING
VV Nagar, Arasoor, Sathankulam (TK)
Tisaiyanvillai (Via), Tuticorin-628 656.
Ph: 04637-273312
www.vvcoe.org
BONAFIDE CERTIFICATE
Certified that this is bonafide record of work done by
Mr/Ms................................................................................................. of the ..................................
Semester in ................................…………………………………………………………………….. Engineering
of this college in the ..................................................................................................................…
during .........................................… in the partial fulfillment of the requirements of the B.E
degree course of the ANNA UNIVERSITY.
Staff in charge Head of the Department
University Registration No ..............................................
University Examination held on ..............................................
Internal Examiner External Examiner

S.
No.
Date Name of the Experiment Page
No.
Marks Signature
XILINX AND FPGA BASED EXPERIMENTS
1 HDL based design entry and simulation of
Logic Gates and Multiplexer.
2 HDL based design entry and simulation of
Simple counters, State Machines, 8-bit
Adder and 4-bit Multiplier
3 Synthesis P & R and post P & R simulation,
Critical paths and Static timing analysis of
the components simulated in (2).
4 Hardware fusing and testing of each of the
blocks simulated in (2).
CADENCE BASED EXPERIMENTS
5 Design, simulation and layout of a CMOS
inverter.
6 Design and simulation of a simple 5
transistor differential amplifier.
7 Layout generation and parasitic extraction
of differential amplifier.
8 Synthesis and Standard cell based design
of (2). Identification of critical paths and
power consumption.
9 P & R, power, clock routing and post P & R
simulation of (2).
10 Analysis of results of static timing analysis.

NOT Gate: NAND Gate:
Symbol Truth Table Symbol Truth Table
AND Gate: NOR Gate:
OR Gate: XNOR Gate:
XOR Gate:
Symbol Truth Table

Ex. No: 1 Date:
HDL BASED DESIGN ENTRY AND SIMULATION OF LOGIC GATES
AND MULTIPLEXER
AIM:
To design and simulate the logic gates and multiplexer using Verilog HDL.
SOFTWARE REQUIRED:
Xilinx 13.4 ISE– A project navigator software tool
PROGRAM:
Logic Gates
module LOGICGATES(A,B,Y_AND,Y_OR, Y_XOR, Y_XNOR, Y_NAND, Y_NOR, Y_NOT);
input A,B;
output Y_AND,Y_OR, Y_XOR, Y_XNOR, Y_NAND, Y_NOR, Y_NOT;
reg Y_XOR,Y_NOT;
assign Y_AND = A & B;
assign Y_OR = A | B;
always @ (A or B)
begin
Y_XOR = A ^ B;
Y_NOT = ~A;
end
nand N1(Y_NAND,A,B);
nor N2(Y_NOR,A,B);
xnor N3(Y_XNOR,A,B);
endmodule
Multiplexer
module mux(Y,D1,D0,S);
input [2:0] D1,D0;
input S;
output [2:0] Y;
reg [2:0] Y;
always @(D1 or D0 or S)
if (S == 1'b0)
Y = D0;
else
Y = D1;
endmodule

Logic Diagram for Multiplexer:
SIMULATION OUTPUT:
Logic gates
Multiplexer

PROCEDURE:
• Double click Xilinx ISE Design Suite 13.4 on the desktop or Go to Start –> All
programs –> Xilinx ISE Design Suite 13.4 –> ISE Design tools.
• Click on File –> New project. A new project wizard will open. Type the name of the
project and select the location. The top-level source type should be selected as HDL.
Click next.
• A new project wizard opens.
Product category :All
Family :Spartan 6
Device :XC6SLX45
Package :CSG324
Speed :-2
Top-level source type :HDL
Synthesis tool :XST(VHDL/Verilog)
Simulator :Isim(VHDL/Verilog)
Preferred language :Verilog
• Click next–>finish–>Right click on the project name shown in hierarchy and select
new source.
• New source wizard open. Select Verilog module and give program name as the file
name and click next and finish.
• Write the program and save it.
• In the process tab click on ‘+’ sign of synthesis and double click on check syntax.
• In the design tab select the simulation.
• Select the verilog module file in hierarchy tab and in process tab click on ‘+’ sign of
Isim simulator and double click on simulate behavioral model. The waveform displays.
• Give the inputs and verify the output through simulation results.
• Save the waveform.
RESULT:
Thus, the logic gates and multiplexer were designed and simulated using xilinx.

SIMULATION OUTPUT:
Up-Counter

Ex. No: 2 Date:
HDL BASED DESIGN ENTRY AND SIMULATION OF SIMPLE
COUNTERS, STATE MACHINES, 8-BIT ADDER AND 4-BIT MULTIPLIER
AIM:
To design and simulate the logic gates and multiplexer using Verilog HDL.
SOFTWARE REQUIRED:
PROGRAM:
Up-Counter
Verilog code:
module upcounter(clk,reset,count);
input clk,reset;
output reg[3:0]count;
wire clk,reset;
always@(posedge clk)
begin
if(reset)
count=4'b0000;
else
count=count+4'b1;
end
endmodule
Testbench:
module upcountertb;
// Inputs
reg clk;
reg reset;
// Outputs
wire [3:0] count;
// Instantiate the Unit Under Test (UUT)
upcounter uut (
.clk(clk),
.reset(reset),
.count(count)
);
initial begin
$display("timet clk reset count");
$display("%gt %b %b %b",
$time,clk,reset,count);
// Initialize Inputs
clk=1;
#2 reset=0;
#10 reset=1;
#10 reset=0;
#250 $finish;
end
always
begin
#10 clk=~clk;
end
endmodule

SIMULATION OUTPUT:
Down-Counter

Down-Counter
Verilog code:
module downcounter(clk,reset,count);
input clk,reset;
wire clk,reset;
begin
if(reset)
count=4'b0000;
else
count=count-4'b1;
end
endmodule
Testbench:
module downcountertb;
// Inputs
reg clk;
reg reset;
// Outputs
wire [3:0] count;
upcounter uut (
.clk(clk),
.reset(reset),
.count(count)
);
initial begin
clk=1;
#2 reset=0;
#10 reset=1;
#10 reset=0;
#250 $finish;
end
always
begin
#10 clk=~clk;
end
endmodule

SIMULATION OUTPUT:
Up-Down-Counter

Up-Down-Counter
Verilog code:
module updowncounter(clk,reset,UD,count);
input clk,reset,UD;
wire clk,reset;
begin
if(reset)
count=4'b0000;
elsif
(UD ==1)
count=count+4'b1;
else
count=count-4'b1;
end
endmodule
Testbench:
module updowncountertb;
// Inputs
reg clk;
reg reset;
reg UD;
// Outputs
wire [3:0] count;
updowncounter uut (
.clk(clk),
.reset(reset),
.count(count)
);
initial begin
clk=1;
#2 reset=0;
#10 reset=1;
#10 reset=0;
#50 UD=0;
#50 UD=1;
#250 $finish;
end
always
begin
#10 clk=~clk;
end
endmodule

DIVIDE-BY-3 COUNTER MOORE FSM:
SIMULATION OUTPUT:
Moore State Machine

Moore State Machine
Verilog code:
module Moorefsm(input clk,input reset,output
out);
reg[1:0]state,nextstate;
parameter S0=2'b00;
parameter S1=2'b01;
parameter S2=2'b10;
always @(posedge clk,posedge reset)
if(reset)state <=0;
else state<=nextstate;
always @(*)
case(state)
S0:nextstate<=S1;
S1:nextstate<=S2;
S2:nextstate<=S0;
default:nextstate<=S0;
endcase
assign out=(state==S2);
endmodule

MEALY FSM:
SIMULATION OUTPUT:
Mealy State Machine

Mealy State Machine
Verilog code:
module MealyFSM(input clk,
input reset,
input a,
output x, y);
reg [2:0] state, nextstate;
parameter S0 = 3'b000;
// State Register
always @(posedge clk, posedge reset)
if (reset) state <= S0;
else state <= nextstate;
// Next State Logic
always @ (*)
case (state)
S0: if (a) nextstate = S3;
else nextstate = S1;
default: nextstate = S0;
endcase
// Output Logic
assign x = (state [1] & ~a) | (state [2]& a);
assign y = (state [1] & state [0] & ~a) |
(state [2] & state [0] & a);
endmodule

8-bit Adder Block Diagram
1-bit Full adder Logic Diagram:
SIMULATION OUTPUT:
Eight-Bit Full Adder
In Unsigned decimal representation
In Binary representation

Eight-Bit Full Adder
Verilog code:
Eight-bit Full adder
module fa8bitadder(sum,carry,a,b,cin);
input [7:0] a,b;
input cin;
output [7:0] sum;
output carry;
wire c1,c2,c3,c4,c5,c6,c7;
fulladder fa0(sum[0],c1,a[0],b[0],cin);
fulladder fa1(sum[1],c2,a[1],b[1],c1);
fulladder fa7(sum[7],carry,a[7],b[7],c7);
endmodule
One-bit Full adder
module fulladder(sum,carry,a,b,cin);
input a,b,cin;
output sum,carry;
assign sum=a^b^cin;
assign carry=((a&b)|(b&cin)|(cin&a));
endmodule
Testbench:
module fatb;
// Inputs
reg [7:0] a;
reg [7:0] b;
reg cin;
// Outputs
wire [7:0] sum;
wire carry;
fa8bitadder uut (
.sum(sum),
.carry(carry),
.a(a),
.b(b),
.cin(cin)
);
initial begin
a=8'b00000001;b=8'b00000111;cin=1'b0;
$display("sum=%b,carry=%b",sum,carry);
#50 a=8'b00000001;b=8'b00000111;
#50 a=8'b01110001;b=8'b01100111;
#50 a=8'b11100001;b=8'b11000100;cin=1'b1;
#50 a=8'b00110001;b=8'b000011000;cin=1'b0;
#50 a=8'b10001001;b=8'b00110001;
#50 a=8'b11101101;b=8'b11111111;
#50 $finish;
end
endmodule

SIMULATION OUTPUT:
Multiplier

Multiplier
Verilog code:
module multiply4bits(product,inp1,inp2);
output [7:0]product;
input [3:0]inp1;
input [3:0]inp2;
assign product[0]=(inp1[0]&inp2[0]);
wire x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,
x13,x14,x15,x16,x17;
HA HA1(product[1],x1,(inp1[1]&inp2[0]),
(inp1[0]&inp2[1]));
FA FA1(x2,x3,inp1[1]&inp2[1],
(inp1[0]&inp2[2]),x1);
FA FA2(x4,x5,(inp1[1]&inp2[2]),
(inp1[0]&inp2[3]),x3);
HA HA2(x6,x7,(inp1[1]&inp2[3]),x5);
HA HA3(product[2],x15,x2,
(inp1[2]&inp2[0]));
FA FA5(x14,x16,x4,(inp1[2]&inp2[1]),x15);
FA FA4(x13,x17,x6,(inp1[2]&inp2[2]),x16);
FA FA3(x9,x8,x7,(inp1[2]&inp2[3]),x17);
HA HA4(product[3],x12,x14,
(inp1[3]&inp2[0]));
FA FA8(product[4],x11,x13,
(inp1[3]&inp2[1]),x12);
FA FA7(product[5],x10,x9,
(inp1[3]&inp2[2]),x11);
FA FA6(product[6],product[7],x8,
(inp1[3]&inp2[3]),x10);
endmodule
module HA(sout,cout,a,b); output sout,cout;
input a,b;
assign sout=a^b; assign cout=(a&b);
endmodule
module FA(sout,cout,a,b,cin); output
sout,cout;
input a,b,cin;
assign sout=(a^b^cin);
assign cout=((a&b)|(a&cin)|(b&cin));
endmodule

PROCEDURE:
• Double click Xilinx ISE Design Suite 13.4 on the desktop or Go to Start –> All
programs –> Xilinx ISE Design Suite 13.4 –> ISE Design tools.
• Click on File –> New project. A new project wizard will open. Type the name of the
project and select the location. The top-level source type should be selected as HDL.
Click next.
• A new project wizard opens.
Product category :All
Family :Spartan 6
Device :XC6SLX45
Package :CSG324
Speed :-2
Top-level source type :HDL
Synthesis tool :XST(VHDL/Verilog)
Simulator :Isim(VHDL/Verilog)
Preferred language :Verilog
• Click next–>finish–>Right click on the project name shown in hierarchy and select
new source.
• New source wizard open. Select Verilog module and give program name as the file
name and click next and finish. Write the program and save it.
• In the process tab click on ‘+’ sign of synthesis and double click on check syntax.
• In the hierarchy tab right click on the program and select new source.
• In the opened new source wizard select Verilog test fixture and then give file name and
click next and select the associate source and click next and then finish.
• Write the test bench code save it and select the simulation in design tab.
• Select the test bench file in hierarchy tab and in process tab click on ‘+’ sign of Isim
simulator and double click on simulate behavioral model .The waveform displays.
RESULT:
Thus, the counters, state machines, 8-bit adder and multiplier were designed and
simulated using testbench.

RTL SCHEMATIC FOR MULTIPLIER:
TECHNOLOGY SCHEMATIC FOR MULTIPLIER:

Ex. No: 3 Date:
SYNTHESIS, P&R AND POST P&R SIMULATION
AIM:
To synthesize, place & route and pin assign the logic circuits designed.
SOFTWARE REQUIRED:
PROCEDURE:
• Repeat the procedure of the 1st experiment.
• Select the program and double click on the synthesis.
• Click the “+” sign next to Synthesize – XST and double click on RTL Schematic and
Technology Schematic and view them.
• The Register Transfer Level (RTL) schematic view shows gates and elements independent of
the targeted Xilinx® device.
• Technology schematic view shows the design hierarchy in terms of the LUTs and buffers.
• Double click on Design Summary/Reports to see the Synthesis reports.
• In the Device Utilization Summary section, observe the number of Slice Flip Flops that were
used during implementation. To see other reports, scroll to the bottom of the Design
Summary.
• Double click on the User Constraints file. Now a '.ucf ' file opens automatically in the design
tab.
• Click on that file and double click on edit constraints in the process tab and write the pin
assignments.
• Click the “+” sign next to Implement Design. The Translate, Map, and Place & Route
processes are displayed. Expand those processes as well by clicking on the “+” sign.
• Double click on the Place and Route. A Plan Ahead window opens where the package and
device view of FPGA can be seen. Floor planning can be done here.
• Double click on the XPower analyzer to view the power analysis.

SYNTHESIS REPORT FOR MULTIPLIER:
Device utilization summary:
---------------------------
Selected Device : 6slx45csg324-2
Slice Logic Utilization:
Number of Slice LUTs: 20 out of 27288 0%
Number used as Logic: 20 out of 27288 0%
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 20
Number with an unused Flip Flop: 20 out of 20 100%
Number with an unused LUT: 0 out of 20 0%
Number of fully used LUT-FF pairs: 0 out of 20 0%
Number of unique control sets: 0
IO Utilization:
Number of IOs: 16
Number of bonded IOBs: 16 out of 218 7%
Maximum combinational path delay: 11.425ns
Timing Details:
---------------
All values displayed in nanoseconds (ns)
=======================================================================
==
Timing constraint: Default path analysis
Total number of paths / destination ports: 411 / 8
-------------------------------------------------------------------------
Delay: 11.425ns (Levels of Logic = 7)
Source: inp2<1> (PAD)
Destination: product<7> (PAD)
Data Path: inp2<1> to product<7>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 13 1.328 1.326 inp2_1_IBUF (inp2_1_IBUF)
LUT4:I1->O 3 0.235 0.994 HA1/cout1 (x1)
LUT6:I3->O 4 0.235 1.080 HA3/cout1 (x15)
LUT4:I0->O 2 0.254 0.834 FA5/cout1 (x16)
LUT6:I4->O 3 0.250 1.042 FA3/Mxor_sout_xo<0>1 (x9)
LUT6:I2->O 1 0.254 0.681 FA6/cout1 (product_7_OBUF)
OBUF:I->O 2.912 product_7_OBUF (product<7>)
----------------------------------------
Total 11.425ns (5.468ns logic, 5.957ns route)
(47.9% logic, 52.1% route)

Cross Clock Domains Report:
Total REAL time to Xst completion: 8.00 secs
Total CPU time to Xst completion: 7.95 secs
Total memory usage is 249264 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 1 ( 0 filtered)
P&R REPORT FOR MULTIPLIER:
All signals are completely routed.
Total REAL time to PAR completion: 48 secs
Total CPU time to PAR completion: 7 secs
Peak Memory Usage: 383 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Number of error messages: 0
POST P&R REPORT FOR MULTIPLIER:
Data Sheet report:
-----------------
Pad to Pad
Source Pad |Destination Pad| Delay |
---------------+---------------+---------+
inp1<0> |product<0> | 15.066|
inp1<0> |product<1> | 14.999|
inp1<0> |product<2> | 16.195|
inp1<0> |product<3> | 16.962|
inp1<0> |product<4> | 17.517|
inp1<0> |product<5> | 22.773|
inp1<0> |product<6> | 19.856|
inp1<0> |product<7> | 19.717|
inp1<1> |product<1> | 16.027|
inp1<1> |product<2> | 17.223|
inp1<1> |product<3> | 18.258|
inp1<1> |product<4> | 18.813|
inp1<1> |product<5> | 24.069|
---------------+---------------+---------+
inp2<0> |product<0> | 12.131|
inp2<0> |product<1> | 14.997|
inp2<0> |product<2> | 16.193|
inp2<0> |product<3> | 16.960|
inp2<0> |product<4> | 17.515|
inp2<0> |product<5> | 22.771|
inp2<0> |product<6> | 19.854|
inp2<0> |product<7> | 19.715|
inp2<1> |product<1> | 15.469|
inp2<1> |product<2> | 16.665|
inp2<1> |product<3> | 17.690|
inp2<1> |product<4> | 18.245|
inp2<1> |product<5> | 23.501|

inp1<1> |product<6> | 21.152|
inp1<1> |product<7> | 21.013|
inp1<2> |product<2> | 15.832|
inp1<2> |product<3> | 17.346|
inp1<2> |product<4> | 17.901|
inp1<2> |product<5> | 23.157|
inp1<2> |product<6> | 20.240|
inp1<2> |product<7> | 20.101|
inp1<3> |product<3> | 13.751|
inp1<3> |product<4> | 16.383|
inp1<3> |product<5> | 20.089|
inp1<3> |product<6> | 18.543|
inp1<3> |product<7> | 17.759|
inp2<1> |product<6> | 20.584|
inp2<1> |product<7> | 20.445|
inp2<2> |product<2> | 14.945|
inp2<2> |product<3> | 17.004|
inp2<2> |product<4> | 17.559|
inp2<2> |product<5> | 22.815|
inp2<2> |product<6> | 19.898|
inp2<2> |product<7> | 19.759|
inp2<3> |product<3> | 16.557|
inp2<3> |product<4> | 17.370|
inp2<3> |product<5> | 22.626|
inp2<3> |product<6> | 19.706|
inp2<3> |product<7> | 19.567|
Analysis completed Wed Feb 22 15:10:12 2017
--------------------------------------------------------------------------------
Trace Settings
PIN ASSIGNMENT FOR MULTIPLIER:
NET "inp1<0>" LOC = A10;
NET "inp1<1>" LOC = D14;
NET "inp1<2>" LOC = C14;
NET "inp1<3>" LOC = P15;
NET "inp2<0>" LOC = P12;
NET "inp2<1>" LOC = R5;
NET "inp2<2>" LOC = T5;
NET "inp2<3>" LOC = E4;
NET "product<7>" LOC = N12;
NET "product<6>" LOC = P16;
NET "product<5>" LOC = D4;
NET "product<4>" LOC = M13;
NET "product<3>" LOC = L14;
NET "product<2>" LOC = N14;

NET "product<1>" LOC = M14;
NET "product<0>" LOC = U18;
SYNTHESIS REPORT FOR 8-BIT ADDER:
Device utilization summary:
---------------------------
Selected Device : 6slx45csg324-2
Slice Logic Utilization:
Number of Slice LUTs: 12 out of 27288 0%
Number used as Logic: 12 out of 27288 0%
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 12
Number with an unused Flip Flop: 12 out of 12 100%
Number with an unused LUT: 0 out of 12 0%
Number of fully used LUT-FF pairs: 0 out of 12 0%
Number of unique control sets: 0
IO Utilization:
Number of IOs: 26
Number of bonded IOBs: 26 out of 218 11%
Timing Details:
Timing constraint: Default path analysis
Total number of paths / destination ports: 97 / 9
-------------------------------------------------------------------------
Delay: 9.703ns (Levels of Logic = 6)
Source: a<1> (PAD)
Destination: sum<7> (PAD)
Data Path: a<1> to sum<7>
Gate Net

RTL SCHEMATIC FOR 8-BIT ADDER:
RTL SCHEMATIC FOR INSTANTIATED 1-BIT FULLADDER:

Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 2 1.328 1.156 a_1_IBUF (a_1_IBUF)
LUT5:I0->O 3 0.254 0.874 fa1/carry1 (c2)
LUT5:I3->O 3 0.250 0.874 fa3/carry1 (c4)
LUT5:I3->O 3 0.250 0.874 fa5/carry1 (c6)
LUT5:I3->O 1 0.250 0.681 fa7/carry1 (carry_OBUF)
OBUF:I->O 2.912 carry_OBUF (carry)
----------------------------------------
Total 9.703ns (5.244ns logic, 4.459ns route)
(54.0% logic, 46.0% route)
Cross Clock Domains Report:
Total REAL time to Xst completion: 7.00 secs
Total CPU time to Xst completion: 6.96 secs
Total memory usage is 248624 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 1 ( 0 filtered)
P&R REPORT FOR 8-BIT ADDER:
All signals are completely routed.
Total REAL time to PAR completion: 47 secs
Total CPU time to PAR completion: 6 secs
Placer: Placement generated during map.
Routing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 0
Number of info messages: 2

TECHNOLOGY SCHEMATIC FOR 8-BIT ADDER:

POST P&R REPORT FOR 8-BIT ADDER:
Data Sheet report:
-----------------
Pad to Pad
---------------+---------------+---------+
---------------+---------------+---------+
a<0> |carry | 21.697|
a<0> |sum<0> | 14.838|
a<0> |sum<1> | 15.375|
a<0> |sum<2> | 15.496|
a<0> |sum<3> | 16.492|
a<0> |sum<4> | 19.085|
a<0> |sum<5> | 19.397|
a<0> |sum<6> | 19.829|
a<0> |sum<7> | 20.471|
a<1> |carry | 21.953|
a<1> |sum<1> | 15.631|
a<1> |sum<2> | 15.752|
a<1> |sum<3> | 16.748|
a<1> |sum<4> | 19.341|
a<1> |sum<5> | 19.653|
a<1> |sum<6> | 20.085|
a<1> |sum<7> | 20.727|
a<2> |carry | 21.228|
a<2> |sum<2> | 15.121|
a<2> |sum<3> | 16.023|
a<2> |sum<4> | 18.616|
a<2> |sum<5> | 18.928|
a<2> |sum<6> | 19.360|
---------------+---------------+---------+
---------------+---------------+---------+
b<0> |sum<4> | 16.621|
b<0> |sum<5> | 16.933|
b<0> |sum<6> | 17.365|
b<0> |sum<7> | 18.007|
b<1> |carry | 20.904|
b<1> |sum<1> | 14.582|
b<1> |sum<2> | 14.703|
b<1> |sum<3> | 15.699|
b<1> |sum<4> | 18.292|
b<1> |sum<5> | 18.604|
b<1> |sum<6> | 19.036|
b<1> |sum<7> | 19.678|
b<2> |carry | 20.257|
b<2> |sum<2> | 14.308|
b<2> |sum<3> | 15.052|
b<2> |sum<4> | 17.645|
b<2> |sum<5> | 17.957|
b<2> |sum<6> | 18.389|
b<2> |sum<7> | 19.031|
b<3> |carry | 20.958|
b<3> |sum<3> | 15.753|
b<3> |sum<4> | 18.346|
b<3> |sum<5> | 18.658|

a<2> |sum<7> | 20.002|
a<3> |carry | 19.298|
a<3> |sum<3> | 14.093|
a<3> |sum<4> | 16.686|
a<3> |sum<5> | 16.998|
a<3> |sum<6> | 17.430|
a<3> |sum<7> | 18.072|
a<4> |carry | 11.450|
a<4> |sum<4> | 8.884|
a<4> |sum<5> | 9.150|
a<4> |sum<6> | 9.582|
a<4> |sum<7> | 10.224|
a<5> |carry | 11.750|
a<5> |sum<5> | 9.450|
a<5> |sum<6> | 9.882|
a<5> |sum<7> | 10.524|
a<6> |carry | 10.998|
a<6> |sum<6> | 9.739|
a<6> |sum<7> | 9.772|
a<7> |carry | 10.505|
a<7> |sum<7> | 9.279|
b<0> |carry | 19.233|
b<0> |sum<0> | 12.730|
b<0> |sum<1> | 12.911|
b<0> |sum<2> | 13.032|
b<0> |sum<3> | 14.028|
b<3> |sum<6> | 19.090|
b<3> |sum<7> | 19.732|
b<4> |carry | 11.500|
b<4> |sum<4> | 9.355|
b<4> |sum<5> | 9.200|
b<4> |sum<6> | 9.632|
b<4> |sum<7> | 10.274|
b<5> |carry | 11.635|
b<5> |sum<5> | 9.335|
b<5> |sum<6> | 9.767|
b<5> |sum<7> | 10.409|
b<6> |carry | 10.583|
b<6> |sum<6> | 8.987|
b<6> |sum<7> | 9.357|
b<7> |carry | 10.356|
b<7> |sum<7> | 9.130|
cin |carry | 21.246|
cin |sum<0> | 14.420|
cin |sum<1> | 14.924|
cin |sum<2> | 15.045|
cin |sum<3> | 16.041|
cin |sum<4> | 18.634|
cin |sum<5> | 18.946|
cin |sum<6> | 19.378|
cin |sum<7> | 20.020|
Analysis completed Fri Mar 03 09:33:49 2017

PIN ASSIGNMENT FOR 8-BIT ADDER:
As Spartan 6 FPGA has only 8 input switches, we modify the program for 4-bit and dump into the kit.
NET "cin" LOC = F6;
NET "a<0>" LOC = A10;
NET "a<1>" LOC = D14;
NET "a<2>" LOC = C14;
NET "a<3>" LOC = P15;
NET "b<0>" LOC = P12;
NET "b<1>" LOC = R5;
NET "b<2>" LOC = T5;
NET "b<3>" LOC = E4;
NET "sum<0>" LOC = U18;
NET "sum<1>" LOC = M14;
NET "sum<2>" LOC = N14;
NET "sum<3>" LOC = L14;
NET "carry" LOC = M13;
RESULT:
Thus, the circuits in experiment (2) were synthesised, and their P&R , post P&R static
timing reports were generated , critical paths were found.

Figure: iMPACT Welcome Dialog Box

Ex. No: 4 Date:
GENERATION OF CONFIGURATION FILES, IMPLEMENTATION OF LOGIC
CIRCUITS IN FPGA DEVICE
AIM:
To generate the configuration files and download the design into the Spartan6 kit.
APPARATUS REQUIRED :
• Xilinx 13.4 ISE– A project navigator software tool
• Spartan 6 FPGA kit(XC6SLX45 CSG324)
• Power cable
• USB cable
PROCEDURE:
• Repeat the procedure of 3rd experiment.
• Next connect the 5V DC power cable to the power input on the kit.
• Connect the USB cable between the PC and kit.
• Select program in the Sources window.
• Double click on the Implementation to run it and it to see the translate, map and place
and route click on the “+” sign to expand.
• Double click on Xpiower Analyzer to see the power analysis
• In the Processes window, click the “+” sign to expand the Generate Programming File
processes.
• Double-click the Configure Device (iMPACT) process.
• iMPACT opens and the Configure Devices dialog box is displayed.
• In the Welcome dialog box, select Boundary-Scan.
• Right Click and select initialize chain.
• Now right click on the device and select Assign New Configuration File and select
the .bit file and click Open.
• Right-click on the device image, and select Program... The Programming
Properties dialog box opens.

Figure: Assign New Configuration File

• Click OK to program the device. When programming is complete, the Program
Succeeded message is displayed.
• Now give the inputs through switches in the FPGA kit and observe the output in the
LEDs.
RESULT:
The designed logic circuits were configured to FPGA device and hardware tested.

This is a table 1 of components for building the
Inverter schematic.
Figure 1
SCHEMATIC DIAGRAM OF INVERTER:
Figure 2

Ex. No: 5 Date:
DESIGN, SIMULATION AND LAYOUT OF A CMOS INVERTER
AIM:
To design the schematic and layout of a CMOS inverter and simulate it.
SOFTWARE REQUIRED:
CADENCE Virtuoso tool
PROCEDURE:
CREATING THE INVERTER SCHEMATIC
Creating a New library
1. In the Library Manager, execute File - New – Library. The new library form appears.
2. In the “New Library” form, type “myDesignLib” in the Name section. Note: A technology
file is not required if you are not interested to do the layouts for the design.
3. In the next “Technology File for New library” form, select option Attach to an
existing techfile and click OK.
4. In the “Attach Design Library to Technology File” form, select gpdk180.
Creating a Schematic Cellview
1. In the Library manager, execute File – New – Cellview.
2. Set up the New file form as shown in Figure 1.Do not edit the Library path file.
3. Click OK when done the above settings. A blank schematic window for the Inverter design
appears.
Adding Components to schematic
1. In the Inverter schematic window, click the Instance fixed menu icon to display the
Add Instance form or press i.
2. Click on the Browse button. This opens up a Library browser from which you can select
components and the symbol view. You will update the Library Name, Cell Name, and the
property values given in the table 1 as you place each component.
3. After you complete the Add Instance form, move your cursor to the schematic window and
click left to place a component. If you place a component with the wrong parameter values,
use the Edit— Properties— Objects command to change the parameters. Use the Edit—

Figure 3
GENERATED CMOS INVERTER SYMBOL:
Figure 4

Move command if you place components in the wrong location. You can rotate components
at the time you place them, or use the Edit— Rotate command after they are placed.
4. After entering components, click Cancel in the Add Instance form or press Esc with your
cursor in the schematic window.
Adding pins to Schematic
1. Click the Pin fixed menu icon in the schematic window.You can also execute
Create — Pin or press p. The Add pin form appears.
2. Type the following in the Add pin form in the exact order leaving space between the pin
names.
Pin Names Direction
vin Input
vout Output
3. Select Cancel from the Add – pin form after placing the pins.
In the schematic window, execute Window— Fit or press the f bindkey.
Adding Wires to a Schematic
1. Click the Wire (narrow) icon or w
key, in the schematic window.
2.Complete the wiring as shown in figure 2 and when done wiring press ESC key in the
schematic window to cancel wiring.
Saving the Design
1. Click the Check and Save icon in the schematic editor window.
2. Observe the CIW output area for any errors.
Symbol Creation
1. In the Inverter schematic window, execute Create — Cellview— From Cellview. With
the Edit Options function active, you can control the appearance of the symbol to generate.
2. Verify that the From View Name field is set to schematic, and the To View Name field
is set to symbol, with the Tool/Data Type set as SchematicSymbol.
3. Click OK in the Cellview From Cellview form. The Symbol Generation Form appears.
4. Modify the Pin Specifications as shown in Figure 3.
5. Click OK in the Symbol Generation Options form.
6. A new window displays an automatically created Inverter symbol as shown in Figure 4.

MODIFIED CMOS INVERTER SYMBOL:
Figure 5
Figure 6
Library name Cellview name Properties/Com
ments
myDesignLib Inverter Symbol
analogLib vpulse v1=0, v2=1.8,td=0
tr=tf=1ns, ton=10n,
T=20n
analogLib vdc, gnd vdc=1.8
Table 2

Editing a Symbol
1. Move the cursor over the automatically generated
symbol, until the green rectangle is highlighted, click left
to select it.
2. Click Delete icon in the symbol window, similarly select the red rectangle and delete that.
3. Execute Create – Shape – polygon, and draw a shape similar to triangle.
4. After creating the triangle press ESC key.
5. Execute Create – Shape – Circle to make a circle at the end of triangle.
6. You can move the pin names according to the location.
7. Execute Create — Selection Box. In the Add Selection Box form, click Automatic. A
new red selection box is automatically added.
8. After creating symbol, click on the save icon in the symbol editor window to save the
symbol(Figure 5).
BUILDING THE INVERTER_TEST DESIGN
Creating the Inverter_Test Cellview
In the CIW or Library Manager, execute File— New— Cellview. Set up the New File form
as as shown in Figure 6. Click OK when done. A blank schematic window for the
Inverter_Test design appears.
Building the Inverter_Test Circuit
1. Using the component list and Properties/Comments in this table, build the Inverter_Test
schematic.
2. Add the above components using Create — Instance or by pressing I.
3. Click the Wire (narrow) icon and wire your schematic.
4. Click Create — Wire Name or press L to name the input (Vin) and output (Vout)
wires as in the below schematic.
4. Click on the Check and Save icon to save the design.
5. The schematic should looks as shown in Figure 7.
6. Leave your Inverter_Test schematic window open for the next section.
Starting the Simulation Environment
1. In the Inverter_Test schematic window, execute Launch – ADE L. The Virtuoso
Analog Design Environment (ADE) simulation window appears.

Figure 7
Figure 8

2. In the simulation window (ADE), execute Setup— Simulator/Directory/Host.
3. In the Choosing Simulator form, set the Simulator field to spectre and click OK.
ANALOG SIMULATION WITH SPECTRE
Choosing Analyses
1. In the Simulation window (ADE), click the Choose - Analyses icon or execute Analyses -
Choose. The Choosing Analysis form appears.
2. As shown in Figure 8 setup for transient analysis
3. To set up for DC Analyses:
a. In the Analyses section, select dc.
b. In the DC Analyses section, turn on Save DC Operating Point.
c. Turn on the Component Parameter.
d. Double click the Select Component, Which takes you to the schematic window.
e. Select input signal vpulse source in the test schematic window.
f. Select DC Voltage― ‖ in the Select Component Parameter form and click OK.
f. In the analysis form type start and stop voltages as 0 to 1.8 respectively.
g. Check the enable button and then click Apply.
4. Click OK in the Choosing Analyses Form.
Setting Design Variables
1. In the Simulation window, click the Edit Variables icon. The Editing Design Variables
form appears.
3. Set the value of the wp variable. With the wp variable highlighted in the Table of Design
Variables, click on the variable name wp and enter the following:
Value(Expr) 2u
Selecting Outputs for Plotting
1. Execute Outputs – To be plotted – Select on Schematic in the simulation window.
2. Follow the prompt at the bottom of the schematic window, Click on output net Vout, input
net Vin of the Inverter. Press ESC with the cursor in the schematic after selecting it.
The simulation window looks as shown in Figure 9.
Running the Simulation
1. Execute Simulation – Netlist and Run in the simulation window to start the Simulation

Figure 9
SIMULATION OUTPUT:
Figure 10

or the icon, this will create the netlist as well as run the simulation.
2. When simulation finishes, the Transient, DC plots automatically will be popped up along
with log file.
Measuring the Propagation Delay
1. In the waveform window as shown in Figure 10 execute Tools – Calculator.
The calculator window appears.
2. From the functions select delay, this will open the delay data panel.
3. Place the cursor in the text box for Signal1, select the wave button and select the input
waveform from the waveform window.
4. Repeat the same for Signal2, and select the output waveform.
5. Set the Threshold value 1 and Threshold value 2 to 0.9, this directs the calculator to
calculate delay at 50% i.e. at 0.9 volts.
6. Execute OK and observe the expression created in the calculator buffer.
7. Click on Evaluate the buffer icon to perform the calculation, note down the value
returned after execution.
8. Close the calculator window.
Creating Layout View of Inverter
1. From the Inverter schematic window menu execute Launch – Layout XL. A Startup
Option form appears.
2. Select Create New option. This gives a New Cell View Form.
3. Check the Cellname (Inverter), Viewname (layout).
4. Click OK from the New Cellview form. LSW and a blank layout window appear along with
schematic window.
Adding Components to Layout
1. Execute Connectivity – Generate – All from Source or click the icon in the layout
editor window, Generate Layout form appears. Click OK which imports the schematic
components in to the Layout window automatically.
2. Re arrange the components with in PR-Boundary as shown in the Figure 11.
3. To rotate a component, Select the component and execute Edit –Properties. Now select
the degree of rotation from the property edit form.

Connection Contact Type
For Metal1- Poly
Connection
Metal1-Poly
For Metal1-
Psubstrate
Connection
Metal1-Psub
For Metal1-
Nwell Connection
Metal1-Nwell
Table 3
Figure 11

4. To Move a component, Select the component and execute Edit -Move command.
Making interconnection
1. Execute Connectivity –Nets – Show/Hide selected Incomplete Nets or click
the icon in the Layout Menu.
2. From the layout window execute Create – Shape – Path/ Create wire or Create –
Shape – Rectangle (for vdd and gnd bar) and select the appropriate Layers from the LSW
window and Vias for making the inter connections
Creating Contacts/Vias
1. Execute Create — Via or select command to place different Contacts, as given in below
table 3.
2. Save your design by selecting File — Save, layout should appear as shown in the Figure 11.
PHYSICAL VERIFICATION
ASSURA DRC
Running a DRC
1. Open the Inverter layout form the CIW or library manger. Press shift – f in the layout
window to display all the levels.
2. Select Assura - Run DRC from layout window. The DRC form appears. Select the
Technology as gpdk180. This automatically loads the rule file.
3. Click OK to start DRC.
4. A Progress form will appears. You can click on the watch log file to see the log file.
5. When DRC finishes, a dialog box appears asking you if you want to view your DRC results,
and then click Yes to view the results of this run.
6. If there any DRC error exists in the design View Layer Window (VLW) and Error
Layer Window (ELW) appears. Also the errors highlight in the design itself.
7. Click View – Summary in the ELW to find the details of errors.
8. You can refer to rule file also for more information, correct all the DRC errors and Re –
run the DRC.

Figure 12

9. If there are no errors in the layout then a dialog box appears with No DRC errors found
written in it, click on close to terminate the DRC run.
ASSURA LVS
Running LVS
1. Select Assura – Run LVS from the layout window. The Assura Run LVS form appears. It
will automatically load both the schematic and layout view of the cell.
2. Change in the form as shown in Figure 12 and click OK.
3. The LVS begins and a Progress form appears.
4. If the schematic and layout matches completely, the form displaying Schematic and Layout
Match appears.
5. If the schematic and layout do not matches, a form informs that the LVS completed
successfully and asks if you want to see the results of this run.
6. Click Yes in the form. LVS debug form appears, and you are directed into LVS debug
environment.
7. In the LVS debug form you can find the details of mismatches and you need to correct all
those mismatches and Re – run the LVS till you will be able to match the schematic with
layout.
RESULT:
Thus, the schematic and layout of a CMOS inverter was designed and simulated.

SCHEMATIC DIAGRAM OF A DIFFERENTIAL AMPLIFIER:
Figure 1

Ex. No: 6 Date:
DESIGN AND SIMULATION OF A SIMPLE 5 TRANSISTOR
DIFFERENTIAL AMPLIFIER.
AIM:
To design the schematic of a differential amplifier and simulate it.
SOFTWARE REQUIRED:
PROCEDURE:
CREATING THE DIFFERENTIAL AMPLIFIER SCHEMATIC
• Create a new library.
• Create a schematic cellview.
• Add the components to the schematic by giving the following specifications.
Library name Cell
Name
Properties/Comments
gpdk180 nmos Model Name = nmos1 (NM0,
NM1) ; W= 3u ; L= 1u
gpdk180 nmos Model Name =nmos1 (NM2,
NM3) ; W= 4.5u ; L= 1u
gpdk180 pmos Model Name =pmos1 (PM0,
PM1);
• After you complete the Add Instance form, move your cursor to the schematic window
and click left to place a component.
• Type the following in the Add pin form in the exact order leaving space between the pin
names.
Pin Names Direction
Idc,V1,V2 Input
Vout Output
vdd, vss, InputOutput
• Press w and complete the wiring as shown in figure 1 and when done wiring, press ESC

DIFFERENTIAL AMPLIFIER SYMBOL
Figure 2
Figure 3

key in the schematic window to cancel wiring.
• Save the schematic disgram.
• In the schematic window, execute Create — Cellview— From Cellview. With the
Edit Options function active, you can control the appearance of the symbol to generate.
• Modify the Pin Specifications.
• Click OK in the Symbol Generation Options form.
• A new window displays an automatically created symbol as shown in Figure 2.
• Save the design.
• Using the component list and Properties/Comments as shown in the table, build the
Diff_amplifier_test schematic as shown in Figure 3.
Library name Cellview name Properties/Comments
myDesignLib Diff_amplifier Symbol
analogLib vsin Define specification as
AC Magnitude= 1;
Amplitude= 5m;
Frequency= 1K
analogLib vdd, vss, gnd Vdd=2.5 ; Vss= -2.5
analogLib Idc Dc current = 30u
• Leave your Diff_amplifier_test schematic window open for the next section.
• In the Diff_amplifier_test schematic window, execute Launch – ADE L. The Analog
Design Environment simulation window appears.
• In the simulation window or ADE, execute Setup— Simulator/Directory/Host.
• In the Choosing Simulator form, set the Simulator field to spectre and click OK.
• In the Simulation window, click the Choose - Analyses icon.
• The Choosing Analysis form appears.
• To setup for transient analysis
a. In the Analysis section select tran
b. Set the stop time as 5m
c. Click at the moderate or Enabled button at the bottom, and then click Apply.
• To set up for DC Analyses:
a. In the Analyses section, select dc.
b. In the DC Analyses section, turn on Save DC Operating Point.

SIMULATION OUTPUT:
Figure 5

c. Turn on the Component Parameter
d. Double click the Select Component, Which takes you to the schematic
window.
e. Select input signal Vsin for dc analysis.
f. In the analysis form, select start and stop voltages as -5 to 5 respectively.
g. Check the enable button and then click Apply.
• To set up for AC Analyses form is shown in the previous page.
a. In the Analyses section, select ac.
b. In the AC Analyses section, turn on Frequency.
c. In the Sweep Range section select start and stop frequencies as 150 to
100M
d. Select Points per Decade as 20.
e. Check the enable button and then click Apply.
• Click OK in the Choosing Analyses Form.
• Execute Outputs – To be plotted – Select on Schematic in the simulation
window.
• Follow the prompt at the bottom of the schematic window, Click on output net Vo,
input net Vin of the Diff_amplifier. Press ESC with the cursor in the schematic after
selecting node. The simulation window looks as shown in figure 4.
• Execute Simulation – Netlist and Run in the simulation window to start the
simulation, this will create the netlist as well as run the simulation.
• When simulation finishes, the Transient, DC and AC plots automatically will be popped
up along with netlist.
• To Calculate the gain of Differential pair, Configure the Differential pair schematic as
shown in figure 6.
• Now, open the ADE L, from LAUNCH --> ADE L , choose the analysis set the ac
response and run the simulation, from Simulation --> Run.
• Next go to Results -->Direct plot select AC dB20 and output from the schematic and
press escape. The waveform appears as shown in figure 7.
• To Calculate the BW of the Differential pair, open the calculator and select the
bandwidth option, select the waveform of the gain in dB and press Evaluate the buffer,

Figure 6
Figure 7

Figure 8
Figure 9

Figure 10
Figure 11

• the waveform appears as shown in figure 8.
• To Calculate the CMRR of the Differential pair, Configure the Differential pair
schematic to calculate the differential gain as shown 9.
• In the ADE L, plot the ac response with gain in dB. Measure the gain at 100hz and at
100Mhz,note down the value of the gain in dB, as shown in figure 10.
• Configure the Differential pair schematic to calculate the common-mode gain as shown
in figure 11.
• In the ADE L, plot the ac response with gain in dB. Measure the gain at 100hz and at
100Mhz, note down the value of the gain in dB, as shown below
• Calculate the CMRR, add the gains in dB i.e., Ad – (-Ac).
RESULT:
Thus, the schematic of a differential amplifier was designed, simulated and CMRR is
calculated.

Table 1
Connection Contact Type
For Metal1- Poly
Connection
Metal1-Poly
For Metal1- Psubstrate
Connection
Metal1-Psub
For Metal1- Nwell
Connection
Metal1-Nwell
Figure 1

Ex. No: 7 Date:
LAYOUT GENERATION AND PARASITIC EXTRACTION OF
DIFFERENTIAL AMPLIFIER.
AIM:
To generation the Layout and do parasitic extraction for a differential amplifier.
SOFTWARE REQUIRED:
PROCEDURE:
Creating a Layout View of Diff_ Amplifier
1. From the Diff_amplifier schematic window menu execute Launch – Layout XL. A
Startup Option form appears.
2. Select Create New option. This gives a New Cell View Form.
3. Check the Cellname (Diff_amplifier), Viewname (layout).
4. Click OK from the New Cellview form.
Adding Components to Layout
1. Execute Connectivity – Generate – All from Source or click the icon in the layout
editor window, Generate Layout form appears. Click OK which imports the schematic
components in to the Layout window automatically.
2. Re arrange the components with in PR-Boundary as shown in the next page.
3. To rotate a component, Select the component and execute Edit –Properties. Now select
the degree of rotation from the property edit form.
4. To Move a component, Select the component and execute Edit -Move command.
Making interconnection
1. Execute Connectivity –Nets – Show/Hide selected Incomplete Nets or click
the icon in the Layout Menu.
2. Move the mouse pointer over the device and click LMB to get the connectivity information,

Figure 2

which shows the guide lines (or flight lines) for the inter connections of the components.
3. From the layout window execute Create – Shape – Path or Create – Shape –
Rectangle (for vdd and gnd bar) and select the appropriate Layers from the LSW window
and Vias for making the inter connections
Creating Contacts/Vias
1. Execute Create — Via to place different Contacts, as given in table 1.
2. Save your design by selecting File — Save to save the layout. The layout appears as shown
in figure 1.
PHYSICAL VERIFICATION
ASSURA DRC
Running a DRC
1. Open the Differential Amplifier layout form the CIW or library manger. Press shift – f in
the layout window to display all the levels.
2. Select Assura - Run DRC from layout window. The DRC form appears. Select the
Technology as gpdk180. This automatically loads the rule file.
3. Click OK to start DRC.
4. A Progress form will appears. You can click on the watch log file to see the log file.
5. When DRC finishes, a dialog box appears asking you if you want to view your DRC results,
and then click Yes to view the results of this run.
6. If there any DRC error exists in the design View Layer Window (VLW) and Error
Layer Window (ELW) appears. Also the errors highlight in the design itself.
7. Click View – Summary in the ELW to find the details of errors.
8. You can refer to rule file also for more information, correct all the DRC errors and Re –
run the DRC.
9. If there are no errors in the layout then a dialog box appears with No DRC errors found
written in it, click on close to terminate the DRC run.
ASSURA LVS
Running LVS
1. Select Assura – Run LVS from the layout window. The Assura Run LVS form appears. It
will automatically load both the schematic and layout view of the cell.
2. Change in the form as shown in Figure 12 and click OK.

Figure 3

3. The LVS begins and a Progress form appears. Verify the specifications in the Run Assura
LVS form shown in figure 2.
4. If the schematic and layout matches completely, the form displaying Schematic and Layout
Match appears.
5. If the schematic and layout do not matches, a form informs that the LVS completed
successfully and asks if you want to see the results of this run.
6. Click Yes in the form. LVS debug form appears, and you are directed into LVS debug
environment.
7. In the LVS debug form you can find the details of mismatches and you need to correct all
those mismatches and Re – run the LVS till you will be able to match the schematic with
layout.
ASSURA RCX
Running RCX
1. From the layout window execute Assura – Run RCX.
2. Make the changes as shown in figure 3, in the Assura parasitic extraction form. Select
output type under Setup tab of the form.
3. In the Extraction tab of the form shown in figure 4, choose Extraction type, Cap Coupling
Mode and specify the Reference node for extraction.
4. In the Filtering tab of the form, Enter Power Nets as vdd!, vss! and Enter Ground
Nets as gnd!
5. Click OK in the Assura parasitic extraction form when done. The RCX progress form
appears, in the progress form click Watch log file to see the output log file.
6. When RCX completes, a dialog box appears, informs you that Assura RCX run
completed successfully.
7. Open the av_extracted view from the library manager and view the parasitic.
RESULT:
Thus, the layout of a differential amplifier was generated and the parasitic extraction was
done.

SIMULATION OUTPUT:
RTL SCHEMATIC:

Ex. No: 8 Date:
SYNTHESIS AND STANDARD CELL BASED DESIGN OF COUNTER
AIM:
To Synthesis and design a counter using Standard cell and to identify the critical paths
and power consumption.
SOFTWARE REQUIRED:
CADENCE NCLaunch and Encounter tool
PROCEDURE:
• Create a folder, right click inside the folder and open a blank document and write the
coding for counter and save with the extension .v.
• Right click inside the folder and open a blank document and write the test bench
• Right click and select open terminal in that folder. Now type the following commands.
csh
source /cad/cshrc
nclaunch -new
• Now click on multi-step create cds file save.→ →
• Select don't include any libraries.
• Nclaunch window appears.
• Compile counter.v and counter_test files. Now the files appears under work lib.
• Expand the worklib & elaborate counter.v and counter_test files. Now the files appears
under snapshot.
• Expand the snapshot and select counter_test file and simulate it.
• Two panels design and console are displayed.
• In the design panel, right click on the counter and select add to waveform window.
• Run the simulation.
• To see the full simulation click on = symbol in the waveform window.
• Now create a synthesize.tcl file and write the code to generate the reports for area,

POWER REPORT:
Leakage Dynamic Total
Instance Cells Power(nW) Power(nW)
Power(nW)
-------------------------------------------------
counter_main 21 1486.946 24081.425
25568.371
AREA REPORT:
Instance Cells Cell Area Net Area Total
Area Wireload
-------------------------------------------------------------
------
counter_main 21 238 0 238
<none> (D)
GATE REPORT:
Gate Instances Area Library
--------------------------------------
CLKINVX1 4 9.083 slow
DFFRX1 1 21.950 slow
INVXL 3 6.812 slow
NAND2BX1 1 4.541 slow
NAND2XL 1 3.028 slow
OR2X1 4 18.166 slow
SDFFRHQX1 7 174.844 slow
--------------------------------------
total 21 238.423
Type Instances Area Area %
------------------------------------
sequential 8 196.794 82.5
inverter 7 15.895 6.7
logic 6 25.735 10.8
------------------------------------
total 21 238.423 100.0
STANDARD CELLS PLACEMENT:

• power, timing and number of gates.
csh
source /cad/cshrc
rc -f synthesize.tcl -gui
• In the command window, the reports and the critical path can be seen.
• The netlist file is generated in the folder.
• An encounter window opens automatically. Double click on the counter to see the RTL
schematic.
• To see the power report, select Report Power Detailed report.→ →
csh
source /cad/cshrc
encounter
• Click on File Import design browse and select counter.netlist . Add and make it as→ →
top cell and select auto assign and click on load to select the default.globals file.
• The imported design appears. To see the full view, press F.
• Select Floorplan Specify floorplan and give the following specifications→
core to left = 10 right = 10 top = 10 bottom = 10
• Select Power Power planning add rings . Select VDD and VSS and add them as→ →
rings.
• Select Layer Top→ bottom left right
Metal8 Metal8 Metal8 Metal8
channel center→
• Select Power planning add stripes and select VDD and VSS, Layer as M8, No. of sets→
in set pattern as 3.
• Select Route Special Route and select VDD and VSS.→
• Select Place place standard cells.→
RESULT:
Thus, the counter is synthesized, simulated, standard cells were placed, power report
was found and the critical path was identified.

ADDING RINGS TO THE DESIGN:
ADDING STRIPES TO THE DESIGN:

Ex. No: 9 Date:
P & R, POWER, CLOCK ROUTING AND POST P & R SIMULATION OF
COUNTER
AIM:
To P & R, power, clock routing and post P & R simulation of counter.
SOFTWARE REQUIRED:
CADENCE NCLaunch and Encounter tool
PROCEDURE:
• Create a folder, right click inside the folder and open a blank document and write the
• Now create a synthesize.tcl file and write the code to generate the reports for area,
power, timing and number of gates.
csh
source /cad/cshrc
rc -f synthesize.tcl -gui
• In the command window, the reports and the critical path can be seen.
• The netlist file is generated in the folder.
• An encounter window opens automatically. Double click on the counter to see the RTL
schematic.
• To see the power report, select Report Power Detailed report.→ →
csh
source /cad/cshrc
encounter
• Click on File Import design browse and select counter.netlist . Add and make it as→ →
•

CLOCK ROUTING THE DESIGN:
ROUTING THE STANDARD CELL BASED DESIGN :
POST P& R SIMULATION OUTPUT:

rings.
channel center→
ok
• Select Clock Synthesis clock tree. Browse and add all the clock signals.→
• Select optimize optimizing design, select post CTS and hold mode.→
• Select route nano route.→
• Now save the design in .gds format.
csh
source /cad/cshrc
nclaunch
• Nclaunch window appears.
• Compile & elaborate counter.v and counter_test files.
• Expand the snapshot and select counter_test file and simulate it.
• In the design panel, right click on the counter and select add to waveform window.
• Run the simulation.
• To see the full simulation click on = symbol in the waveform window.
RESULT:
Thus, P & R, power, clock routing and post P & R simulation of counter was performed.

TIMING REPORT:
PRE P&R TIMING:
------------------------------------------------------------
timeDesign Summary
------------------------------------------------------------
+--------------------+---------+---------+---------+---------+---------+---------+
| Setup mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
| WNS (ns):| 8.286 | 8.286 | 9.016 | 8.603 | N/A | N/A |
| TNS (ns):| 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| Violating Paths:| 0 | 0 | 0 | 0 | N/A | N/A |
| All Paths:| 38 | 22 | 8 | 8 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
Density: 0.000%
Total Memory Usage: 479.871094 Mbytes
PRE P&R TIMING:
------------------------------------------------------------
timeDesign Summary
------------------------------------------------------------
+--------------------+---------+---------+---------+---------+---------+---------+
+--------------------+---------+---------+---------+---------+---------+---------+
| WNS (ns):| 8.112 | 8.112 | 9.015 | 8.573 | N/A | N/A |
| TNS (ns):| 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| All Paths:| 38 | 22 | 8 | 8 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 0 (0) | 0.000 | 0 (0) |
| max_tran | 0 (0) | 0.000 | 0 (0) |
| max_fanout | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density:87.017%

Ex. No: 10 Date:
STATIC TIMING ANALYSIS OF COUNTER
AIM:
To analyse the static timing results of counter.
SOFTWARE REQUIRED:
CADENCE Encounter tool
PROCEDURE:
csh
source /cad/cshrc
encounter
• Click on File Import design browse and select counter.netlist. Add and make it as→ →
rings.
channel center→
• Select timing report timing pre-P&R ok. In the command window the timing→ → →
report is displayed.
• Select timing report timing post P&R . In the command window the timing report→ →
is displayed

POST CTS FOR SETUP - ANALYSIS:
+--------------------+---------+---------+---------+---------+---------+---------+
+--------------------+---------+---------+---------+---------+---------+---------+
| WNS (ns):| 8.181 | 8.181 | 9.019 | 8.555 | N/A | N/A |
| TNS (ns):| 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| All Paths:| 38 | 22 | 8 | 8 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
Density: 92.248%
Total Real time: 1.0 sec
POST CTS FOR HOLD – ANALYSIS WITH VIOLATIONS:
+--------------------+---------+---------+---------+---------+---------+---------+
| Hold mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
| WNS (ns):| -0.003 | -0.003 | N/A | N/A | N/A | N/A |
| TNS (ns):| -0.003 | -0.003 | N/A | N/A | N/A | N/A |
| Violating Paths:| 1 | 1 | N/A | N/A | N/A | N/A |
| All Paths:| 22 | 22 | N/A | N/A | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
Density: 92.248%
Routing Overflow: 0.00% H and 0.00% V
------------------------------------------------------------
Reported timing to dir timingReports
Total CPU time: 0.14 sec
Total Real time: 0.0 sec
POST CTS FOR HOLD – ANALYSIS WITHOUT VIOLATIONS:
+--------------------+---------+---------+---------+---------+---------+---------+
| Hold mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
| WNS (ns):| 0.001 | 0.001 | N/A | N/A | N/A | N/A |
| TNS (ns):| 0.001 | 0.001 | N/A | N/A | N/A | N/A |
| Violating Paths:| 0 | 0 | N/A | N/A | N/A | N/A |
| All Paths:| 22 | 22 | N/A | N/A | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+

• Select timing report timing pre CTS . In the command window the timing report→ →
is displayed.
• Select Clock Synthesis clock tree. Browse and add all the clock signals.→
• Select timing report timing post CTS setup mode. In the command window the→ → →
timing report is displayed.
• Select timing report timing post CTS hold mode. In the command window the→ → →
timing report is displayed.
• If there are any violations then the results will be negative.
• Select optimize optimizing design, select post CTS and hold mode.→
• Now the results will be positive and there won't be any violations.
• Select route nano route.→
• Now save the design in .gds format.
RESULT:
Thus, the static timing analysis of counter was done.

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