It is a challenging task for a VLSI design engineer to develop low power VLSI circuits, without sacrificing its performance. Feedthrough Logic (FTL) is a new technology which could be considered better than the existing technologies for improving circuit efficiency. Modified Feedthrough Logic (MFTL), offers a better power factor than the FTL logic structures, and also shows an improvement in the speed factor. But the scenario again changes when the design extends to nano scales of device dimension, where many factors which were neglected otherwise need to be given more importance. To avoid or minimize problems like hot carrier effects, electro migration, drain induced barrier lowering and other issues that becomes prominent in nano scale MOSFET‟s, Carbon Nanotube Field Effect Transistor (CNTFET) is considered to be a promising candidate in future integrated circuits. Hence this work extends the advantages of MFTL logic into nano level by incorporating CNTFETs in place of MOSFETs. The modifications have been implemented using CNTFETs of 16nm technology from HSPICE library on a 10 chain inverter stage, an 8 bit RCA and a Vedic multiplier and performance factors like PDP and ADP are compared to that of the conventional MOSFET circuits.
This document discusses the design of high frequency 32/33 prescalers using a 2/3 prescaler technique. It analyzes different types of flip-flops that can be used in prescaler circuits including master-slave, pulse-triggered, differential, and dual-edge triggered. Dual-edge triggered and pulse-triggered flip-flops are determined to be unsuitable for prescaler circuits. Various implementations of divide-by-2/3 prescalers using true single phase clock (TSPC) and extended TSPC (ETSPC) flip-flops are presented and compared in terms of operating frequency, power, delay, and power-delay product. Simulation results show that ETSPC designs
Iaetsd design of a low power multiband clock distribution circuitIaetsd Iaetsd
This document describes the design of a low power multiband clock distribution circuit using a single phase clock. It proposes a dynamic logic divider based on pulse swallow topology that uses a low power 2/3 prescaler and multimodulus 32/33/47/48 prescaler. The divider allows programming to divide over a wide range of frequencies for applications like Bluetooth, Zigbee, and WiFi. It is modeled in Verilog and implemented using Xilinx tools with a power consumption of 0.96-2.2mW.
This document presents the design of low power CMOS high performance true single phase clock dual modulus prescalers. It describes a glitch elimination TSPC D-flip flop design used in synchronous counters. Transmission gates are used in the critical path and control logic for mode selection. Power efficient 3/4 and 15/16 prescaler designs are presented and their performance is compared to previous work through Eldo simulation. Simulation results show the improved speed, lower power consumption, and flexibility of the proposed prescaler designs in the frequency range of 0.5-3.125GHz.
Iaetsd low power pulse triggered flipflop withIaetsd Iaetsd
This document describes a novel low-power pulse-triggered flip-flop design with a conditional pulse enhancement scheme. The design improves on existing pulse-triggered FF designs in two ways: 1) It reduces the number of transistors in the discharge path from four to three, speeding up the discharge operation. 2) It uses an additional transistor to conditionally enhance the discharge pulse width only when needed, allowing for smaller transistor sizes and reduced power. Simulation results show the proposed design has the best power-delay product performance compared to seven other FF designs, with up to a 38.4% power savings. It also reduces average leakage power by a factor of 3.52 compared to a conventional transmission gate FF.
A Novel Flipflop Topology for High Speed and Area Efficient Logic Structure D...IOSR Journals
In high speed data path network flop is one of the major functional elements to store intermediate
results and data at different stages. But the most important problem is huge power utilization due to switching
activity and increase in clock period that is Timing Latency; causes the performance of data path in digital
design is decreased. The existing works implement various Flipflop topology in data path structure design such
as conventional Transmission Gate Based Master Slave Filpflop (TGMS FF), Write Port Master Slave Flip-flop
(WPMS) and Clocked Complementary Metal Oxide Semiconductor (C2MOS). In WPMS method, area is
minimized but delay is increased. In C2MOS technique Power consumption and delay is reduced, but there is a
definite scope to reduce Power, area and delay. In this paper a Modified Clocked Complementary Metal Oxide
Semiconductor Latch (mC2MOS Latch) is proposed and delay, power is again reduced up to 60% and the area
of the circuit is also reduced while comparing with previous methods.
A Survey Analysis on CMOS Integrated Circuits with Clock-Gated Logic StructureIJERA Editor
Various circuit design techniques has been presented to improve noise tolerance of the proposed CGS logic families. Noise in deep submicron technology limits the reliability and performance of ICs. The ANTE (Average Noise Threshold Energy) metric is used for the analysis of noise tolerance of proposed CGS. A 2-input NAND and NOR gate is designed by the proposed technique. Simulation results for a 2-input NAND gate at clock gated logic show that the proposed noise tolerant circuit achieves 1.79X ANTE improvement along with the reduction in leakage power. Continuous scaling of technology towards the manometer range significantly increases leakage current level and the effect of noise. This research can be further extended for performance optimization in terms of power, speed, area and noise immunity.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
DESIGN OF A LOW POWER MULTIBAND CLOCK DISTRIBUTION CIRCUIT USING SINGLE PHASE...IJERA Editor
The clock distribution network consumes nearly 70% of the total power consumed by the integrated circuit since
this is the only signal which has the highest switching activity. Normally for a multiband clock domain network
we develop a multiple PLL to cater the need. This project aim for developing a low power true single phase
clock(TSPC) multiband network which will supply for the multi clock domain network. In this paper, a wide
band 2/3 prescaler is verified in the design of proposed wide band multimodulus 32/33/47/48 or 64/65/78/79
prescaler. A dynamic logic multiband flexible integer-n divider based on pulse swallow topology is proposed
which uses a low power wide band 2/3 prescaler and a wide band multimodulus 32/33/47/48 or 64/65/78/79
prescaler. Since the multimodulus 32/33/47/48 or 64/65/78/79 prescaler has a maximum operating frequency of
6.2GHz, the values of P and S counters can actually be programmed to divide over the whole range of
frequencies. However the P and S counter are programmed accordingly. The proposed multiband flexible
divider also uses an improved loadable bit cell for swallow counter and consumes a power of 0.96 and 2.2mW.
This project is highly useful and recommended for communication applications like Bluetooth, Zigbee, IEEE
802.15.4 and 802.11 a/b/g WLAN frequency synthesizers which are proposed based on pulse swallow topology.
This design is modelled using Verilog simulated tool „MODELSIM 6.4b‟ and implemented and synthesized
using „Xilinx ISE 10.1‟.
This document discusses the design of high frequency 32/33 prescalers using a 2/3 prescaler technique. It analyzes different types of flip-flops that can be used in prescaler circuits including master-slave, pulse-triggered, differential, and dual-edge triggered. Dual-edge triggered and pulse-triggered flip-flops are determined to be unsuitable for prescaler circuits. Various implementations of divide-by-2/3 prescalers using true single phase clock (TSPC) and extended TSPC (ETSPC) flip-flops are presented and compared in terms of operating frequency, power, delay, and power-delay product. Simulation results show that ETSPC designs
Iaetsd design of a low power multiband clock distribution circuitIaetsd Iaetsd
This document describes the design of a low power multiband clock distribution circuit using a single phase clock. It proposes a dynamic logic divider based on pulse swallow topology that uses a low power 2/3 prescaler and multimodulus 32/33/47/48 prescaler. The divider allows programming to divide over a wide range of frequencies for applications like Bluetooth, Zigbee, and WiFi. It is modeled in Verilog and implemented using Xilinx tools with a power consumption of 0.96-2.2mW.
This document presents the design of low power CMOS high performance true single phase clock dual modulus prescalers. It describes a glitch elimination TSPC D-flip flop design used in synchronous counters. Transmission gates are used in the critical path and control logic for mode selection. Power efficient 3/4 and 15/16 prescaler designs are presented and their performance is compared to previous work through Eldo simulation. Simulation results show the improved speed, lower power consumption, and flexibility of the proposed prescaler designs in the frequency range of 0.5-3.125GHz.
Iaetsd low power pulse triggered flipflop withIaetsd Iaetsd
This document describes a novel low-power pulse-triggered flip-flop design with a conditional pulse enhancement scheme. The design improves on existing pulse-triggered FF designs in two ways: 1) It reduces the number of transistors in the discharge path from four to three, speeding up the discharge operation. 2) It uses an additional transistor to conditionally enhance the discharge pulse width only when needed, allowing for smaller transistor sizes and reduced power. Simulation results show the proposed design has the best power-delay product performance compared to seven other FF designs, with up to a 38.4% power savings. It also reduces average leakage power by a factor of 3.52 compared to a conventional transmission gate FF.
A Novel Flipflop Topology for High Speed and Area Efficient Logic Structure D...IOSR Journals
In high speed data path network flop is one of the major functional elements to store intermediate
results and data at different stages. But the most important problem is huge power utilization due to switching
activity and increase in clock period that is Timing Latency; causes the performance of data path in digital
design is decreased. The existing works implement various Flipflop topology in data path structure design such
as conventional Transmission Gate Based Master Slave Filpflop (TGMS FF), Write Port Master Slave Flip-flop
(WPMS) and Clocked Complementary Metal Oxide Semiconductor (C2MOS). In WPMS method, area is
minimized but delay is increased. In C2MOS technique Power consumption and delay is reduced, but there is a
definite scope to reduce Power, area and delay. In this paper a Modified Clocked Complementary Metal Oxide
Semiconductor Latch (mC2MOS Latch) is proposed and delay, power is again reduced up to 60% and the area
of the circuit is also reduced while comparing with previous methods.
A Survey Analysis on CMOS Integrated Circuits with Clock-Gated Logic StructureIJERA Editor
Various circuit design techniques has been presented to improve noise tolerance of the proposed CGS logic families. Noise in deep submicron technology limits the reliability and performance of ICs. The ANTE (Average Noise Threshold Energy) metric is used for the analysis of noise tolerance of proposed CGS. A 2-input NAND and NOR gate is designed by the proposed technique. Simulation results for a 2-input NAND gate at clock gated logic show that the proposed noise tolerant circuit achieves 1.79X ANTE improvement along with the reduction in leakage power. Continuous scaling of technology towards the manometer range significantly increases leakage current level and the effect of noise. This research can be further extended for performance optimization in terms of power, speed, area and noise immunity.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
DESIGN OF A LOW POWER MULTIBAND CLOCK DISTRIBUTION CIRCUIT USING SINGLE PHASE...IJERA Editor
The clock distribution network consumes nearly 70% of the total power consumed by the integrated circuit since
this is the only signal which has the highest switching activity. Normally for a multiband clock domain network
we develop a multiple PLL to cater the need. This project aim for developing a low power true single phase
clock(TSPC) multiband network which will supply for the multi clock domain network. In this paper, a wide
band 2/3 prescaler is verified in the design of proposed wide band multimodulus 32/33/47/48 or 64/65/78/79
prescaler. A dynamic logic multiband flexible integer-n divider based on pulse swallow topology is proposed
which uses a low power wide band 2/3 prescaler and a wide band multimodulus 32/33/47/48 or 64/65/78/79
prescaler. Since the multimodulus 32/33/47/48 or 64/65/78/79 prescaler has a maximum operating frequency of
6.2GHz, the values of P and S counters can actually be programmed to divide over the whole range of
frequencies. However the P and S counter are programmed accordingly. The proposed multiband flexible
divider also uses an improved loadable bit cell for swallow counter and consumes a power of 0.96 and 2.2mW.
This project is highly useful and recommended for communication applications like Bluetooth, Zigbee, IEEE
802.15.4 and 802.11 a/b/g WLAN frequency synthesizers which are proposed based on pulse swallow topology.
This design is modelled using Verilog simulated tool „MODELSIM 6.4b‟ and implemented and synthesized
using „Xilinx ISE 10.1‟.
Spur Reduction Of MB-OFDM UWB System using CMOS Frequency SynthesizerIDES Editor
This document presents a design for an all-digital phase locked loop (ADPLL) frequency synthesizer to reduce spurs in an MB-OFDM UWB system. The proposed design replaces an analog PLL with an ADPLL composed of fully digital components. It includes a phase frequency detector, time-to-digital converter, digitally controlled oscillator, and frequency divider. Simulation results show the ADPLL locks the reference clock frequency and reduces spurs through multiplexing and mixing stages. The ADPLL approach overcomes limitations of analog PLL designs and allows for lower power consumption and reduced noise compared to traditional analog implementations.
The document describes a proposed design for a low power implicit pulse triggered flip-flop (P-FF). P-FFs have advantages over conventional master-slave FFs in high-speed applications and can reduce clock power consumption. The proposed design uses only transistor switching logic with 8 transistors, reducing power and area compared to other P-FF designs. Simulations show the proposed design has lower power consumption of 2.339μW compared to other designs. The design achieves lower power and area through a reduced transistor count.
enhancement of low power pulse triggered flip-flop design based on signal fee...Kumar Goud
Abstract: Low Power research major concern in today’s VLSI word. Practically, clocking system like flip-flop (FF) consumes large portion of total chip power. So in this paper we discuss about the design of the clock system using novel Flip-Flop design. In this paper, a novel low-power pulse-triggered flip-flop (FF) design is presented. Pulse- triggered FF (P-FF) has been considered as a popular alternative to the conventional master –slave based F. a low-power flip-flop (FF) design featuring an explicit type pulse-triggered structure and a modified true single phase clock latch based on a signal feed-through scheme is presented. The proposed design successfully solves the long discharging path problem in conventional explicit type pulse-triggered FF (P-FF) designs and achieves better speed and power performance in the applications of high speed. These circuits are simulated using Tanner Tools with TSMC018 technology.
Keywords: pulse-triggered flip-flop (FF), true single phase clock latch, clocking system
High Speed Low Power CMOS Domino or Gate Design in 16nm Technologycsandit
Dynamic logic circuits provide more compact designs with faster switching speeds and low power consumption compared with the other CMOS design styles. This paper proposes a wide
fan-in circuit with increased switching speed and noise immunity. Speed is achieved by quickly removing the charge on the dynamic node during evaluation phase, compared to the other
circuits. The design also offers very less Power Delay Product (PDP). The design is exercised for 20% variation in supply voltage.
Design and Analysis of Second and Third Order PLL at 450MHzVLSICS Design
Designing of an analog circuit satisfying the design constraints for desired application is a challenging job. Phase Lock Loop (PLL) is an important analog circuit used in various communication applications such as frequency synthesizer, radio, computer, clock generation, clock recovery, global positioning system, etc. Since all these applications are operating at different frequency, satisfying design constraints for PLL with respect to type of PLL operating frequency, Bandwidth, Settling time and other parameters is an critical and time consuming issue. In this paper, selection and design for Second order and third order PLL suggested using MATLAB, Simulink as a simulation tool. The simulated results for the design PLL at 450 MHz indicates good accuracy when the behavior model is compared with the mathematical model. Finally the performance of PLL is tested and calculated for parameters like lock time, lock range, Bandwidth.
DESIGN OF A HIGH PRECISION, WIDE RANGED ANALOG CLOCK GENERATOR WITH FIELD PRO...VLSICS Design
This paper presents a circuit of a high-precision, wide ranged, analog clock generator with on-chip programmability feature using Floating-gate transistors. The programmable oscillator can attain a continuous range of time-periods lying in the programming precision range of Floating Gates. The circuit consists of two sub circuits: Current Generator circuit and Wave Generator circuit. The current of current generator circuit is programmable and mirrored to the wave generator to generate the desired square wave. The topology is well suited to applications like clocking high performance ADCs and DACs as well as used as the internal clock in structured analog CMOS designs. A simulation model of the circuit was built in T-Spice, 0.35µm CMOS process. The circuit results in finely tuned clock with programmability precision of about 13bit [1]. Simulation results show high amount of temperature insensitivity (0.507ns/°C) for a large range of thermal conditions. The proposed circuit can compensate any change in temperature. The circuit design can be operated at low supply voltage i.e., 1v.
A high speed low power consumption d flip flop for high speed phase frequency...IAEME Publication
Phase Frequency Detector (PFD) and Frequency divider are indispensable modules of PLL,
which uses D flip-flop as an integral part. This paper focus on design of High-Speed, Low Power
Consumption D Flip-Flop for High Speed Phase Frequency Detector and Frequency divider. The
designed Frequency divider has been used in the divider counter of the phase locked loop. A divide
counter is required in the feedback loop to scales down the frequency of the VCO output signal. The
conventional and proposed D-Flip flop has been designed in UMC 180nm CMOS Technology with
supply voltage 1.8 using CADENCE spectre tool. Virtuoso Analog Design Environment tool of
Cadence have used to design and simulate schematic. This work has been used in the design of 2.4
GHz CMOS PLL targeting Frequency Multiplier application. The proposed D flip flop circuit is
faster than the conventional circuit as it has fast reset operation. The circuit consumes less power as
it prevents short circuit power consumption.
The document summarizes two new buffer circuit designs for footed domino logic that aim to reduce power consumption. The proposed circuits minimize redundant switching at the output node during the precharge phase, which saves power. Simulation results using a 180nm CMOS technology show that the proposed circuits reduce power consumption and power-delay product compared to a standard domino circuit across different logic functions, loading conditions, clock frequencies, temperatures and power supplies. Power savings of up to 36% were achieved at higher operating frequencies.
Theoretical Analysis of a two-stage Sagnac loop filter Using Jones Matrices IJECEIAES
In this work, a theoretical analysis of a Sagnac loop filter (SLF) with twostage polarization maintaining fibers (PMFs) and polarization controllers (PCs) is presented. The transmission function of this two-stage SLF is calculated in detail by using Jones matrix. The calculation is performed in order to investigate the filtering characteristics. The theoretical results show that the wavelength interval is depending on the dynamic settings of the length of the PMFs and the polarization angle of the PCs. By changing the polarization angle of the PCs, a multiple of single, dual or triple wavelength in each channel can be achieved. Based on this study, a flat multiwavelength spectrum can be obtained by adjusting the PMFs and the PCs in the twostage SLF. This finding significantly contributes to the generation of multiwavelength fiber laser (MWFL) that can be used for many optical applications.
This document describes a hybrid full adder design using both CMOS and transmission gate technologies that achieves low power and high speed. The design is divided into modules: 1) an XOR-XNOR module using weak inverters to reduce power, 2) a sum generation module using transmission gates, and 3) a carry generation module using strong transmission gates to reduce delay. Simulation results show the hybrid full adder achieves a power dissipation of 2.94μW and delay of 61.4ps at 1.8V in a 180nm technology, with lower power at lower voltages. This design coupled weak inverters with strong transmission gates to achieve both low power and high speed.
A High Speed Pipelined Dynamic Circuit Implementation Using Modified TSPC Log...IDES Editor
This document presents a modified True Single Phase Clock (TSPC) logic design style to implement high-speed pipelined circuits with improved performance. The modified style reduces transistor count by 40-50% compared to the standard TSPC style by allowing logic functions to be implemented using either the N-block or P-block. A 3-bit pipelined adder was designed using the modified style and showed a 46-47% reduction in transistors and 50% reduction in clock cycles compared to the standard style. The modified style offers benefits like lower transistor count, reduced latency, increased throughput, and lower power consumption for pipelined circuits.
My first comprehensive wlan presentation in the draft-11n days in 2008.
Note: Lots of text and pictures are used from across the web, author doesn't claim any copyright on them. In case of issues/feedback please email: chaitanya.mgit@gmail.com
Efficient Method of Power Saving Topologically-Compressed With 21Transistor’s...IJMTST Journal
The increasing market trends of extremely low power operated handy applications like laptop, electronic gadgets etc requires microelectronic devices with low power consumption. It is obvious that the transistor dimensions continues to shrink and as require for more complex chips increases, power management of such deep sub-micron based chip is one of the major challenges in VLSI industry. The manufacturers are always targeting for low power designs for the reason that to provide adequate physical resources to withstand against design hurdles and this lead to increases the cost and restrict the functionality of the device. This power reduction ratio is the highest among FFs that have been reported so far. The reduction is achieved by applying topological compression technique, merger of logically equivalent transistors to an eccentric latch structure. Fewer transistors, only three, connected to clock signal which reduces the power drastically, and the smaller total transistor count assures to retain the chip area as conventional FFs. In addition, fully static full-swing operation makes the cell lenient of supply voltage and input slew variation. An experimental chip design with 40 nm CMOS technology shows that almost all conventional FFs are expendable with proposed FF while preserving the same system performance and layout area. The performance of this paper is evaluated on the design simulation using HSPICE simulator.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
A dual pulse-clock double edge triggered flip-flopKavitha Reddy
The document proposes a new dual-pulse-clock double edge triggered D flip-flop (DPDET) for low voltage and high speed applications. The DPDET uses a split output latch clocked by a dual pulse train from an external generator. It uses only 6 transistors, reducing transistor count by 40-70% compared to other double edge triggered flip-flops. Simulation results show the DPDET operates at 2.7GHz at 3.3V and 224MHz at 0.9V, with 41% and 49% higher speed than other designs at 3.3V and 2.5V respectively. Power is also reduced by 36% and 29% at those voltages. The DPDET is suitable for low voltage
CNFET BASED BASIC GATES AND A NOVEL FULLADDER CELLVLSICS Design
In this paper two novel high performance designs for AND and OR basic gates and a novel Full-Adder Cell are presented. These designs are based on carbon nanotube technology. In order to compare the proposed designs with previous ones both MOSFET based and CNFET based circuits are selected. By the way the proposed designs have better performance in comparison with previous designs in terms of speed, power consumption and power-delay product (PDP).
An OFDM System Based on Dual Tree Complex Wavelet Transform (DT-CWT)CSCJournals
This document presents a study comparing an orthogonal frequency division multiplexing (OFDM) system based on dual-tree complex wavelet transform (DT-CWT) to conventional OFDM and wavelet packet modulation (WPM) based OFDM systems. The key findings are:
1) The proposed DT-CWT based OFDM system achieves significantly better bit error rate performance than conventional OFDM and WPM based OFDM systems.
2) The proposed system also achieves about 3 dB better peak-to-average power ratio performance compared to conventional OFDM and WPM based systems, indicating greater signal stability.
3) The performance of the proposed DT-CWT based OFDM system is not
Implementation for Controller to Unified Single Phase Power Flow Using Digita...IJERA Editor
Presenting in his paper, Digital signal processor (DSP)-based implementation of a single phase unified power flow controller (UPFC). For shunt side and series side An efficient UPFC control algorithm is achieved. Discussing the laboratory experimental results using DC source are taken as an UPFC linked by two ll-bridge PWM voltage source converters.
Knowledge Discovery Applied to a Database of Errors of Systems DevelopmentIJERA Editor
This paper presents the knowledge discovery process in a database related to the development of computer systems through the Apriori algorithm. This method of data mining was succesfull in discovering of patterns of relationships between kinds of non-conformities found during the software development and relationships of noncompliance with the kinds of tasks to be performed as an association between two variables "Simple" and "Average" in more than fifty percent of the cases whit tasks labeled as "Improvement". The discovered rules may assist in the decision making by development systems managers in order to reduce non-conformities related to the development of computational systems.
The Cortisol Awakening Response Using Modified Proposed Method of Forecasting...IJERA Editor
A growing body of data suggests that a significantly enhanced salivary cortisol response to waking may indicate
an enduring tendency to abnormal cortisol regulation. More methods have been proposed to deal with
forecasting problems using fuzzy time series. In this paper, our objective was to apply the response test to a
population already known to have long-term hypothalamo–pituitary–adrenocortical (HPA) axis dysregulation.
We hypothesized that the free cortisol response to waking, believed to be genetically influenced, would be
elevated in a significant percent age of cases, regard less of the afternoon Dexamethasone Suppression Test
(DST) value based on fuzzy time series and genetic algorithms. The proposed method adjusts the length of each
interval in the universe of discourse for forecasting the Longitudinal Dexamethasone Suppression Test (DST)
data on a fully remitted lithium responder for past 5 years who was asymptomatic and treated with lithium
throughout the experimental results show that the proposed method gets good forecasting results.
Stability and stabilization of discrete-time systems with time-delay via Lyap...IJERA Editor
The stability and stabilization problems for discrete systems with time-delay are discussed .The stability and
stabilization criterion are expressed in the form of linear matrix inequalities (LMI). An effective method
allowing us transforming a bilinear matrix Inequality (BMI) to a linear matrix Inequality (LMI) is developed.
Based on these conditions, a state feedback controller with gain is designed. An illustrative numerical example
is provided to show the effectiveness of the proposed method and the reliability of the results.
Experimental Plans and Intensive Numerical Aided DesignIJERA Editor
This document discusses a new method for optimizing product design called intensive numerical simulation. It proposes reversing the traditional design process by conducting intensive simulations based on manufacturing knowledge before creating the CAD model. Experimental design plans are used to efficiently run a large number of simulations. The method aims to help small-to-medium enterprises obtain unexpected gains in areas like mass and better use of manufacturing resources. Results show the approach is a promising new way for computer-aided design.
Spur Reduction Of MB-OFDM UWB System using CMOS Frequency SynthesizerIDES Editor
This document presents a design for an all-digital phase locked loop (ADPLL) frequency synthesizer to reduce spurs in an MB-OFDM UWB system. The proposed design replaces an analog PLL with an ADPLL composed of fully digital components. It includes a phase frequency detector, time-to-digital converter, digitally controlled oscillator, and frequency divider. Simulation results show the ADPLL locks the reference clock frequency and reduces spurs through multiplexing and mixing stages. The ADPLL approach overcomes limitations of analog PLL designs and allows for lower power consumption and reduced noise compared to traditional analog implementations.
The document describes a proposed design for a low power implicit pulse triggered flip-flop (P-FF). P-FFs have advantages over conventional master-slave FFs in high-speed applications and can reduce clock power consumption. The proposed design uses only transistor switching logic with 8 transistors, reducing power and area compared to other P-FF designs. Simulations show the proposed design has lower power consumption of 2.339μW compared to other designs. The design achieves lower power and area through a reduced transistor count.
enhancement of low power pulse triggered flip-flop design based on signal fee...Kumar Goud
Abstract: Low Power research major concern in today’s VLSI word. Practically, clocking system like flip-flop (FF) consumes large portion of total chip power. So in this paper we discuss about the design of the clock system using novel Flip-Flop design. In this paper, a novel low-power pulse-triggered flip-flop (FF) design is presented. Pulse- triggered FF (P-FF) has been considered as a popular alternative to the conventional master –slave based F. a low-power flip-flop (FF) design featuring an explicit type pulse-triggered structure and a modified true single phase clock latch based on a signal feed-through scheme is presented. The proposed design successfully solves the long discharging path problem in conventional explicit type pulse-triggered FF (P-FF) designs and achieves better speed and power performance in the applications of high speed. These circuits are simulated using Tanner Tools with TSMC018 technology.
Keywords: pulse-triggered flip-flop (FF), true single phase clock latch, clocking system
High Speed Low Power CMOS Domino or Gate Design in 16nm Technologycsandit
Dynamic logic circuits provide more compact designs with faster switching speeds and low power consumption compared with the other CMOS design styles. This paper proposes a wide
fan-in circuit with increased switching speed and noise immunity. Speed is achieved by quickly removing the charge on the dynamic node during evaluation phase, compared to the other
circuits. The design also offers very less Power Delay Product (PDP). The design is exercised for 20% variation in supply voltage.
Design and Analysis of Second and Third Order PLL at 450MHzVLSICS Design
Designing of an analog circuit satisfying the design constraints for desired application is a challenging job. Phase Lock Loop (PLL) is an important analog circuit used in various communication applications such as frequency synthesizer, radio, computer, clock generation, clock recovery, global positioning system, etc. Since all these applications are operating at different frequency, satisfying design constraints for PLL with respect to type of PLL operating frequency, Bandwidth, Settling time and other parameters is an critical and time consuming issue. In this paper, selection and design for Second order and third order PLL suggested using MATLAB, Simulink as a simulation tool. The simulated results for the design PLL at 450 MHz indicates good accuracy when the behavior model is compared with the mathematical model. Finally the performance of PLL is tested and calculated for parameters like lock time, lock range, Bandwidth.
DESIGN OF A HIGH PRECISION, WIDE RANGED ANALOG CLOCK GENERATOR WITH FIELD PRO...VLSICS Design
This paper presents a circuit of a high-precision, wide ranged, analog clock generator with on-chip programmability feature using Floating-gate transistors. The programmable oscillator can attain a continuous range of time-periods lying in the programming precision range of Floating Gates. The circuit consists of two sub circuits: Current Generator circuit and Wave Generator circuit. The current of current generator circuit is programmable and mirrored to the wave generator to generate the desired square wave. The topology is well suited to applications like clocking high performance ADCs and DACs as well as used as the internal clock in structured analog CMOS designs. A simulation model of the circuit was built in T-Spice, 0.35µm CMOS process. The circuit results in finely tuned clock with programmability precision of about 13bit [1]. Simulation results show high amount of temperature insensitivity (0.507ns/°C) for a large range of thermal conditions. The proposed circuit can compensate any change in temperature. The circuit design can be operated at low supply voltage i.e., 1v.
A high speed low power consumption d flip flop for high speed phase frequency...IAEME Publication
Phase Frequency Detector (PFD) and Frequency divider are indispensable modules of PLL,
which uses D flip-flop as an integral part. This paper focus on design of High-Speed, Low Power
Consumption D Flip-Flop for High Speed Phase Frequency Detector and Frequency divider. The
designed Frequency divider has been used in the divider counter of the phase locked loop. A divide
counter is required in the feedback loop to scales down the frequency of the VCO output signal. The
conventional and proposed D-Flip flop has been designed in UMC 180nm CMOS Technology with
supply voltage 1.8 using CADENCE spectre tool. Virtuoso Analog Design Environment tool of
Cadence have used to design and simulate schematic. This work has been used in the design of 2.4
GHz CMOS PLL targeting Frequency Multiplier application. The proposed D flip flop circuit is
faster than the conventional circuit as it has fast reset operation. The circuit consumes less power as
it prevents short circuit power consumption.
The document summarizes two new buffer circuit designs for footed domino logic that aim to reduce power consumption. The proposed circuits minimize redundant switching at the output node during the precharge phase, which saves power. Simulation results using a 180nm CMOS technology show that the proposed circuits reduce power consumption and power-delay product compared to a standard domino circuit across different logic functions, loading conditions, clock frequencies, temperatures and power supplies. Power savings of up to 36% were achieved at higher operating frequencies.
Theoretical Analysis of a two-stage Sagnac loop filter Using Jones Matrices IJECEIAES
In this work, a theoretical analysis of a Sagnac loop filter (SLF) with twostage polarization maintaining fibers (PMFs) and polarization controllers (PCs) is presented. The transmission function of this two-stage SLF is calculated in detail by using Jones matrix. The calculation is performed in order to investigate the filtering characteristics. The theoretical results show that the wavelength interval is depending on the dynamic settings of the length of the PMFs and the polarization angle of the PCs. By changing the polarization angle of the PCs, a multiple of single, dual or triple wavelength in each channel can be achieved. Based on this study, a flat multiwavelength spectrum can be obtained by adjusting the PMFs and the PCs in the twostage SLF. This finding significantly contributes to the generation of multiwavelength fiber laser (MWFL) that can be used for many optical applications.
This document describes a hybrid full adder design using both CMOS and transmission gate technologies that achieves low power and high speed. The design is divided into modules: 1) an XOR-XNOR module using weak inverters to reduce power, 2) a sum generation module using transmission gates, and 3) a carry generation module using strong transmission gates to reduce delay. Simulation results show the hybrid full adder achieves a power dissipation of 2.94μW and delay of 61.4ps at 1.8V in a 180nm technology, with lower power at lower voltages. This design coupled weak inverters with strong transmission gates to achieve both low power and high speed.
A High Speed Pipelined Dynamic Circuit Implementation Using Modified TSPC Log...IDES Editor
This document presents a modified True Single Phase Clock (TSPC) logic design style to implement high-speed pipelined circuits with improved performance. The modified style reduces transistor count by 40-50% compared to the standard TSPC style by allowing logic functions to be implemented using either the N-block or P-block. A 3-bit pipelined adder was designed using the modified style and showed a 46-47% reduction in transistors and 50% reduction in clock cycles compared to the standard style. The modified style offers benefits like lower transistor count, reduced latency, increased throughput, and lower power consumption for pipelined circuits.
My first comprehensive wlan presentation in the draft-11n days in 2008.
Note: Lots of text and pictures are used from across the web, author doesn't claim any copyright on them. In case of issues/feedback please email: chaitanya.mgit@gmail.com
Efficient Method of Power Saving Topologically-Compressed With 21Transistor’s...IJMTST Journal
The increasing market trends of extremely low power operated handy applications like laptop, electronic gadgets etc requires microelectronic devices with low power consumption. It is obvious that the transistor dimensions continues to shrink and as require for more complex chips increases, power management of such deep sub-micron based chip is one of the major challenges in VLSI industry. The manufacturers are always targeting for low power designs for the reason that to provide adequate physical resources to withstand against design hurdles and this lead to increases the cost and restrict the functionality of the device. This power reduction ratio is the highest among FFs that have been reported so far. The reduction is achieved by applying topological compression technique, merger of logically equivalent transistors to an eccentric latch structure. Fewer transistors, only three, connected to clock signal which reduces the power drastically, and the smaller total transistor count assures to retain the chip area as conventional FFs. In addition, fully static full-swing operation makes the cell lenient of supply voltage and input slew variation. An experimental chip design with 40 nm CMOS technology shows that almost all conventional FFs are expendable with proposed FF while preserving the same system performance and layout area. The performance of this paper is evaluated on the design simulation using HSPICE simulator.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
A dual pulse-clock double edge triggered flip-flopKavitha Reddy
The document proposes a new dual-pulse-clock double edge triggered D flip-flop (DPDET) for low voltage and high speed applications. The DPDET uses a split output latch clocked by a dual pulse train from an external generator. It uses only 6 transistors, reducing transistor count by 40-70% compared to other double edge triggered flip-flops. Simulation results show the DPDET operates at 2.7GHz at 3.3V and 224MHz at 0.9V, with 41% and 49% higher speed than other designs at 3.3V and 2.5V respectively. Power is also reduced by 36% and 29% at those voltages. The DPDET is suitable for low voltage
CNFET BASED BASIC GATES AND A NOVEL FULLADDER CELLVLSICS Design
In this paper two novel high performance designs for AND and OR basic gates and a novel Full-Adder Cell are presented. These designs are based on carbon nanotube technology. In order to compare the proposed designs with previous ones both MOSFET based and CNFET based circuits are selected. By the way the proposed designs have better performance in comparison with previous designs in terms of speed, power consumption and power-delay product (PDP).
An OFDM System Based on Dual Tree Complex Wavelet Transform (DT-CWT)CSCJournals
This document presents a study comparing an orthogonal frequency division multiplexing (OFDM) system based on dual-tree complex wavelet transform (DT-CWT) to conventional OFDM and wavelet packet modulation (WPM) based OFDM systems. The key findings are:
1) The proposed DT-CWT based OFDM system achieves significantly better bit error rate performance than conventional OFDM and WPM based OFDM systems.
2) The proposed system also achieves about 3 dB better peak-to-average power ratio performance compared to conventional OFDM and WPM based systems, indicating greater signal stability.
3) The performance of the proposed DT-CWT based OFDM system is not
Implementation for Controller to Unified Single Phase Power Flow Using Digita...IJERA Editor
Presenting in his paper, Digital signal processor (DSP)-based implementation of a single phase unified power flow controller (UPFC). For shunt side and series side An efficient UPFC control algorithm is achieved. Discussing the laboratory experimental results using DC source are taken as an UPFC linked by two ll-bridge PWM voltage source converters.
Knowledge Discovery Applied to a Database of Errors of Systems DevelopmentIJERA Editor
This paper presents the knowledge discovery process in a database related to the development of computer systems through the Apriori algorithm. This method of data mining was succesfull in discovering of patterns of relationships between kinds of non-conformities found during the software development and relationships of noncompliance with the kinds of tasks to be performed as an association between two variables "Simple" and "Average" in more than fifty percent of the cases whit tasks labeled as "Improvement". The discovered rules may assist in the decision making by development systems managers in order to reduce non-conformities related to the development of computational systems.
The Cortisol Awakening Response Using Modified Proposed Method of Forecasting...IJERA Editor
A growing body of data suggests that a significantly enhanced salivary cortisol response to waking may indicate
an enduring tendency to abnormal cortisol regulation. More methods have been proposed to deal with
forecasting problems using fuzzy time series. In this paper, our objective was to apply the response test to a
population already known to have long-term hypothalamo–pituitary–adrenocortical (HPA) axis dysregulation.
We hypothesized that the free cortisol response to waking, believed to be genetically influenced, would be
elevated in a significant percent age of cases, regard less of the afternoon Dexamethasone Suppression Test
(DST) value based on fuzzy time series and genetic algorithms. The proposed method adjusts the length of each
interval in the universe of discourse for forecasting the Longitudinal Dexamethasone Suppression Test (DST)
data on a fully remitted lithium responder for past 5 years who was asymptomatic and treated with lithium
throughout the experimental results show that the proposed method gets good forecasting results.
Stability and stabilization of discrete-time systems with time-delay via Lyap...IJERA Editor
The stability and stabilization problems for discrete systems with time-delay are discussed .The stability and
stabilization criterion are expressed in the form of linear matrix inequalities (LMI). An effective method
allowing us transforming a bilinear matrix Inequality (BMI) to a linear matrix Inequality (LMI) is developed.
Based on these conditions, a state feedback controller with gain is designed. An illustrative numerical example
is provided to show the effectiveness of the proposed method and the reliability of the results.
Experimental Plans and Intensive Numerical Aided DesignIJERA Editor
This document discusses a new method for optimizing product design called intensive numerical simulation. It proposes reversing the traditional design process by conducting intensive simulations based on manufacturing knowledge before creating the CAD model. Experimental design plans are used to efficiently run a large number of simulations. The method aims to help small-to-medium enterprises obtain unexpected gains in areas like mass and better use of manufacturing resources. Results show the approach is a promising new way for computer-aided design.
Reduction of Un-safe Work Practices by Enhancing Shop floor Safety– A case studyIJERA Editor
Industrial safety is of utmost important in the present industrial scenario in order to protect employees, plant and
environment. The present study is carried out in a machine tool manufacturing company. The initial study
revealed several problems with respect to industrial safety and productivity. Keeping these problems in view,
the aim of the present study was to analyse the existing layout and designing the new layout to improve the
productivity by ensuring safety in the shop floor according to the standards.The existing problems were
analysed systematically and solved by adopting andimplementing DuPont Safety Model. The implementation
resulted in increasing the safety and productivity in the organization.
Implementation of Full-Bridge Single-Stage Converter with Reduced Auxiliary C...IJERA Editor
The inclusion of a few additional diodes and passive elements in the high-frequency full-bridge ac–dc converter with galvanic isolation permits one to achieve sinusoidal input-current wave shaping and output-voltage regulation simultaneously without adding any auxiliary transistors. Recently, this procedure, together with an appropriate control process, has been used to obtain low-cost high-efficiency single-stage converters. In an attempt to improve the performance of such converters, this paper introduces three new single-stage full-bridge ac–dc topologies with some optimized characteristics and compares them with the ones of the existing full-bridge single-stage topologies. The approach used consists in the definition of the operating principles identifying the boost function for each topology, their operating limits, and the dependence between the two involved conversion processes. Experimental results for each topology were obtained in 500-W modular voltage disturbances that result from the input-current wave-shaping process.
An Overview of Workflow Management on Mobile Agent TechnologyIJERA Editor
This document discusses mobile agent technology for workflow management. It provides an overview of current research on using mobile agents to automate business processes across distributed systems. The document summarizes several related works on topics like inter-organizational workflows, mobile agent communication, coordination techniques, and workflow partitioning and scheduling algorithms. It aims to improve methods for designing and implementing prototype models for mobile agent-based workflow management systems.
Investigation of Tribological Behaviour of GF Filled Peek Composite under the...IJERA Editor
Composite materials have successfully substituted the traditional materials in several light weight and high
strength applications. The reasons why composites are selected for such applications are mainly their high
strength-to-weight ratio, high tensile strength at elevated temperatures, high creep resistance and high
toughness. Therefore minimum Wear of component or part used in machinery is very important factor for the
industry. In this paper the tribological behavior of PEEK (Poly-ether-ether-ketone) composites reinforced by
30% short glass fiber and phosphor bronze were comparatively evaluated on Pin on disc machine. The effect of
three parameters such as temperature, load and sliding distance on Wear loss of PEEK composites reinforced by
30% short glass fiber and phosphor bronze were examined. The detailed mathematical model is simulated by
Minitab 17 and simulation results fit experiment data very well
In this investigation, an effective approach based on Taguchi method, analysis of variance (ANOVA),
multivariable linear regression (MVLR), has been developed to determine the optimum conditions leading to
minimum Wear. Experiments were conducted by varying temperature, load and sliding distance using L9
orthogonal array of Taguchi method. The present work aims at optimizing process parameters to achieve
minimum Wear. Experimental results from the orthogonal array were used as the training data for the MVLR
model to map the relationship between process parameters and Wear. The experiment was conducted on
computerized Pin on Disc machine. It was observed that PEEK 30% Glass Fiber Composite Polymer has
excellent wear resistance compare to Phosphor bronze at elevated temperature.
On Steiner Dominating Sets and Steiner Domination Polynomials of PathsIJERA Editor
This document introduces the concept of the Steiner domination polynomial of a path Pn. It defines the Steiner domination polynomial Sγ(Pn, x) as the sum of the number of Steiner dominating sets of size i for each i, where the number of such sets is represented by sγ(Pn, i). Several lemmas are provided about properties of Sγ(Pn, x) and its coefficients, including that it has no constant term, is strictly increasing, and properties related to the polynomials of smaller paths Pn-1, Pn-2, and Pn-3. The proofs of these lemmas are also given.
Performance Analysis of Cognitive Radio for Wi-Fi Signals Using Cyclostationa...IJERA Editor
The need for radio spectrum usage is increasing day by day with recent advancements in wireless system. But there is limited amount of spectrum available. So that for solving this problem Cognitive Radio (CR) is used for purpose of the spectrum utilization properly. Basically the Licensed users use the licensed bands but the unlicensed users should always check spectrum with the help of CR technology. The main aim of cognitive radio is to sense the spectrum continuously. In this paper, we have provided the proposal that how the capacity of the system can be increased by reuse the unused licensed band by simulating a Cognitive radio system. The secondary users can occupy free space (spectrum holes) and also licensed bands by continuously monitoring the spectrum. The requirements of cognitive radio systems will be investigated by considering spectrum sensing techniques. To achieve this, a Cyclostationary Spectrum Sensing technique is studied and applied to detect OFDM signals in a noisy environment. The results are obtained for the applications employed in high frequency, such as, Wi-Fi.
This document describes the modeling and design of a five-level cascaded H-bridge multilevel inverter with a DC/DC boost converter. It begins with an introduction to multilevel inverters and their advantages over traditional two-level inverters. It then discusses the specific topology of a five-level cascaded H-bridge inverter and describes the operation and components of a DC/DC boost converter. Simulation results in MATLAB/Simulink are presented, showing the output voltage waveform both with and without filtering. The total harmonic distortion of the output is analyzed, showing less than 5% distortion. The conclusion is that this five-level inverter topology with boost converter provides high efficiency of 95% and improved power
1. The document introduces concepts of equitable domination in fuzzy graphs. It defines fuzzy dominating sets and fuzzy domination numbers.
2. An equitable dominating set in a fuzzy graph is defined such that the degree of any dominating vertex is never more than 1 greater than the degree of the dominated vertex. The minimum cardinality of an equitable dominating set is the equitable domination number.
3. Properties of equitable domination in fuzzy graphs are explored, including results showing the domination number and equitable domination number are equal for regular and bi-regular fuzzy graphs. The concept of equitable isolates is also introduced.
The microscopic effect of the exchange interaction parameter for the 2-Dimensional ising model with nearest neighbor interaction has been studied. By supposing simple temperature dependent relationship for the exchange parameter, graphs were straightforwardly obtained that show the reentrant closed looped phase diagrams symptomatic of some colloids and complex fluids and some binary liquids mixtures in particular. By parameter modifications, other phase diagrams were also obtained. Amongst which are the u-shapes and other exotic shapes of phase diagrams. Our results show that the exchange interaction parameter greatly influence the size of the ordered phase. Hence the larger the value of the constant, the larger the size of the ordered phase. This means that the higher values of the exchange parameter brings about phase transitions that straddle a wider range of polarizations and temperatures.
A Stochastic Model for the Progression of Chronic Kidney DiseaseIJERA Editor
Multistate Markov models are well-established methods for estimating rates of transition between stages of
chronic diseases. The objective of this study is to propose a stochastic model that describes the progression
process of chronic kidney disease; CKD, estimate the mean time spent in each stage of disease stages that
precedes developing end-stage renal failure and to estimate the life expectancy of a CKD patient. Continuoustime
Markov Chain is appropriate to model CKD. Explicit expressions of transition probability functions are
derived by solving system of forward Kolmogorov differential equations. Besides, the mean sojourn time, the
state probability distribution, life expectancy of a CKD patient and expected number of patients in each state of
the system are presented in the study. A numerical example is provided. Finally, concluding remarks and
discussion are presented.
This document discusses analyzing and evaluating suitable sites for a textile wastewater treatment plant in Salem, India using remote sensing and GIS techniques. The study area experiences high population growth and economic development putting pressure on water resources. Textile industries in the area discharge wastewater containing dyes and chemicals. The document examines using GIS to select the best location for a treatment plant by evaluating factors like ground slope, land use, and proximity to rivers and roads to minimize environmental degradation. Spatial analysis tools in ArcGIS were used to classify suitable sites as good, moderate, or poorly suitable.
Efficient video compression using EZWTIJERA Editor
In this article, wavelet based lossy video compression algorithm is presented. The motion estimation and compensation, being an important part in the compression, is based on segment movements. The proposed work is based on wavelet transform algorithm Embedded Zeroed WaveletTransform (EZWT). Based on the results of peak signal to noise ratio (PSNR), mean squared error (MSE), different videos are analyzed. Maintaining the PSNR to acceptable limits the proposed EZWT algorithm achieves very good compression ratios making the technique more efficient than the 2-Discrete Cosine Transform (DCT) in the H.264/AVC codec. The method is being suitable for low bit rate video showing highest compression ratio and very good PSNR of more than 30dB.
Micro CT settings for caries detection: how to optimizeIJERA Editor
Some important items that can influence micro CT image were reviewed in this study. Different settings were
optimized for the assessment of early caries lesions. There are several researches on bone using micro CT but not
too much on dental hard tissues when assessing mineral loss. Different kinds of micro CT devices and
technologies are taking place today, each requiring unique settings, and this consists one of the greatest obstacles
for the use of micro CT on dental hard tissues. Achieving the settings for an ideal dental image is therefore a
challenge. The purpose of this study was to evaluate different micro CT settings to optimize the assessment of
early caries lesions aiming the integrity of the dental specimen thus, making possible to reuse it for further
studies. Three teeth with early caries lesions were submitted to different micro CT settings and different
reconstruction settings, aiming a better image. The final image was compared visually through different densities
and attenuation coefficients. The best setting for teeth tissues was achieved regarding contrast, definition, noise
reduction and the larger difference between sound enamel and early lesions attenuation coefficient.
Size and Time Estimation in Goal Graph Using Use Case Points (UCP): A SurveyIJERA Editor
In order to achieve ideal status and meet demands of stakeholders, each organization should follow their vision and long term plan. Goals and strategies are two fundamental basis in vision and mission. Goals identify framework of organization where processes, rules and resources are designed. Goals are modelled based on a graph structure by means of extraction, classification and determining requirements and their relations and in form of graph. Goal graph shows goals which should be satisfied in order to guarantee right route of organization. On the other hand, these goals can be called as predefined sub projects which business management unit should consider and analyse them. If we know approximate size and time of each part, we will design better management plans resulting in more prosperity and less fail. This paper studies how use case points method is used in calculating size and time in goal graph.
Duration for Classification and Regression Treefor Marathi Textto- Speech Syn...IJERA Editor
This research paper reports preliminary results of data-driven modeling of segmentalphoneme duration for
Marathi. Classification and Regression Tree based data driven duration modeling for segmental duration
prediction is presented. A number of features are considered and their usefulness and relative contribution for
segmental duration prediction is assessed. Objective evaluation of the duration model, by root mean squared
prediction error and correlation between actual and predicted durations, is performed.
HIGH SPEED MULTIPLE VALUED LOGIC FULL ADDER USING CARBON NANO TUBE FIELD EFFE...VLSICS Design
High speed Full-Adder (FA) module is a critical element in designing high performance arithmetic circuits. In this paper, we propose a new high speed multiple-valued logic FA module. The proposed FA is constructed by 14 transistors and 3 capacitors, using carbon nano-tube field effect transistor (CNFET) technology. Furthermore, our proposed technique has been examined in different voltages (i.e., 0.65v and 0.9v). The observed results reveal power consumption and power delay product (PDP) improvements compared to existing FA counterparts.
A Novel Flipflop Topology for High Speed and Area Efficient Logic Structure D...IOSR Journals
Abstract: In high speed data path network flop is one of the major functional elements to store intermediate results and data at different stages. But the most important problem is huge power utilization due to switching activity and increase in clock period that is Timing Latency; causes the performance of data path in digital design is decreased. The existing works implement various Flipflop topology in data path structure design such as conventional Transmission Gate Based Master Slave Filpflop (TGMS FF), Write Port Master Slave Flip-flop (WPMS) and Clocked Complementary Metal Oxide Semiconductor (C2MOS). In WPMS method, area is minimized but delay is increased. In C2MOS technique Power consumption and delay is reduced, but there is a definite scope to reduce Power, area and delay. In this paper a Modified Clocked Complementary Metal Oxide Semiconductor Latch (mC2MOS Latch) is proposed and delay, power is again reduced up to 60% and the area of the circuit is also reduced while comparing with previous methods. Index Terms: Circuit enhancement, flip-flops (FFs), high-speed, logical effort, master–slave, transmission-gate.
Comparators are basic building elements for designing modern analog and mixed signal systems. Speed and resolution are two important factors which are required for high speed applications. This paper presents a design for an on chip high-speed dynamic latched comparator for high frequency signal digitization. The dynamic latched comparator consists of two cross coupled inverters comprising a total of 9 MOS transistors. The measured and simulation results show that the dynamic latched comparator design has higher speed, low power dissipation and occupying less active area compared to double tail latched and preamplifier based clocked comparators. A new fully dynamic latched comparator which shows lower offset voltage and higher load drivability than the conventional dynamic latched comparators has been designed. With two additional inverters inserted between the input-stage and output-stage of the conventional double-tail dynamic comparator, the gain preceding the regenerative latch stage was improved and the complementary version of the output-latch stage, which has bigger output drive current capability at the same area, was implemented.
Review of Integrated Power Factor Correction (PFC) Boost converter topologies...IJARBEST JOURNAL
This paper provides a review of various Power Factor Correction (PFC) boost
converter topologies suitable for telecoms. A novel integrated PFC topology is proposed which acts
as a backup power supply for telecommunication systems. The advantage of the proposed circuit is
that it operates based on soft switching principle thereby reducing the switching losses in the
converter. The topologies analyzed in this paper are conventional average current mode control
boost PFC, bridgeless boost PFC, semi-bridgeless boost PFC, totem-pole bridgeless boost PFC and
proposed integrated boost PFC. All these topology studies are investigated by carrying out the
simulation of the converter circuits using PSIM software. A detailed comparison of all the
topologies have been done and they are compared in terms of supply power factor, supply current
THD and displacement factor. From the results, it is inferred that the proposed integrated PFC
provides a reduced supply current THD and improved power factor. The results are validated.
Analysis of pocket double gate tunnel fet for low stand by power logic circuitsVLSICS Design
This document analyzes and compares the pocket double gate tunnel FET (DGTFET) and MOSFET for use in low standby power logic circuits. Simulation results show that the pocket DGTFET has lower leakage current than the MOSFET. A pocket DGTFET inverter is designed in 32nm technology with a supply voltage of 0.6V. The pocket DGTFET inverter has significantly lower leakage power of 0.116pW compared to 1.83pW for a multi-threshold CMOS inverter. Therefore, the pocket DGTFET is well-suited to replace the MOSFET for low standby power applications.
Performance Comparison of CMOS and Finfet Based Circuits At 45nm Technology U...IJERA Editor
According to the Moore’s Law, the number of transistors in a unit chip area double every two years. But the existing technology of integrated circuit formation is posing limitations to this law. CMOS technology shows certain limitations as the device is reduced more and more in the nanometer regime out of which power dissipation is an important issue. FinFET is evolving to be a promising technology in this regard. This paper aims to analyze and compare the characteristics of CMOS and FinFET circuits at 45nm technology. Inverter circuit is implemented in order to study the basic characteristics such as voltage transfer characteristics, leakage current and power dissipation. Further the efficiency of FinFET to reduce power as compared to CMOS is proved using SRAM circuit. The results show that the average power is reduced by 92.93% in read operation and by 97.8% in write operation.
A Low Power High Bandwidth Four Quadrant Analog Multiplier in 32 NM CNFET Tec...VLSICS Design
Carbon Nanotube Field Effect Transistor (CNFET) is a promising new technology that overcomes several limitations of traditional silicon integrated circuit technology. In recent years, the potential of CNFET for analog circuit applications has been explored. This paper proposes a novel four quadrant analog multiplier design using CNFETs. The simulation based on 32nm CNFET technology shows that the proposed multiplier has very low harmonic distortion (<0.45%), large input range (±400mV), large bandwidth (~50GHz) and low power consumption (~247µW), while operating at a supply voltage of ±0.9V.
Review on Tunnel Field Effect Transistors (TFET)IRJET Journal
The document discusses Tunnel Field Effect Transistors (TFETs) as a promising alternative to MOSFETs for low power applications. TFETs use band-to-band tunneling as the switching mechanism instead of thermionic emission like in MOSFETs, allowing TFETs to achieve subthreshold slopes lower than 60 mV/decade. The document reviews different TFET structures that have been proposed over time, including heterojunction TFETs that use different materials for the source and channel to facilitate band-to-band tunneling. TFETs are seen as important for continued device scaling as they can help reduce static and dynamic power consumption compared to conventional MOSFETs.
A Single-Phase Clock Multiband Low-Power Flexible Dividerijsrd.com
In this paper, a low-power single-phase clock multiband flexible divider for Bluetooth, Zigbee, and IEEE 802.15.4 and 802.11 a/b/g WLAN frequency synthesizers The frequency synthesizer was implemented using a charge-pump based phase-locked loop with a tri-state phase/frequency detector and a programmable pulse-swallow frequency divider. Since the required frequency of operation can be as high as 1.4GHz, the speed of the digital logic used in the frequency divider is a critical design factor. A custom library of digital logic gates was designed using MOS current-mode logic (MCML). These gates were designed to operate at frequencies up to 1.4GHz. This report outlines the design of the phase/frequency detector and the programmable pulse-swallow frequency divider. The design, layout, and simulation of the MCML logic family are also presented.
This document discusses the design and analysis of a carbon nanotube field effect transistor (CNTFET) based D flip-flop (DFF). The proposed DFF uses a single clock phase and includes a reset function. Simulation results show it consumes significantly less power and has lower delay than a comparable 32nm CMOS DFF. Circuits like a gray counter and linear feedback shift register built using the CNTFET DFF achieve over 96% improvement in power delay product compared to CMOS designs. The document evaluates the performance of the proposed CNTFET DFF and compares it to a CMOS DFF in terms of propagation delay, power consumption, and other metrics. It demonstrates that CNTFET technology has potential
This document discusses the design and analysis of a D flip-flop (DFF) based on carbon nanotube field-effect transistors (CNTFETs). It presents a negative edge triggered DFF designed using pass transistor logic with single clock phase and reset function. Simulation results show the CNTFET DFF consumes significantly lower power and has less delay compared to a 32nm CMOS DFF. Application examples of the CNTFET DFF in a gray counter and linear feedback shift register also achieve over 90% improvement in power-delay product compared to CMOS designs. The document evaluates the performance of the CNTFET DFF and applications, demonstrating its advantages over CMOS technologies for low power, high performance applications
Design and Analysis of Power and Variability Aware Digital Summing CircuitIDES Editor
This document analyzes and compares different 1-bit digital summing circuit topologies in terms of their robustness against process, voltage, and temperature variations at the 22nm technology node. It finds that the transmission gate-based topology is the most robust, with the tightest spread in propagation delay, power dissipation, and energy-delay product. It then proposes a transmission gate-based digital summing circuit implemented using carbon nanotube field-effect transistors, which offers even greater robustness against PVT variations compared to an implementation using traditional MOSFETs.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Performance Analysis of Interconnect Drivers for Ultralow Power ApplicationsIDES Editor
ultralow power consumption requirement of low
throughput applications needs to operate circuits in
subthreshold region where subthreshold leakage current is used
as active current for necessary computations. This paper
investigates the impact of interconnect drivers on digital circuit
performance in subthreshold region. In particular, we have
investigates the performance of Si-MOSFET and CNFETs at
32nm deep submicron technology node. Performance Analysis
is carried out for different interconnect drivers driving global
interconnect. We have proposed an optimized CNFET driver
which gives the significant improvement in delay and PDP over
conventional CNFET in subthreshold for global and semi-global
interconnect length. HSPICE device model files generated from
“Nano CMOS” tool are use for Si-MOSFET to analyze the
impact of Process and Temperature (P, T) variations on
robustness of circuit for fair comparison with CNFET.
Variability of design metric parameters is evaluated by applying
Gaussian distribution using Monte Carlo simulation run.
Analysis and Design of A Low-Voltage Low-Power Double-Tail Comparator. This is a final semester Mtech project on VLSI design implementation of dual tail comparator in a modifyied version. This design is implemented using VHDL Language with 100% Source code synthesizable available. Software for free to download and knowledge transfer for the same project is also being implemented..The design is implemented using FSM technology, low power is achieved in this project.area utilization is the major advantage in this project.Low power techniques such as Clock gating, power gating is implemented in this project.,ieee reference paper is used for the base.
Analysis and design_of_a_low-voltage_low-power[1]Srinivas Naidu
The document presents an analysis of the delay characteristics of dynamic comparators. It analyzes the delay of conventional dynamic and double-tail comparators, deriving analytical expressions showing the impact of various design parameters on delay. A new dynamic comparator is then proposed based on modifying the circuit of a conventional double-tail comparator to strengthen positive feedback, reducing delay time. Simulation results on the proposed comparator show significantly reduced power consumption and delay compared to conventional designs, enabling higher clock frequencies at lower supply voltages.
Conducted EMI Reduction Accomplished via IEEE 1588 PTP for Grid Connected Par...idescitation
This paper introduces a distributed approach for
interleaving paralleled power converter to reduce EMI and
voltage ripple, accomplished via IEEE 1588 Precision time
protocol. An open source software stack of IEEE 1588v2 named
PTPd-2.2.0 is used to implement software stack over stellaris
series microcontroller from Texas Instruments (TI). A general
methodology for achieving distributed interleaving is proposed,
along with a specific software based implementation approach
using the PTPdv2. The effectiveness of such methods in terms
of EMI reduction is experimentally validated in grid connected
Paralleled Solar Power Inverters.
The document discusses using IEEE 1588 Precision Time Protocol (PTP) to achieve distributed interleaving of paralleled solar power inverters. PTP allows networked devices to synchronize clocks with microsecond accuracy over Ethernet networks. The paper proposes using PTP to introduce phase shifts between inverter switching signals, which reduces electromagnetic interference and voltage ripple. Experimental results validated the EMI reduction achieved through this software-based distributed interleaving approach using PTP.
LEAKAGE POWER REDUCTION AND ANALYSIS OF CMOS SEQUENTIAL CIRCUITSVLSICS Design
A significant portion of the total power consumption in high performance digital circuits in deep submicron regime is mainly due to leakage power. Leakage is the only source of power consumption in an idle circuit. Therefore it is important to reduce leakage power in portable systems. In this paper two techniques such as transistor stacking and self-adjustable voltage level circuit for reducing leakage power in sequential circuits are proposed. This work analyses the power and delay of three different types of D flip-flops using pass transistors, transmission gates and gate diffusion input gates. . All the circuits are simulated with and without the application of leakage reduction techniques. Simulation results show that the proposed pass transistor based D flip-flop using self-adjustable voltage level circuit has the least leakage power dissipation of 9.13nW with a delay of 77 nS. The circuits are simulated with MOSFET models of level 54 using HSPICE in 90 nm process technology.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
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Design and Analysis of New Modified Feedthrough Logic (MFTL) Circuits Using Carbon Nanotube Field Effect Transistor (CNTFET)
1. Sneha Meryn Thomas Int. Journal of Engineering Research and Applications www.ijera.com
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Design and Analysis of New Modified Feedthrough Logic (MFTL) Circuits Using Carbon Nanotube Field Effect Transistor (CNTFET) Sneha Meryn Thomas1, Rakesh S2 1(Department of Electronics and Communication Engineering, Mangalam College of Engineering, MG University, Ettumanoor, Kerala-686631) 2 (Asst. Prof, Department of Electronics and Communication Engineering, Mangalam College of Engineering, MG University, Ettumanoor, Kerala-686631) ABSTRACT It is a challenging task for a VLSI design engineer to develop low power VLSI circuits, without sacrificing its performance. Feedthrough Logic (FTL) is a new technology which could be considered better than the existing technologies for improving circuit efficiency. Modified Feedthrough Logic (MFTL), offers a better power factor than the FTL logic structures, and also shows an improvement in the speed factor. But the scenario again changes when the design extends to nano scales of device dimension, where many factors which were neglected otherwise need to be given more importance. To avoid or minimize problems like hot carrier effects, electro migration, drain induced barrier lowering and other issues that becomes prominent in nano scale MOSFET‟s, Carbon Nanotube Field Effect Transistor (CNTFET) is considered to be a promising candidate in future integrated circuits. Hence this work extends the advantages of MFTL logic into nano level by incorporating CNTFETs in place of MOSFETs. The modifications have been implemented using CNTFETs of 16nm technology from HSPICE library on a 10 chain inverter stage, an 8 bit RCA and a Vedic multiplier and performance factors like PDP and ADP are compared to that of the conventional MOSFET circuits.
Keywords – CNT, Domino logic, FTL, MFTL
I. Introduction
When considering the circuit design styles put forward in the last couple of decades, it can be seen that power is the factor that gets compromised for attaining the overall circuit efficiency. Some of the different common methods employed include the use of multi threshold voltages for different circuit portions, using dual supply voltages as needed [8,9,10,11] etc. But in all such cases, it is seen that power factor gets traded for attaining efficiency.
However the development of FTL proved to bring a better change, as it provides improved power and speed factors compared to the existing circuit styles. It provides high performance operation for delay critical circuit like arithmetic or pipelining circuit [2,3]. Domino logic that is employed primarily to overcome the cascading issues of dynamic logic blocks, hold to be the basic principle of FTL logic. In addition, the main feature of FTL is its ability to evaluate the final output before all the inputs have a valid value or voltage level. This can be considered as the factor that improves the speed of the circuit. This pre-evaluation is possible because of the presence of the clock, which acts as the control signal. Also, with respect to the short comings of domino logic like inability to provide non inverting logic, problem of charge sharing, monotonic nature of output and requirement of additional inverter at output [2, 3,12,13], FTL can be used to overcome them gracefully. Again, from the previous works carried out [1]., Modified FTL (MFTL) circuit families provide better PDP as compared to the existing FTL. For MFTL, the working principle is the same as for existing FTL and the difference comes structurally as explained in Section II. Hence MFTL also has the advantages of FTL style.
As scaling down of dimensions have become a necessity and reality in the modern scenario of circuit designs, new challenges are put forward to the designer including dealing with issues like electro migration as in the case of interconnects and hot carrier effects, drain induced barrier lowering and so on in case of MOSFET‟s. Hence better options and architecture for new interconnects and alternative for MOSFETs must be generated. Carbon Nanotube Field Effect Transistor (CNTFET) is a promising candidate for future integrated circuits because of its excellent properties like near ballistic transport [4], high carrier mobility and easy integration of high-k dielectric material [4, 5, 6, 7], Hence this work extends the advantages of MFTL logic into nano level by incorporating CNTFETs in place of MOSFETs. The modifications have been implemented using CNTFETs of 16nm technology
RESEARCH ARTICLE OPEN ACCESS
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from HSPICE library on a 10 chain inverter stage, an 8 bit RCA and a Vedic multiplier and performance factors like PDP and ADP are compared to that of the conventional MOSFET circuits [14]. Section 2 explains the working principle of the MFTL circuits. Section 3 describes the principle of operation of LP-MFTL circuits. Section 4 gives a detailed analysis explanation of the MFTL and LP- MFTL logic styles when implemented using CNTFETs, through extensive simulation on HSPICE platform. Section 5 gives a glossary of the advantages, disadvantages and applications of MFTL logic.
II. PRINCIPLE OF MFTL OPERATION
Consider the block diagram of MFTL structure, as extended from existing FTL structure [Fig 1]. Fig 1 MFTL structure For FTL, the pull down network is connected directly to ground, whereas in MFTL the pull down network is connected to ground through additional NMOS transistor Ta. The gate of NMOS is driven by VDD as gate source voltage. Similar to FTL, following the domino logic, MFTL also uses a clock as the control signal.
The principle of operation of MFTL is as follows: There are two phases of operation depending upon the value of the clock namely. Precharge phase (CLK=0) and Evaluation phase (CLK=1). During Evaluation phase (clock goes „HIGH‟), output is pulled to „LOW‟ through reset transistor Tr and during Precharge phase (clock goes „LOW‟), the output is generated conditionally according to the given set of inputs with additional transistor Ta which is always „ON‟. The purpose of the additional transistor Ta is to increase the dynamic resistance of the pull down network, which in turn causes the output node to discharge to a VOL value that is greater than that of the existing FTL. This trade-off in VOL results for less high-to-low propagation delay from VTH to VOL, thus reducing the overall delay. Also, increased value of VOL reduces power consumption, as the dynamic power dissipation of a digital circuit is given by
P dynamic = α.CL.VDD .V(x).Fclk (1) Here, α is the switching factor, CL is the load capacitance, VDD is supply voltage, Fclk is the maximum operating frequency and V(x) is the power delivered by the source during low to high transition. Increased value of VOL reduces V(x) in MFTL. Therefore, modified FTL has lower dynamic power consumption than in existing FTL
III. PRINCIPLE OF LP-MFTL OPERATION
For LP-MFTL structure also, the connection to the ground from the NMOS block (pull down network) in existing LP-FTL structure is replaced with additional NMOS transistor Ta which is then connected to ground. Consider the block diagram of LP-MFTL structure [Fig 2], as extended from existing LP-FTL structure. Fig 2 LP-MFTL structure
Power reduction in LP-FTL logic is obtained with the additional PMOS transistor TP2 that comes in series with TP1 that actually reduces VOL. The operation of this circuit is also controlled by the clock signal. When the clock signal, „CLK‟ is HIGH (evaluation phase) output node is pulled to ground (LOW) through Tr and when CLK goes LOW (precharge phase) output node charges (HIGH) through TP1 and TP2. During this phase, the reset transistor, Tr is turned off and the output node conditionally evaluates to logic high (VOH) or low (VOL) depending upon input to NMOS block. If the NMOS block is turned off, then there exists a high resistance path from the output node to ground and hence, output node gets pulled toward VDD i.e. VOH =VDD, otherwise it remain at logic low i.e. VOL. However for the output to discharge to a complete LOW value, it requires the occurrence of a subsequent evaluation phase. As the two PMOS
Existing LP-FTL grounded by Ta
LP-MFTL Structure
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transistors, TP1 and TP2 are in series the voltage at drain of TP1 is lower than VDD causing a significant reduction in dynamic power consumption compared to existing FTL but due to the insertion of PMOS transistor TP2 propagation delay of the existing LP- FTL in Fig. 2, increases. Despite the above sited advantages of FTL and MFTL logic, it suffers from a non-zero logic low condition. Low power proposed modified FTL (LP-MFTL), has an NMOS transistor Ta connected as shown in Fig. 2. When clock goes „HIGH‟, output is pulled to „LOW‟ through reset transistor Tr. When clock goes „LOW‟; the output is generated according to the given set of inputs with additional transistor Ta always „ON‟. For LP-MFTL, due to the insertion of PMOS transistor TP2 propagation delay increases.
IV. PERFORMANCE ANALYSIS OF NEW LOWER POWER MFTL STRUCTURE USING CNTFET
4.1 Results for Inverter
Fig 3 shows the timing diagram for a 10 chain MFTL inverter using CNTFETs, where the first slot represents the clock signal „clk‟, the second slot represents the input „in‟ and the third slot the output „out10‟. When „clk‟ = 0 and „in‟ =0, the output „out10‟ represents LOW (approximately = 700mV, showing a greater VOL value). Fig.3 Timing diagram for 10 chain MFTL inverter. TABLE I PDP comparison for FTL, MFTL in CNTFET (10 Chain Inverter)
Type
Power (uW)
Delay (ps)
PDP(uW x ps) x 10^- 14
FTL
32.3
486.7
1.57
MFTL
19.06
271.8
0.518
From Table I for 10 inverter chain using FTL and MFTL logic using CNTFETs, it can be viewed that for the proposed modified MFTL structure, there is a significant reduction in power consumption, as well as a noticeable increase in the speedup factor. In other words, from the analysis, a 39% decrease in power and an improvement by 42% for speed factor could be observed. As a result MFTL circuit using CNTFETs in nano scale of dimension holds a better PDP compared to the existing FTL structure. TABLE II. ADP comparison for FTL, MFTL (10 chain inverter)
Type
No; of transistors
Delay (ps)
ADP(nm2 x ps) x 10^- 25
FTL
30
486.7
9.3
MFTL
40
271.8
6.9
In contrary to the ADP comparison for inverter chain using MOSFETs [1], while comparing the ADP of FTL and MFTL circuits using CNTFETs in nano scale, one can notice that the requirement of additional number of transistors gets compensated by the improved speedup factor in the nano regime, thus MFTL 10 chain inverter circuit showing a better ADP.
4.2 Results for 8 bit RCA
For obtaining a justifiable output, for all the circuit structures, same set of input is used which goes like Ai =0.8 V for 5 ns, Bi =0.8V for 5ns (where I = 1 to 8) and C1 =0. Then the output file obtained for different FTL RCA structures using CNTFETs are shown below. Fig.4 Output file for 8 bit FTL RCA Fig.5 Output file for 8 bit MFTL RCA
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Fig.6 Output file for 8 bit LP- MFTL RCA
TABLE III. PDP comparison for 8 bit RCA using
CNTFET
Type Power
(uW)
Delay
(ps)
PDP(uW
x ps) x
10^- 15
FTL 24 91.88 2.2
MFTL 15.03 52.18 0.784
LP -
MFTL
7.87 87.00 0.68
From Table III for 8 bit RCA using FTL, MFTL
logic and LP-MFTL logic using CNTFETs, it can be
viewed that for the proposed modified MFTL
structure, there is a significant reduction in power
consumption, as well as a noticeable increase in the
speedup factor. As a result MFTL circuit using
CNTFETs in nano scale of dimension holds a better
PDP compared to the existing FTL structure. At the
same time the modification when applied to the
existing LP-FTL structure, yields a further reduction
in power, hence a better PDP than the FTL and
MFTL structures is obtained.
4.3 Results for Vedic Multiplier
“Urdhva iryagbhyam” sutra is the algorithm on
which the Vedic Multiplier works. From earlier times
onwards, these algorithms are being used, mainly for
the multiplication of two numbers in the decimal
number system. However, this sutra may be applied
to all cases of multiplication. The literal meaning of
this algorithm is “Vertically” and “Crosswise”. It is
based on a new concept in which the concurrent
addition of the partial products. generates all partial
products.
The 2X2 Vedic multiplier module is
implemented using four input AND gates & two half-adders
which is displayed in its block diagram in Fig
7
Fig 7 Block diagram of 2 x 2 bit Vedic Multiplier
Fig 8 shows the timing diagram for a 2 x 2
MFTL Vedic Multiplier, obtained from DSCH which
is a Schematic tool, where the result can be obtained
directly by drawing the required circuit diagram. This
tool helps to verify the correctness of the design as
the circuit can be directly simulated and the working
can be viewed through checking output LEDs turning
ON and OFF according to inputs, whereas in
HSPICE where the designer can depend only on the
output graphs and output files obtained.
Fig 8 Timing diagram of 2 bit Vedic Multiplier in
MFTL (DSCH).
Fig 9 represents the timing diagram obtained for
2 bit Vedic Multiplier in FTL from HSPICE. It
considers the inputs as (a0 ,a1, b0, b1) HIGH for a
period of 2ns.Here, first slot represents the input
clock signal „clk‟, the second slot represents the four
inputs „a0,a1,b0,b1‟ and the third slot represents the
four outputs „S0, S1.S2,C2‟
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Fig 9 Timing diagram of 2 bit Vedic Multiplier in FTL Fig 10 shows the output file obtained from HSPICE for Vedic multiplier in FTL for the inputs as (a0 ,a1, b0, b1) HIGH for a period of 2ns. Similarly Fig 11 and Fig 12 show the output files for 2 bit Vedic Multiplier using MFTL and LP-MFTL structures. Fig.10 Output file for 2 bit FTL Vedic Multiplier using CNTFET Fig.11 Output file for 2 bit MFTL Vedic Multiplier using CNTFET Fig.12 Output file for 2 bit LP-MFTL Vedic Multiplier using CNTFET Table IV shows the PDP comparison for Vedic multiplier using CNTFET in FTL, MFTL and LP- MFTL structures.
TABLE IV PDP comparison for Vedic Multiplier using CNTFET
Type
Power (uW)
Delay (ps)
PDP(uW x ps) x 10^- 15
FTL
23.37
68.78
1.6
MFTL
21.62
66.76
1.45
LP MFTL
20.71
68.75
1.4
From Table IV, PDP comparison for the three structures namely FTL, the proposed MFTL and the proposed LP MFTL is obtained. Here also better PDP values are obtained for the proposed structures.
V. CONCLUSION
The advantages of MFTL logic includes those as for FTL as already cited in Section 1. In addition, MFTL provides faster circuits with lower power dissipation. Also, the circuit for low power improves dynamic power consumption as compared to the existing Feedthrough Logic circuits .The result comparison of Table III points to the advantage obtained in power and delay when the FTL, MFTL and LP-MFTL 8 bit RCA structures are extended to the nano regime. A clear difference in performance can be obtained by analyzing the Power Delay Product of each structure. For both cases as from Table III and Table IV, better PDP is obtained for the LP-FTL structure. From this analysis we can conclude that the advantages of using the proposed MFTL logic could be effectively extended to nano scale of dimensions employing CNTFETs. Despite these performance advantages, MFTL circuit suffers from certain disadvantages like reduction in noise margin, direct path current and a non-zero low output voltage which occurs due to contention between PMOS and NMOS in the evaluation block. And the inclusion of additional NMOS transistor is needed making the circuits more area greedy while using MOSFETs. However, due to better power and delay factors, MFTL based circuits can be employed in high fanout and high switching frequency circuits. Also, MFTL logic can be used in cascaded stages, differential style, as well as multiple output logic with iterative networks. MFTL logic can also be used effectively in nano scale dimensions using CNTFETs.
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