This document summarizes a research paper that proposes a novel 7-transistor SRAM cell design using carbon nanotube field-effect transistors (CNTFETs) at the 32nm technology node. The proposed 7T SRAM cell aims to reduce dynamic write power consumption and improve read cycle times compared to a conventional 6T SRAM cell. It adds an additional transistor to cut off feedback during writes, allowing writes to depend on only one bitline instead of two. HSPICE simulations using a CNTFET model show the 7T cell achieves 37.2% lower write power and 38.6% faster reads than a baseline 6T cell.
DESIGN AND MODELLING OF DIFFERENT SRAM’S BASED ON CNTFET 32NM TECHNOLOGYVLSICS Design
Carbon nanotube field-effect transistor (CNTFET) refers to a field-effect transistor that utilizes a single carbon nanotube or an array of carbon nanotubes as the channel material instead of bulk silicon in the traditional MOSFET structure. Since it was first demonstrated in 1998, there have been tremendous developments in CNTFETs, which promise for an alternative material to replace silicon in future electronics. Carbon nanotubes are promising materials for the nano-scale electron devices such as nanotube FETs for ultra-high density integrated circuits and quantum-effect devices for novel intelligent circuits, which are expected to bring a breakthrough in the present silicon technology. A Static Random Access Memory (SRAM) is designed to plug two needs: i) The SRAM provides as cache memory, communicating between central processing unit and Dynamic Random Access Memory (DRAM). ii) The SRAM technology act as driving force for low power application since SRAM is portable compared to DRAM, and SRAM doesn’t require any refresh current. On the basis of acquired knowledge, we present
different SRAM's designed for the conventional CNTFET. HSPICE simulations of this circuit using Stanford CNTFET model shows a great improvement in power saving.
IOSR Journal of Electronics and Communication Engineering(IOSR-JECE) is an open access international journal that provides rapid publication (within a month) of articles in all areas of electronics and communication engineering and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications in electronics and communication engineering. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
Crdom cell re ordering based domino on-the-fly mappingVLSICS Design
This Domino logic is often the choice for designing high speed CMOS circuits. Often VLSI designers
choose library based approaches to perform technology mapping of large scale circuits involving static
CMOS logic style. Cells designed using Domino logic style have the flexibility to accommodate wide range
of functions in them. Hence, there is a scope to adopt a library free synthesis approach for circuits
designed using Domino logic. In this work, we present an approach for mapping a domino logic circuit
using an On-the-fly technique. First, we present a node mapping algorithm which maps a given Domino
logic netlist using On-the-fly technique. Next, using an Equivalence Table, we re-order the cells along the
critical path for delay, area benefit. Finally, we find an optimum re-ordering set which can obtain
maximum delay savings for a minimum area penalty. We have tested the efficacy of our approach with a
set of standard benchmark circuits. Our proposed mapping approach (CRDOM) obtained 21%
improvement in area and 17% improvement in delay compared to existing work.
Research Inventy : International Journal of Engineering and Scienceresearchinventy
Research Inventy : International Journal of Engineering and Science is published by the group of young academic and industrial researchers with 12 Issues per year. It is an online as well as print version open access journal that provides rapid publication (monthly) of articles in all areas of the subject such as: civil, mechanical, chemical, electronic and computer engineering as well as production and information technology. The Journal welcomes the submission of manuscripts that meet the general criteria of significance and scientific excellence. Papers will be published by rapid process within 20 days after acceptance and peer review process takes only 7 days. All articles published in Research Inventy will be peer-reviewed.
SINGLE-PORT FIVE-TRANSISTOR SRAM CELL WITH REDUCED LEAKAGE CURRENT IN STANDBYVLSICS Design
In this paper, a new single-port five-transistor (5T) Static Random Access Memory (SRAM) cell with
integrated read/write assist is proposed. Amongst the assist circuitry, a voltage control circuit is coupled to
the sources corresponding to driver transistors of each row memory cells. This configuration is aimed to
control the source voltages of driver transistors under different operating modes. Specifically, during a
write operation, by means of sizing the driver transistor close to bitline to resolve the write ‘1’ issue. In
addition, associated with a two-stage reading mechanism to increase the reading speed and to avoid
unnecessary power consumption. Finally, with the standby start-up cir
RIVERBED-BASED NETWORK MODELING FOR MULTI-BEAM CONCURRENT TRANSMISSIONSijwmn
The paper presents a Riverbed simulator implementation with both routing and medium access control
(MAC) protocols for mobile ad-hoc network wireless networks with multi-beam smart antennas (MBSAs).
As one of the latest promising antenna techniques, MBSAs can achieve concurrent transmissions /
receptions in multiple directions/beams. Thus it can significantly improve the network throughput.
However, so far there is still no accurate network simulator that can measure the MBSA-based
routing/MAC protocol performance. In this paper, we describe the simulation models with the
implementation of MBSA antenna model in physical layer, MAC layer, and routing layer protocols, all in
Riverbed Modeler. We will compare two routing scenarios, i.e., multi-hop diamond routing scenario and
multi-path pipe routing. We will analyze the network performance for those two scenarios and illustrate the
advantages of using MBSAs in wireless networks.
RIVERBED-BASED NETWORK MODELING FOR MULTI-BEAM CONCURRENT TRANSMISSIONSijwmn
The paper presents a Riverbed simulator implementation with both routing and medium access control
(MAC) protocols for mobile ad-hoc network wireless networks with multi-beam smart antennas (MBSAs).
As one of the latest promising antenna techniques, MBSAs can achieve concurrent transmissions /
receptions in multiple directions/beams. Thus it can significantly improve the network throughput.
However, so far there is still no accurate network simulator that can measure the MBSA-based
routing/MAC protocol performance. In this paper, we describe the simulation models with the
implementation of MBSA antenna model in physical layer, MAC layer, and routing layer protocols, all in
Riverbed Modeler. We will compare two routing scenarios, i.e., multi-hop diamond routing scenario and
multi-path pipe routing. We will analyze the network performance for those two scenarios and illustrate the
advantages of using MBSAs in wireless networks.
DESIGN AND MODELLING OF DIFFERENT SRAM’S BASED ON CNTFET 32NM TECHNOLOGYVLSICS Design
Carbon nanotube field-effect transistor (CNTFET) refers to a field-effect transistor that utilizes a single carbon nanotube or an array of carbon nanotubes as the channel material instead of bulk silicon in the traditional MOSFET structure. Since it was first demonstrated in 1998, there have been tremendous developments in CNTFETs, which promise for an alternative material to replace silicon in future electronics. Carbon nanotubes are promising materials for the nano-scale electron devices such as nanotube FETs for ultra-high density integrated circuits and quantum-effect devices for novel intelligent circuits, which are expected to bring a breakthrough in the present silicon technology. A Static Random Access Memory (SRAM) is designed to plug two needs: i) The SRAM provides as cache memory, communicating between central processing unit and Dynamic Random Access Memory (DRAM). ii) The SRAM technology act as driving force for low power application since SRAM is portable compared to DRAM, and SRAM doesn’t require any refresh current. On the basis of acquired knowledge, we present
different SRAM's designed for the conventional CNTFET. HSPICE simulations of this circuit using Stanford CNTFET model shows a great improvement in power saving.
IOSR Journal of Electronics and Communication Engineering(IOSR-JECE) is an open access international journal that provides rapid publication (within a month) of articles in all areas of electronics and communication engineering and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications in electronics and communication engineering. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
Crdom cell re ordering based domino on-the-fly mappingVLSICS Design
This Domino logic is often the choice for designing high speed CMOS circuits. Often VLSI designers
choose library based approaches to perform technology mapping of large scale circuits involving static
CMOS logic style. Cells designed using Domino logic style have the flexibility to accommodate wide range
of functions in them. Hence, there is a scope to adopt a library free synthesis approach for circuits
designed using Domino logic. In this work, we present an approach for mapping a domino logic circuit
using an On-the-fly technique. First, we present a node mapping algorithm which maps a given Domino
logic netlist using On-the-fly technique. Next, using an Equivalence Table, we re-order the cells along the
critical path for delay, area benefit. Finally, we find an optimum re-ordering set which can obtain
maximum delay savings for a minimum area penalty. We have tested the efficacy of our approach with a
set of standard benchmark circuits. Our proposed mapping approach (CRDOM) obtained 21%
improvement in area and 17% improvement in delay compared to existing work.
Research Inventy : International Journal of Engineering and Scienceresearchinventy
Research Inventy : International Journal of Engineering and Science is published by the group of young academic and industrial researchers with 12 Issues per year. It is an online as well as print version open access journal that provides rapid publication (monthly) of articles in all areas of the subject such as: civil, mechanical, chemical, electronic and computer engineering as well as production and information technology. The Journal welcomes the submission of manuscripts that meet the general criteria of significance and scientific excellence. Papers will be published by rapid process within 20 days after acceptance and peer review process takes only 7 days. All articles published in Research Inventy will be peer-reviewed.
SINGLE-PORT FIVE-TRANSISTOR SRAM CELL WITH REDUCED LEAKAGE CURRENT IN STANDBYVLSICS Design
In this paper, a new single-port five-transistor (5T) Static Random Access Memory (SRAM) cell with
integrated read/write assist is proposed. Amongst the assist circuitry, a voltage control circuit is coupled to
the sources corresponding to driver transistors of each row memory cells. This configuration is aimed to
control the source voltages of driver transistors under different operating modes. Specifically, during a
write operation, by means of sizing the driver transistor close to bitline to resolve the write ‘1’ issue. In
addition, associated with a two-stage reading mechanism to increase the reading speed and to avoid
unnecessary power consumption. Finally, with the standby start-up cir
RIVERBED-BASED NETWORK MODELING FOR MULTI-BEAM CONCURRENT TRANSMISSIONSijwmn
The paper presents a Riverbed simulator implementation with both routing and medium access control
(MAC) protocols for mobile ad-hoc network wireless networks with multi-beam smart antennas (MBSAs).
As one of the latest promising antenna techniques, MBSAs can achieve concurrent transmissions /
receptions in multiple directions/beams. Thus it can significantly improve the network throughput.
However, so far there is still no accurate network simulator that can measure the MBSA-based
routing/MAC protocol performance. In this paper, we describe the simulation models with the
implementation of MBSA antenna model in physical layer, MAC layer, and routing layer protocols, all in
Riverbed Modeler. We will compare two routing scenarios, i.e., multi-hop diamond routing scenario and
multi-path pipe routing. We will analyze the network performance for those two scenarios and illustrate the
advantages of using MBSAs in wireless networks.
RIVERBED-BASED NETWORK MODELING FOR MULTI-BEAM CONCURRENT TRANSMISSIONSijwmn
The paper presents a Riverbed simulator implementation with both routing and medium access control
(MAC) protocols for mobile ad-hoc network wireless networks with multi-beam smart antennas (MBSAs).
As one of the latest promising antenna techniques, MBSAs can achieve concurrent transmissions /
receptions in multiple directions/beams. Thus it can significantly improve the network throughput.
However, so far there is still no accurate network simulator that can measure the MBSA-based
routing/MAC protocol performance. In this paper, we describe the simulation models with the
implementation of MBSA antenna model in physical layer, MAC layer, and routing layer protocols, all in
Riverbed Modeler. We will compare two routing scenarios, i.e., multi-hop diamond routing scenario and
multi-path pipe routing. We will analyze the network performance for those two scenarios and illustrate the
advantages of using MBSAs in wireless networks.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Performance Evaluation of Finite Queue Switching Under Two-Dimensional M/G/1...Syeful Islam
Abstract—In this paper we consider a local area network (LAN) of dual mode service
where one is a token bus and the other is a carrier sense multiple access with a collision
detection (CSMA/CD) bus. The objective of the paper is to find the overall cell/packet
dropping probability of a dual mode LAN for finitelength queue M/G/1(m) traffic. Here, the
offered traffic of the LAN is taken to be the equivalent carried traffic of a one-millisecond
delay. The concept of a tabular solution for two-dimensional Poisson’s traffic of circuit
switching is adapted here to find the cell dropping probability of the dual mode packet
service. Although the work is done for the traffic of similar bandwidth, it can be extended
for the case of a dissimilar bandwidth of a circuit switched network.
Time and Low Power Operation Using Embedded Dram to Gain Cell Data RetentionIJMTST Journal
Logic compatible gain cell (GC)-embedded DRAM (eDRAM) arrays are considered an alternative to SRAM because of their small size, non rationed operation, low static leakage, and two port functionality. But traditional GC-eDRAM implementations require boosted control signals in order to write full voltage levels to the cell to reduce the refresh rate and shorten access times. The boosted levels require an extra power supply or on-chip charge pumps, as well as nontrivial level shifting and toleration of high voltage levels. In this paper, we present a novel, logic compatible, 3T GC-eDRAM bit cell that operates with a single-supply voltage and provides superior write capability to the conventional GC structures. The proposed circuit is demonstrated in 0.25μm CMOS process targeted at low power, energy efficient application.
Implementation of High Reliable 6T SRAM Cell Designiosrjce
Memory can be formed with the integration of large number of basic storing element called cells.
SRAM cell is one of the basic storing unit of volatile semiconductor memory that stores binary logic '1' or '0' bit.
Modified read and write circuits were proposed in this paper to address incorrect read and write operations in
conventional 6T SRAM cell design available in open literature. Design of a new highly reliable 6T SRAM cell
design is proposed with reliable read, write operations and negative bit line voltage (NBLV). Simulations are
carried out using MENTOR GRAPHICS
PERFORMANCE ANALYSIS OF SRAM CELL USING REVERSIBLE LOGIC GATESBUKYABALAJI
ABSTRACT: Reversible logic shows a great potential
in the design of Low-power circuits. Remarkable work
has been done in design of basic arithmetic circuits.
Present day progress in sequential circuit design of
reversible logic circuits has shown new ways in
performance of Static random access memory
(SRAM) and Dynamic random access memory
(DRAM). As the memory size is increasing
exponentially, the power absorbed by memory cells is
also growing rapidly. In recent years reversible logic
has achieved great interest because of its low power
performances. This paper proposes a new SRAM
c e l l which u s e s Feynman gates. The proposed
SRAM cell shows reduction of 66% in terms of
quantum cost, 66% reduction in quantum delay, 60%
reduction in number of gates count and 50% reduction
in number of transistors count
Interconnected Serialized Architecture for Transmission SystemsIJERD Editor
Transmission system with proposed multiplexer-flip-flops (MUX-FFs) has a high throughput and low-cost solution for serial link transmitters. MUX-FFs is designed with proposed multiplexer-latches that possess a logic function of various combinational circuits and storing capacity of sequential circuits. Pipeline arrangement with MUX-FFs composed of cascaded latches and MUX-latches with this many latch gates for sequential can be removed. Simulation results show that a 8-to-1 serializer with MUX-FFs reduces 63% gate-count compared to traditional pipeline transmission architecture. The measured results shows that the MUX-FFs and the proposed transmission architecture are almost bit error free and high speed in transmission.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
call for paper 2012, hard copy of journal, research paper publishing, where to publish research paper,
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
STUDY OF SPIN TRANSFER TORQUE (STT) AND SPIN ORBIT TORQUE (SOT) MAGNETIC TUNN...elelijjournal
Magnetic Random Access Memory (MRAM) is a promising candidate to be the universal non-volatile (NV) storage device. The Magnetic Tunnel Junction (MTJ) is the cornerstone of the NV-MRAM technology. 2- terminal MTJ based on Spin Transfer Torque (STT) switching is considered as a hot topic for academic and industrial researchers. Moreover, the 3-terminal Spin Orbit Torque (SOT) MTJ has recently been considered as a hopeful device which provides an increased reliability thanks to independent write and read paths. Since both MTJ devices (STT and SOT) seem to revolutionize the data storage market, it is necessary to explore their compatibility with very advanced CMOS processes in terms of transistor sizing and performance. Assuming a good maturity of the magnetic processes that would enable to fabricate small junctions, simulation results show that the existing advanced sub-micronic CMOS processes can drive the required writing current with reasonable size of transistors confirming the high density feature of MRAMs. At 28 nm node, the minimum transistor size can be used by the STT device. The SOT device shows remarkable energy efficiency with 6× improvement compared with the STT technology. Results are very encouraging for future complex hybrid magnetic/CMOS integrated circuits (ICs).
Power analysis of 4 t sram by stacking technique using tanner tooleSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Optimized Design of 2D Mesh NOC Router using Custom SRAM & Common Buffer Util...VLSICS Design
With the shrinking technology, reduced scale and power-hungry chip IO leads to System on Chip. The design of SOC using traditional standard bus scheme encounters with issues like non-uniform delay and routing problems. Crossbars could scale better when compared to buses but tend to become huge with increasing number of nodes. NOC has become the design paradigm for SOC design for its highly regularized interconnect structure, good scalability and linear design effort. The main components of an NoC topology are the network adapters, routing nodes, and network interconnect links. This paper mainly deals with the implementation of full custom SRAM based arrays over D FF based register arrays in the design of input module of routing node in 2D mesh NOC topology. The custom SRAM blocks replace D FF(D flip flop) memory implementations to optimize area and power of the input block. Full custom design of SRAMs has been carried out by MILKYWAY, while physical implementation of the input module with SRAMs has been carried out by IC Compiler of SYNOPSYS.The improved design occupies approximately 30% of the area of the original design. This is in conformity to the ratio of the area of an SRAM cell to the area of a D flip flop, which is approximately 6:28.The power consumption is almost halved to 1.5 mW. Maximum operating frequency is improved from 50 MHz to 200 MHz. It is intended to study and quantify the behavior of the single packet array design in relation to the multiple packet array design. Intuitively, a
common packet buffer would result in better utilization of available buffer space. This in turn would translate into lower delays in transmission. A MATLAB model is used to show quantitatively how performance is improved in a common packet array design.
Design of Quaternary Logical Circuit Using Voltage and Current Mode LogicVLSICS Design
In VLSI technology, designers main concentration were on area required and on performance of the device. In VLSI design power consumption is one of the major concerns due to continuous increase in chip density and decline in size of CMOS circuits and frequency at which circuits are operating. By considering these parameter logical circuits are designed using quaternary voltage mode logic and quaternary current mode logic. Power consumption required for quaternary voltage mode logic is 51.78 % less as compared to binary . Area in terms of number of transistor required for quaternary voltage mode logic is 3 times more as compared to binary. As quaternary voltage mode circuit required large area as compared to quaternary current mode circuit but power consumption required in quaternary voltage mode circuit is less than that required in quaternary current mode circuit.
A Novel Low Power Energy Efficient SRAM Cell With Reduced Power Consumption u...iosrjce
In modern high performance integrated circuits, maximum of the total active mode energy is
consumed due to leakage current. SRAM cell array is main source of leakage current since majority of
transistor are utilized for on-chip memory in today high performance microprocessor and system on chip
designs. Therefore the design of low leakage SRAM is required. Reducing power dissipation, supply voltage,
leakage currents, area of chip are the most important parameters in today`s VLSI designs. But scaling of these
parameters will lead to drastic increase in sub threshold leakage currents and power dissipation because of that
performance of the design is degraded. So to overcome these issues it is better to concentrate on reduction of
active leakage currents and dynamic power dissipation by using power reduction techniques. In this paper 9T
SRAM (data retention p-gated) cell for low voltage and energy constrain application is analyzed with respect to
power dissipation, area and delay. The analyzed design of 9T SRAM cell with MTCMOS technique has been
proposed. Designed circuits are simulated in Microwind 3.1 VLSI CAD Tool in 90 and 65nm CMOS technology.
IMPLEMENTATION OF LOW POWER ADIABATIC SRAMVLSICS Design
In the featuring VLSI era, compact electronic devices are popular. The reliability and durability of such compact devices relies on low power utilization. The purpose of this project was to implement a low power adiabatic Static Random Access Memory (SRAM), with the following objectives - To reduce the power waste by means of stepwise charging using tank capacitors which is an adiabatic way of generating power
clock. This method is capable of recuperating the electrical energy back to the source. Further to examine the Static Noise Margin (SNM) – a parameter which gives detailed information about the cell stability – in
contrast with conventional 6T, 7T and 8T topologies of SRAM under 180 nm technology. Finally, SNM variations with respect to process parameters are also discussed. All the implementations and analysis were made using CADENCE tool and MATLAB tool.
IMPLEMENTATION OF LOW POWER ADIABATIC SRAMVLSICS Design
In the featuring VLSI era, compact electronic devices are popular. The reliability and durability of such compact devices relies on low power utilization. The purpose of this project was to implement a low power adiabatic Static Random Access Memory (SRAM), with the following objectives - To reduce the power waste by means of stepwise charging using tank capacitors which is an adiabatic way of generating power
clock. This method is capable of recuperating the electrical energy back to the source. Further to examine the Static Noise Margin (SNM) – a parameter which gives detailed information about the cell stability – in contrast with conventional 6T, 7T and 8T topologies of SRAM under 180 nm technology. Finally, SNM
variations with respect to process parameters are also discussed. All the implementations and analysis were made using CADENCE tool and MATLAB tool.
IMPLEMENTATION OF LOW POWER ADIABATIC SRAMVLSICS Design
In the featuring VLSI era, compact electronic devices are popular. The reliability and durability of such compact devices relies on low power utilization. The purpose of this project was to implement a low power adiabatic Static Random Access Memory (SRAM), with the following objectives - To reduce the power waste by means of stepwise charging using tank capacitors which is an adiabatic way of generating power clock. This method is capable of recuperating the electrical energy back to the source. Further to examine the Static Noise Margin (SNM) – a parameter which gives detailed information about the cell stability – in contrast with conventional 6T, 7T and 8T topologies of SRAM under 180 nm technology. Finally, SNM variations with respect to process parameters are also discussed. All the implementations and analysis were made using CADENCE tool and MATLAB tool.
This paper proposes a variation – tolerant dual-diameter CNFET-based 7T (seven transistor) SRAM (static random access memory) cell. The use of appropriate DCNT (diameter of CNFET) and hence Vt of CNFETs is a critical piece of our design strategy. In this work, dual-Vt and dual-diameter CNFETs have been used using suitable chiral vectors for appropriate transistors. It also investigates the impact of process, voltage and temperature variations on its design metrics and compares the results with its counterpart − CMOS-based 7T SRAM cell and standard 6T SRAM cell (only few parameters). The proposed SRAM cell offers 1.35× and 1.25× improvement in standby power on an average @ VDD = 1 V and 0.9 V respectively, 30% improvement in SNM (Static Noise Margin) over CMOS-based 7T cell. Proposed design outperforms 6T in terms of 71.4% improvement in RSNM and shows same read stability as its CMOS counterpart, It shows its robustness by offering 1.4× less spread in TRA (read access time) at 1 V and 1.2× less spread in TRA at 0.9 V than that of its CMOS counterpart at the expense of 1.6× read delay. The proposed bitcell also exhibits higher performance while writing (takes 1.3× and 1.2× less TWA (write access time) @ VDD = 1 V and VDD= 0.9 V respectively). It also proves its robustness against process variations by featuring tighter spread in TWA variability (1.4× and 1.2× @ VDD= 1 V and 0.9 V respectively).
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Performance Evaluation of Finite Queue Switching Under Two-Dimensional M/G/1...Syeful Islam
Abstract—In this paper we consider a local area network (LAN) of dual mode service
where one is a token bus and the other is a carrier sense multiple access with a collision
detection (CSMA/CD) bus. The objective of the paper is to find the overall cell/packet
dropping probability of a dual mode LAN for finitelength queue M/G/1(m) traffic. Here, the
offered traffic of the LAN is taken to be the equivalent carried traffic of a one-millisecond
delay. The concept of a tabular solution for two-dimensional Poisson’s traffic of circuit
switching is adapted here to find the cell dropping probability of the dual mode packet
service. Although the work is done for the traffic of similar bandwidth, it can be extended
for the case of a dissimilar bandwidth of a circuit switched network.
Time and Low Power Operation Using Embedded Dram to Gain Cell Data RetentionIJMTST Journal
Logic compatible gain cell (GC)-embedded DRAM (eDRAM) arrays are considered an alternative to SRAM because of their small size, non rationed operation, low static leakage, and two port functionality. But traditional GC-eDRAM implementations require boosted control signals in order to write full voltage levels to the cell to reduce the refresh rate and shorten access times. The boosted levels require an extra power supply or on-chip charge pumps, as well as nontrivial level shifting and toleration of high voltage levels. In this paper, we present a novel, logic compatible, 3T GC-eDRAM bit cell that operates with a single-supply voltage and provides superior write capability to the conventional GC structures. The proposed circuit is demonstrated in 0.25μm CMOS process targeted at low power, energy efficient application.
Implementation of High Reliable 6T SRAM Cell Designiosrjce
Memory can be formed with the integration of large number of basic storing element called cells.
SRAM cell is one of the basic storing unit of volatile semiconductor memory that stores binary logic '1' or '0' bit.
Modified read and write circuits were proposed in this paper to address incorrect read and write operations in
conventional 6T SRAM cell design available in open literature. Design of a new highly reliable 6T SRAM cell
design is proposed with reliable read, write operations and negative bit line voltage (NBLV). Simulations are
carried out using MENTOR GRAPHICS
PERFORMANCE ANALYSIS OF SRAM CELL USING REVERSIBLE LOGIC GATESBUKYABALAJI
ABSTRACT: Reversible logic shows a great potential
in the design of Low-power circuits. Remarkable work
has been done in design of basic arithmetic circuits.
Present day progress in sequential circuit design of
reversible logic circuits has shown new ways in
performance of Static random access memory
(SRAM) and Dynamic random access memory
(DRAM). As the memory size is increasing
exponentially, the power absorbed by memory cells is
also growing rapidly. In recent years reversible logic
has achieved great interest because of its low power
performances. This paper proposes a new SRAM
c e l l which u s e s Feynman gates. The proposed
SRAM cell shows reduction of 66% in terms of
quantum cost, 66% reduction in quantum delay, 60%
reduction in number of gates count and 50% reduction
in number of transistors count
Interconnected Serialized Architecture for Transmission SystemsIJERD Editor
Transmission system with proposed multiplexer-flip-flops (MUX-FFs) has a high throughput and low-cost solution for serial link transmitters. MUX-FFs is designed with proposed multiplexer-latches that possess a logic function of various combinational circuits and storing capacity of sequential circuits. Pipeline arrangement with MUX-FFs composed of cascaded latches and MUX-latches with this many latch gates for sequential can be removed. Simulation results show that a 8-to-1 serializer with MUX-FFs reduces 63% gate-count compared to traditional pipeline transmission architecture. The measured results shows that the MUX-FFs and the proposed transmission architecture are almost bit error free and high speed in transmission.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
call for paper 2012, hard copy of journal, research paper publishing, where to publish research paper,
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
STUDY OF SPIN TRANSFER TORQUE (STT) AND SPIN ORBIT TORQUE (SOT) MAGNETIC TUNN...elelijjournal
Magnetic Random Access Memory (MRAM) is a promising candidate to be the universal non-volatile (NV) storage device. The Magnetic Tunnel Junction (MTJ) is the cornerstone of the NV-MRAM technology. 2- terminal MTJ based on Spin Transfer Torque (STT) switching is considered as a hot topic for academic and industrial researchers. Moreover, the 3-terminal Spin Orbit Torque (SOT) MTJ has recently been considered as a hopeful device which provides an increased reliability thanks to independent write and read paths. Since both MTJ devices (STT and SOT) seem to revolutionize the data storage market, it is necessary to explore their compatibility with very advanced CMOS processes in terms of transistor sizing and performance. Assuming a good maturity of the magnetic processes that would enable to fabricate small junctions, simulation results show that the existing advanced sub-micronic CMOS processes can drive the required writing current with reasonable size of transistors confirming the high density feature of MRAMs. At 28 nm node, the minimum transistor size can be used by the STT device. The SOT device shows remarkable energy efficiency with 6× improvement compared with the STT technology. Results are very encouraging for future complex hybrid magnetic/CMOS integrated circuits (ICs).
Power analysis of 4 t sram by stacking technique using tanner tooleSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Optimized Design of 2D Mesh NOC Router using Custom SRAM & Common Buffer Util...VLSICS Design
With the shrinking technology, reduced scale and power-hungry chip IO leads to System on Chip. The design of SOC using traditional standard bus scheme encounters with issues like non-uniform delay and routing problems. Crossbars could scale better when compared to buses but tend to become huge with increasing number of nodes. NOC has become the design paradigm for SOC design for its highly regularized interconnect structure, good scalability and linear design effort. The main components of an NoC topology are the network adapters, routing nodes, and network interconnect links. This paper mainly deals with the implementation of full custom SRAM based arrays over D FF based register arrays in the design of input module of routing node in 2D mesh NOC topology. The custom SRAM blocks replace D FF(D flip flop) memory implementations to optimize area and power of the input block. Full custom design of SRAMs has been carried out by MILKYWAY, while physical implementation of the input module with SRAMs has been carried out by IC Compiler of SYNOPSYS.The improved design occupies approximately 30% of the area of the original design. This is in conformity to the ratio of the area of an SRAM cell to the area of a D flip flop, which is approximately 6:28.The power consumption is almost halved to 1.5 mW. Maximum operating frequency is improved from 50 MHz to 200 MHz. It is intended to study and quantify the behavior of the single packet array design in relation to the multiple packet array design. Intuitively, a
common packet buffer would result in better utilization of available buffer space. This in turn would translate into lower delays in transmission. A MATLAB model is used to show quantitatively how performance is improved in a common packet array design.
Design of Quaternary Logical Circuit Using Voltage and Current Mode LogicVLSICS Design
In VLSI technology, designers main concentration were on area required and on performance of the device. In VLSI design power consumption is one of the major concerns due to continuous increase in chip density and decline in size of CMOS circuits and frequency at which circuits are operating. By considering these parameter logical circuits are designed using quaternary voltage mode logic and quaternary current mode logic. Power consumption required for quaternary voltage mode logic is 51.78 % less as compared to binary . Area in terms of number of transistor required for quaternary voltage mode logic is 3 times more as compared to binary. As quaternary voltage mode circuit required large area as compared to quaternary current mode circuit but power consumption required in quaternary voltage mode circuit is less than that required in quaternary current mode circuit.
A Novel Low Power Energy Efficient SRAM Cell With Reduced Power Consumption u...iosrjce
In modern high performance integrated circuits, maximum of the total active mode energy is
consumed due to leakage current. SRAM cell array is main source of leakage current since majority of
transistor are utilized for on-chip memory in today high performance microprocessor and system on chip
designs. Therefore the design of low leakage SRAM is required. Reducing power dissipation, supply voltage,
leakage currents, area of chip are the most important parameters in today`s VLSI designs. But scaling of these
parameters will lead to drastic increase in sub threshold leakage currents and power dissipation because of that
performance of the design is degraded. So to overcome these issues it is better to concentrate on reduction of
active leakage currents and dynamic power dissipation by using power reduction techniques. In this paper 9T
SRAM (data retention p-gated) cell for low voltage and energy constrain application is analyzed with respect to
power dissipation, area and delay. The analyzed design of 9T SRAM cell with MTCMOS technique has been
proposed. Designed circuits are simulated in Microwind 3.1 VLSI CAD Tool in 90 and 65nm CMOS technology.
IMPLEMENTATION OF LOW POWER ADIABATIC SRAMVLSICS Design
In the featuring VLSI era, compact electronic devices are popular. The reliability and durability of such compact devices relies on low power utilization. The purpose of this project was to implement a low power adiabatic Static Random Access Memory (SRAM), with the following objectives - To reduce the power waste by means of stepwise charging using tank capacitors which is an adiabatic way of generating power
clock. This method is capable of recuperating the electrical energy back to the source. Further to examine the Static Noise Margin (SNM) – a parameter which gives detailed information about the cell stability – in
contrast with conventional 6T, 7T and 8T topologies of SRAM under 180 nm technology. Finally, SNM variations with respect to process parameters are also discussed. All the implementations and analysis were made using CADENCE tool and MATLAB tool.
IMPLEMENTATION OF LOW POWER ADIABATIC SRAMVLSICS Design
In the featuring VLSI era, compact electronic devices are popular. The reliability and durability of such compact devices relies on low power utilization. The purpose of this project was to implement a low power adiabatic Static Random Access Memory (SRAM), with the following objectives - To reduce the power waste by means of stepwise charging using tank capacitors which is an adiabatic way of generating power
clock. This method is capable of recuperating the electrical energy back to the source. Further to examine the Static Noise Margin (SNM) – a parameter which gives detailed information about the cell stability – in contrast with conventional 6T, 7T and 8T topologies of SRAM under 180 nm technology. Finally, SNM
variations with respect to process parameters are also discussed. All the implementations and analysis were made using CADENCE tool and MATLAB tool.
IMPLEMENTATION OF LOW POWER ADIABATIC SRAMVLSICS Design
In the featuring VLSI era, compact electronic devices are popular. The reliability and durability of such compact devices relies on low power utilization. The purpose of this project was to implement a low power adiabatic Static Random Access Memory (SRAM), with the following objectives - To reduce the power waste by means of stepwise charging using tank capacitors which is an adiabatic way of generating power clock. This method is capable of recuperating the electrical energy back to the source. Further to examine the Static Noise Margin (SNM) – a parameter which gives detailed information about the cell stability – in contrast with conventional 6T, 7T and 8T topologies of SRAM under 180 nm technology. Finally, SNM variations with respect to process parameters are also discussed. All the implementations and analysis were made using CADENCE tool and MATLAB tool.
This paper proposes a variation – tolerant dual-diameter CNFET-based 7T (seven transistor) SRAM (static random access memory) cell. The use of appropriate DCNT (diameter of CNFET) and hence Vt of CNFETs is a critical piece of our design strategy. In this work, dual-Vt and dual-diameter CNFETs have been used using suitable chiral vectors for appropriate transistors. It also investigates the impact of process, voltage and temperature variations on its design metrics and compares the results with its counterpart − CMOS-based 7T SRAM cell and standard 6T SRAM cell (only few parameters). The proposed SRAM cell offers 1.35× and 1.25× improvement in standby power on an average @ VDD = 1 V and 0.9 V respectively, 30% improvement in SNM (Static Noise Margin) over CMOS-based 7T cell. Proposed design outperforms 6T in terms of 71.4% improvement in RSNM and shows same read stability as its CMOS counterpart, It shows its robustness by offering 1.4× less spread in TRA (read access time) at 1 V and 1.2× less spread in TRA at 0.9 V than that of its CMOS counterpart at the expense of 1.6× read delay. The proposed bitcell also exhibits higher performance while writing (takes 1.3× and 1.2× less TWA (write access time) @ VDD = 1 V and VDD= 0.9 V respectively). It also proves its robustness against process variations by featuring tighter spread in TWA variability (1.4× and 1.2× @ VDD= 1 V and 0.9 V respectively).
CELL STABILITY ANALYSIS OF CONVENTIONAL 6T DYNAMIC 8T SRAM CELL IN 45NM TECHN...VLSICS Design
A SRAM cell must meet requirements for operation in submicron/nano ranges. The scaling of CMOS technology has significant impact on SRAM cell -- random fluctuation of electrical characteristics and substantial leakage current. In this paper we present dynamic column based power supply 8T SRAM cell and comparing the proposed SRAM cell with respect to conventional SRAM 6T in various aspects. To verify read stability and write ability analysis we use N-curve metric. Simulation results affirmed that proposed 8T SRAM cell achieved improved read stability, read current, and leakage current in 45nm Technology comparing with conventional 6T SRAM using cadence virtuoso tool.
CNFET BASED BASIC GATES AND A NOVEL FULLADDER CELLVLSICS Design
In this paper two novel high performance designs for AND and OR basic gates and a novel Full-Adder Cell are presented. These designs are based on carbon nanotube technology. In order to compare the proposed designs with previous ones both MOSFET based and CNFET based circuits are selected. By the way the proposed designs have better performance in comparison with previous designs in terms of speed, power consumption and power-delay product (PDP).
Energy optimization of 6T SRAM cell using low-voltage and high-performance in...IJECEIAES
The performance of the cell deteriorates, when static random access memory (SRAM) cell is operated below 1V supply voltage with continuous scale down of the complementary metal oxide semiconductor (CMOS) technology. The conventional 6T, 8T-SRAM cells suffer writeability and read static noise margins (SNM) at low-voltages leads to degradation of cell stability. To improve the cell stability and reduce the dynamic power dissipation at low- voltages of the SRAM cell, we proposed four SRAM cells based on inverter structures with less energy consumption using voltage divider bias current sink/source inverter and NOR/NAND gate using a pseudo-nMOS inverter. The design and implementation of SRAM cell using proposed inverter structures are compared with standard 6T, 8T and ST-11T SRAM cells for different supply voltages at 22-nm CMOS technology exhibit better performance of the cell. The read/write static noise margin of the cell significantly increases due to voltage divider bias network built with larger cell-ratio during read path. The load capacitance of the cell is reduced with minimized switching transitions of the devices during high-to-low and low- to-high of the pull-up and pull-down networks from VDD to ground leads to on an average 54% of dynamic power consumption. When compared with the existing ones, the read/write power of the proposed cells is reduced to 30%. The static power gets reduced by 24% due to stacking of transistors takes place in the proposed SRAM cells as compare to existing ones. The layout of the proposed cells is drawn at a 45-nm technology, and occupies an area of 1.5 times greater and 1.8 times greater as compared with 6T-SRAM cell.
250nm Technology Based Low Power SRAM Memoryiosrjce
High integration density, low power and fastperformance are all critical parameters in designing of
memory blocks. Static Random Access Memories (SRAMs)’s focusing on optimizing dynamic power concept of
virtual source transistors is used for removing direct connection between VDD and GND.
Also stacking effect can be reduced by switching off the stacktransistors when the memory is ideal and the
leakage current using SVL techniques This paper discusses the evolution of 9t SRAM circuits in terms of low
power consumption, The whole circuit verification is done on the Tanner tool, Schematic of the
SRAM cell is designed on the S-Edit and net list simulation done by using T-spice and waveforms are analyzed
through the W-edit
Designing High-Speed, Low-Power Full Adder Cells Based on Carbon Nanotube Tec...VLSICS Design
This article presents novel high speed and low power full adder cells based on carbon nanotube field effect
transistor (CNFET). Four full adder cells are proposed in this article. First one (named CN9P4G) and
second one (CN9P8GBUFF) utilizes 13 and 17 CNFETs respectively. Third design that we named
CN10PFS uses only 10 transistors and is full swing. Finally, CN8P10G uses 18 transistors and divided into
two modules, causing Sum and Cout signals are produced in a parallel manner. All inputs have been used
straight, without inverting. These designs also used the special feature of CNFET that is controlling the
threshold voltage by adjusting the diameters of CNFETs to achieve the best performance and right voltage
levels. All simulation performed using Synopsys HSPICE software and the proposed designs are compared
to other classical and modern CMOS and CNFET-based full adder cells in terms of delay, power
consumption and power delay product.
PERFORMANCE EVALUATION OF DIFFERENT SRAM CELL STRUCTURES AT DIFFERENT TECHNOL...VLSICS Design
In recent years the demand for low power devices has been increases tremendously. To solve the power dissipation problem, many researchers have proposed different ideas from the device level to the architectural level and above. However, there is no universal way to avoid tradeoffs between power, delay and area, thus designers are required to choose appropriate techniques that satisfy application and product needs. The demand for static random-access memory (SRAM) is increasing with large use of SRAM in System On-Chip and high-performance VLSI circuits. This paper represents the simulation of different SRAM cells and their comparative analysis on different parameters such as Power Supply Voltage, area efficiency etc to enhance the performance. All the simulations have been carried out on BSIM 3V3 90nm, 45nm and 32 technology at Tanner EDA tool.
This paper investigates the leakage current, static noise margin (SNM), delay and energy consumption of a
6 transistor FinFET based static random-access memory (SRAM) cell due to the variation in design and
operating parameters of the SRAM cell. The SRAM design and operating parameters considered in this
investigation are transistor sizing, supply voltage, word-line voltage, temperature and PFET and NFET
back gate biasing. This investigation is performed using a 11nm FinFET shorted gate and low power
technology models. Based on the investigation results, we propose a robust 6 transistor SRAM cells with
optimized performance using shorted gate and independent gate low power FinFET models. By optimizing
the design parameters of the cell, the shorted-gate design shows an improvement of read SNM of 261.56mV
and an improvement of hold SNM of 87.68mV when compared to a shorted-gate cell with standard design
parameters. The low-power design shows an improvement of read SNM of 146.18mV and a marginal
decrease in hold SNM of 22.84mV when compared to a low-power cell with standard design parameters.
Both the cells with the new optimized design parameters are shown to improve the overall SNM of the cells
with minimal impact on the subthreshold leakage currents, performance and energy consumption.
This paper investigates the leakage current, static noise margin (SNM), delay and energy consumption of a
6 transistor FinFET based static random-access memory (SRAM) cell due to the variation in design and
operating parameters of the SRAM cell. The SRAM design and operating parameters considered in this
investigation are transistor sizing, supply voltage, word-line voltage, temperature and PFET and NFET
back gate biasing. This investigation is performed using a 11nm FinFET shorted gate and low power
technology models. Based on the investigation results, we propose a robust 6 transistor SRAM cells with
optimized performance using shorted gate and independent gate low power FinFET models. By optimizing
the design parameters of the cell, the shorted-gate design shows an improvement of read SNM of 261.56mV
and an improvement of hold SNM of 87.68mV when compared to a shorted-gate cell with standard design
parameters. The low-power design shows an improvement of read SNM of 146.18mV and a marginal
decrease in hold SNM of 22.84mV when compared to a low-power cell with standard design parameters.
Both the cells with the new optimized design parameters are shown to improve the overall SNM of the cells
with minimal impact on the subthreshold leakage currents, performance and energy consumption.
This paper investigates the leakage current, static noise margin (SNM), delay and energy consumption of a 6 transistor FinFET based static random-access memory (SRAM) cell due to the variation in design and operating parameters of the SRAM cell. The SRAM design and operating parameters considered in this
investigation are transistor sizing, supply voltage, word-line voltage, temperature and PFET and NFET back gate biasing. This investigation is performed using a 11nm FinFET shorted gate and low power technology models. Based on the investigation results, we propose a robust 6 transistor SRAM cells with optimized performance using shorted gate and independent gate low power FinFET models. By optimizing
the design parameters of the cell, the shorted-gate design shows an improvement of read SNM of 261.56mV
and an improvement of hold SNM of 87.68mV when compared to a shorted-gate cell with standard design parameters. The low-power design shows an improvement of read SNM of 146.18mV and a marginal decrease in hold SNM of 22.84mV when compared to a low-power cell with standard design parameters. Both the cells with the new optimized design parameters are shown to improve the overall SNM of the cells
with minimal impact on the subthreshold leakage currents, performance and energy consumption.
This paper investigates the leakage current, static noise margin (SNM), delay and energy consumption of a 6 transistor FinFET based static random-access memory (SRAM) cell due to the variation in design and operating parameters of the SRAM cell. The SRAM design and operating parameters considered in this
investigation are transistor sizing, supply voltage, word-line voltage, temperature and PFET and NFET back gate biasing. This investigation is performed using a 11nm FinFET shorted gate and low power technology models. Based on the investigation results, we propose a robust 6 transistor SRAM cells with optimized performance using shorted gate and independent gate low power FinFET models. By optimizing
the design parameters of the cell, the shorted-gate design shows an improvement of read SNM of 261.56mV and an improvement of hold SNM of 87.68mV when compared to a shorted-gate cell with standard design parameters. The low-power design shows an improvement of read SNM of 146.18mV and a marginal decrease in hold SNM of 22.84mV when compared to a low-power cell with standard design parameters.
Both the cells with the new optimized design parameters are shown to improve the overall SNM of the cells with minimal impact on the subthreshold leakage currents, performance and energy consumption.
DESIGNING HIGH-SPEED, LOW-POWER FULL ADDER CELLS BASED ON CARBON NANOTUBE TEC...VLSICS Design
This article presents novel high speed and low power full adder cells based on carbon nanotube field effect transistor (CNFET). Four full adder cells are proposed in this article. First one named CN9P4G) and second one (CN9P8GBUFF) utilizes 13 and 17 CNFETs respectively. Third design that we named CN10PFS uses only 10 transistors and is full swing. Finally, CN8P10G uses 18 transistors and divided into two modules, causing Sum and Cout signals are produced in a parallel manner. All inputs have been used straight, without inverting. These designs also used the special feature of CNFET that is controlling the threshold voltage by adjusting the diameters of CNFETs to achieve the best performance and right voltage levels. All simulation performed using Synopsys HSPICE software and the proposed designs are compared to other classical and modern CMOS and CNFET-based full adder cells in terms of delay, power consumption and power delay product.
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DESIGN OF LOW WRITE-POWER CONSUMPTION SRAM CELL BASED ON CNTFET AT 32nm TECHNOLOGY
1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.4, December 2011
DOI : 10.5121/vlsic.2011.2414 167
DESIGN OF LOW WRITE-POWER CONSUMPTION
SRAM CELL BASED ON CNTFET AT 32nm
TECHNOLOGY
Rajendra Prasad S1
, Prof. B K Madhavi2
and Prof. K Lal Kishore3
1
Department of ECE, ACE Engineering College, Hyderabad, AP, India.
srprasad447@gmail.com
2
Department of ECE, GCET, Keesara, Hyderabad, AP, India.
bkmadhavi2009@gmail.com
3
Department of ECE, JNT University, Hyderabad, AP, India.
lalkishorek@yahoo.com
ABSTRACT
The SRAM which functions as the cache for system-on-chip is vital in the electronic industry. Carbon
Nanotube Field Effect Transistor (CNFET) is used for high performance, high stability and low-power
circuit designs as an alternative material to silicon in recent years. Therefore Design of SRAM Cell based
on CNTFET is important for Low-power cache memory. In cells, the bit-lines are the most power
consuming components because of larger power dissipation in driving long bit-line with large capacitance.
The cache write consumes considerable large power due to full voltage swing on the bit-line. This Paper
proposes a novel 7T SRAM cell based on CNTFET that only depends on one of bit lines for Write operation
and reduce the write-power consumption. The read cycle also improved because of careful transistor
sizing. HSPICE simulations of this circuit using Stanford CNFET model shows that 37.2% write power
saving, read cycle improvement of 38.6%.
KEYWORDS
SRAM Cell, CNTFET, 32nm Technology, HSPICE, Low-Power
1. INTRODUCTION
The power consumption has become an important consideration on the VLSI system design and
microprocessor as the demand for the portable devices and embedded systems continuously
increases [1- 2]. The on-chip caches can reduce the speed gap between the processor and main
memory. These on-chip caches are usually implemented using SRAM cells. The write power is
usually larger than the read power due to large power dissipation in driving the cell bit lines to
full swing. The sum of the power consumption in decoders, bit lines, data lines, sense amplifier,
and periphery circuits represents the active power consumption. The power dissipated in bit-lines
represents 70 per cent of the total SRAM power consumption during a write operation [3]. Many
techniques have been proposed to reduce the write power consumption by reducing the voltage
swing level on the bit lines [4-6]. Especially for modern VLSI processor design, SRAM takes
large part of power consumption portion and area overhead.
2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.4, December 2011
168
Since the first CNTFET was reported in 1998, great progress has been made during the past years
in all the areas of CNTFET science and technology, including materials, devices, and circuits [7].
On the other hand, as the feature size of silicon semiconductor devices scales down to nanometer
range, planar bulk CMOS design and fabrication encounter significant challenges [8]. CNTFET
among other new materials is promising due to the unique one-dimensional band-structure which
reduces backscattering and makes near-ballistic operation. Exceptional electrical properties such
as high speed, high-K compatibility, chemical stability, low SCEs have provided CNFETs with
excellent characteristics which exceed those of the state of the art Si-based MOSFETs. Several
researches have been done to estimate the performance of CNTFET at a single device level in the
presence of process related non-idealities and imperfections at the 32 nm technology node using
compact CNFET SPICE model [9][10].
While seeking for solutions with higher integration, performance, stability, and lower power,
carbon nanotube (CNT) has been presented for next-generation SRAM design as an alternative
material in recent years [11]-[15].This paper proposes a novel 7T SRAM cell based on CNTFET
to reduce dynamic write-power and to improve the read cycle at the cost of minimal increase of
cell area.
2. THE CARBON NANOTUBE FET
Figure 1 illustrates a conceptual layout of a CNT transistor based on Stanford CNFET model.
Ideally, several semiconducting CNTs grow on quartz or Si substrate in an exactly straight and
parallel pattern. Those segments which are covered by gate are intrinsic CNT regions, whose
conductivity is controlled by the gate. Drain and source segments of CNTs are heavily doped to
form Ptype or N-type transistor. The drain, gate and source metal contacts and interconnects are
defined by conventional lithography. Pitch size, namely the inter-CNT distance, is determined by
CNT syntheses process since CNTs are grown in a self-assembly way. Gate width is determined
by CNT tube number and pitch.
Figure 1. The CNTFET layout
CNTFET refers to a field-effect transistor that utilizes a single carbon nanotube or an array of
carbon nanotubes as the channel material instead of bulk silicon in the traditional MOSFET
structure. It is a three-terminal device consisting of a semiconducting nanotube bringing two
contacts (source and drain), and acting as a carrier channel, which is turned on or off electrically
via the third contact (gate).
A single-wall carbon nanotube (SWCNT) is a tube formed by rolling a single sheet of graphene.
It can either be metallic or semiconducting depends on the chirality vector (m, n), i.e. the
direction in that the graphene sheet is rolled. For CNFETs, the threshold voltage of the transistor
3. International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.4, December 2011
169
is defined by the diameter of the carbon nanotubes, which is related to the chirality vector as
follows:
2 2
CNT
a
D mnm nπ
= + +
(1)
3TH
CNT
aV
qD
V π
=
∗
(2)
where q is the charge of an electron, a = 2.49Å is the CNT atomic distance and Vπ= 3.033eV is
the carbon π to π bond energy. The sizing of a CNFET is equivalent to adjusting the number of
tubes. Since the mobility of n-type and the mobility of p-type carriers inside CNTs are identical,
the minimum size is 1 for both P-CNFET and N-CNFET. Semiconducting nanotubes have
attracted widespread attention of the electron device and circuit designers as a promising channel
material for high-performance transistors. A typical structure of a MOSFET-like CNTFET in
planar and co-axial form is illustrated in Figure 2 [16]-[18].
(a)
(b)
Figure 2. The CNTFET Structures: a) planar, b) coaxial
3. THE CONVENTIONAL 6T SRAM CELL
Static Random Access Memory (SRAM) is a type of semiconductor memory. SRAMs are a major
component of digital systems such as Embedded systems, microprocessors, reconfigurable
4. International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.4, December 2011
170
hardware, field programmable gate arrays just to name a few. Fast memory access times and
design for density have been two of the most important target design criteria for many years,
however with device scaling to achieve even faster designs; power supply voltages and device
threshold voltages have scaled as well leading to degradation of standby power and static noise
margins of memories.
Each bit in an SRAM is stored on four transistors that form two cross-coupled inverters. This
storage cell has two stable states which are used to denote “0” and “1”. Two additional access
transistors help controlling the access to the cross coupled unit formed by the inverters during
read and write operations. So typically it takes six transistors to store one memory bit. The design
of a basic SRAM cell is shown in Figure 2. Access to the cell is enabled by the word line (WL)
which controls the two access transistors M5 and M6 which allow the access of the memory cell
to the bit lines: ‘BL’ and ‘BLbar’. They are used to transfer data for both read and write
operations. The presence of dual bit lines i.e. ‘BL’ and ‘BLbar’ improves noise margins over a
single bit line. The symmetric circuit structure allows for accessing a memory location much
faster than in a DRAM. Also the faster operation of an SRAM over DRAM can be attributed to
the fact that it accepts all address bits at a time where as DRAMs typically have the address
multiplexed in two halves, i.e. higher bits followed by lower bits.
The SRAM is operated in one of the three modes namely WRITE, READ and IDLE operations.
The start of a write cycle begins by applying the value to be written and its complement to the bit
lines. In order to write a ‘0’, we would apply a ‘0’ to the bit line ‘BL’ and its complement ‘1’ to
the ‘BLbar’. A ‘1’ is written by inverting the values of the bit lines i.e by setting ‘BL’ to ‘1’ and
‘BLbar’ to ‘0’. ‘WL’ is then made high and the value that is to be stored is latched in. The input-
drivers of the bit lines are designed to be much stronger than the relatively weak transistors in the
cell itself, so that they can easily override the previous state of the cross-coupled inverters. Proper
operation of an SRAM cell however needs careful sizing of the transistors in the unit. The read
cycle is started by asserting the word line ‘WL’, enabling both the access transistors M5 and M6.
The second step occurs when the values stored in ‘Q’ and ‘Qbar’ are transferred to the bit lines
‘BL’ and ‘BLbar’ through M1 and M6. On the BL side, the transistors M4 and M5 pull the bit
line towards VDD (when a “1” is stored at Q). If the content of the memory was a 0, the reverse
would happen and ‘BLbar’ would be pulled towards 1 and ‘BL’ towards 0. For the idle state, the
word line is not asserted and the access transistors M5 and M6 disconnect the cell from the bit
lines. The two cross coupled inverters INV1 and INV2 formed by M1, M2 and M3 M4 will
continue to reinforce each other as long as they are disconnected from any external circuits [19].
The operation of CNFETs based memories is very similar to that of CMOS except for minor
differences in device orientation. One such difference being that the source and drain terminals of
a CNFET are not interchangeable as is the case with MOSFET devices. Care must therefore be
taken to orient the transistors in a memory cell in a manner that will ensure correct transmission
of logic levels.
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Figure 3. The basic 6T CNTFET SRAM Cell
4. The Proposed CNTFET SRAM Cell
Authors in [20] proposed a 7T cell to reduce the activity factor α for reduction of dynamic power
while writing to a cell. The 7-transistor SRAM cell based on CNTFETs has been designed to
improve the read cycle and reduce dynamic power. The transistor level schematic of this cell
appears in Figure 3. It adds a transistor M7 in the feedback loop and a separate read line
‘ReadBit’ from the word line ‘WriteBit’ of the 6-transistor cell.
The four transistors M1, M2 and M3, M4 in the centre form two cross-coupled inverters INV1
and INV2. Due to the feedback structure, a low input value on the first inverter INV1 will
generate a high value on the second inverter INV2, which amplifies and stores the low value on
the second inverter INV2. Similarly, a high input value on the first inverter INV1 will generate a
low input value on the second inverter INV2, which feeds back the high input value onto the first
inverter INV1. Therefore, the two inverters INV1 and INV2 will store their current logical value,
whatever value that is. But in this circuit feedback connection is established through an extra
nMOS transistor M7. The circuit stores data at a node ‘Q’ and its complement at a node ‘Qbar’.
This circuit uses two separate transistors M5 and M6 to write and read data from memory cell. To
write data into cell ‘WriteSelect’ signal is used. To read data from the cell ‘ReadSelect’ signal is
used.
This proposed 7T CNTFET SRAM cell depends on cutting off the feed back connection between
the two inverters, INV1 and INV2, before a write operation. The feedback connection and
disconnection is performed through an extra nMOS transistor M7. During write operation M7 is
OFF and during read operation it is ON. The cell depends only on ‘WriteBit’ to perform a write
operation as shown in Figure 3.
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Figure 4. Proposed 7T CNTFET SRAM Cell
4.1. Read and Write Operation
Read operation starts by turning on a transistor M6 using a signal ‘ReadSelect’ and turning off the
transistor M5. During this operation feedback path is connected by turning on ‘WriteBar’ signal.
Then the stored data at a node ‘Q’ can be read at ‘ReadBit’. The read cycle is improved based on
two aspects of the cell operation namely the ability to pre-charge the read bit line ‘ReadBit’
irrespective of the activity of the write bit line ‘WriteBit’ and device sizing of the read zero path
with the pull-down transistor M3 of the second inverter made 8 times larger than the M6 to
provide a fast path to ground.
The write operation starts by turning M7 off to cut off the feedback connection, thereby allowing
for a fast transfer of the logic value from the write bit line ‘WriteBit’ into the memory cell.
‘WriteBit’ carries the input data, M5 is turned on by using a signal ‘WriteSelect’, while M6 is
kept off as shown in Figure 3. The 7T SRAM cell looks like two cascaded inverters, INV1
followed by INV2. M5 transistor transfers the data from ‘WriteBit’ to Q1 which drives INV1, M1
and M2, to develop ‘Qbar’. Similarly, ‘Qbar’ drives INV2, M3 and M4, to develop ‘Q’, the cell
data. Then, M5 is turned off and M7 is turned on to reconnect the feed back link between the two
inverters to stably store the new data. Dynamic power reduction would result from the reduced
switching activity during memory accesses. The ‘WriteBit’ line does not have to be pre-charged
in preparation for the read operation and a write operation affects only a single bit line of the cell
compared to both for the 6-transistor memory cell.
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5. RESULTS AND DISCUSSIONS
The 7T SRAM Cell based on CNTFET is designed at 32nm technology. Another 6T SRAM cell
at 32nm technology is also designed for comparison. This circuit is simulated in HSPICE using
Stanford CNTFET model at 32nm feature size with supply voltage VDD of 0.9V [21].
The following technology parameters are used for simulation of 6T and 7T SRAM cells using
CNTFET Technology [22-24]:
Physical channel length (L_channel) = 32.0nm
The length of doped CNT source/drain extension region (L_sd) = 32.0nm
Fermi level of the doped S/D tube (Efo) = 0.6 eV
The thickness of high-k top gate dielectric material (Tox) = 4.0nm
Chirality of tube (m, n) = (19, 0)
CNT Pitch = 10nm
Flatband voltage for n-CNTFET and p-CNTFET (Vfbn and Vfbp) = 0.0eV and 0.0eV
The mean free path in intrinsic CNT (Lceff ) = 200.0nm
The mean free path in p+/n+ doped CNT = 15.0nm
The work function of Source/Drain metal contact = 4.6eV
CNT work function = 4.5eV
The sizing of a CNFET is equivalent to adjusting the number of tubes. In this 7T CNTFET
SRAM Cell Circuit design we have chosen 3 tubes for M1, M2 and M5 transistors, 1 tube for M4
and M7 transistors, 8 tubes for M3 transistor and 6 tubes for M6 transistor for proper functionality
of the cell.
Read delay, defined as the time delay between 50% ‘ReadSelect’ activation to when the sense
amplifier has reached 90% of its full swing, should be measured at the worst case scenario.
Because of the asymmetry of the proposed 7T cell, the read path when Q =”1”, represents the
worst case read delay. The read cycle improvement is based on two aspects of the memory cell
operation. Firstly the ability to pre-charge ‘ReadBit’ line irrespective of the activity of the
‘WriteBit’ line and secondly device sizing of the read zero path containing transistors M3 and
M6, with the pull-down transistor M3 of the second inverter INV2 made 8 times larger to provide
a fast path to ground.
For a write operation, the write delay is defined as the time between the activation 50% of
‘WriteSelect’ to when ‘Q’ is 90% of its full swing. The write delay is approximately equals the
propagation delay of INV1 and INV2.
Because the write power consumption for a conventional 6T cell is independent of the input data,
the activity factor of discharging the bit line α is equal to 1, because for any input data one of the
bit lines is discharges. But this 7T CNTFET SRAM cell design uses only one bit line for writing
and the discharging of the bit line ‘Writedata’ depends on the stored data, so the activity factor α
is definitely less than 1. Dynamic power reduction would result from the reduced switching
activity during memory accesses. The ‘WriteBit’ line does not have to be pre-charged in
preparation for the read operation and a write operation affects only a single bit line of the cell
compared to both for the 6T CNTFET SRAM cell.
The 7T CNTFET SRAM circuit is successfully simulated using HSPICE and simulation
waveforms are measured using the HSPICE Cscope. The Simulation waveforms for successive
Writes and Reads are shown in Figure 4 and the simulation results of Dynamic Power and Read
Delay are tabulated in Table 1. This circuit is verified by successfully writing the data “1010101”
into the cell using ‘WriteSelect’ and ‘WriteBit’ signals, as shown by the waveform Q and
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correspond successfully reading of the data using the signal ‘ReadSelect’ as shown by the signal
‘ReadBit’ in Figure 4. The Dynamic Power and Read delay of 7T CNTFET SRAM Cell is
reduced by 37.2% and 38.6 % respectively compared to 6T CNTFET SRAM cell
.
Figure 5. 7T CNTFET SRAM Cell Simulation Results
Table 1. Simulation Results
Sl. No. Parameter 6T CNTFET
SRAM Cell
7T CNTFET
SRAM Cell
1 Dynamic Power (µW) 8.75 5.495
2 Read Delay (pS) 5.87 3.604
6. CONCLUSIONS
Carbon-based devices show promising features, so that they are considered as potential
candidates to replace silicon based MOSFETs in the future. In this paper a SRAM Cell is
designed using CNTFETs at 32nm Technology to reduce write-power dissipation and to reduce
the read delay. This 7T CNTFET SRAM Cell circuit uses extra one transistor compared to
conventional 6T SRAM Cell to reduce write-power. This circuit is designed and simulated in
9. International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.4, December 2011
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HSPICE using Stanford CNFET model at 32nm and simulated results are compared with the
simulated results of 6T CNTFET SRAM cell. The Simulation results are tabulated in table 1. The
results shows that the Dynamic Power and Read delay of 7T CNTFET SRAM Cell is reduced by
37.2% and 38.6 % respectively compared to 6T CNTFET SRAM cell. The results proved that this
circuit reduces write-power and read-delay to the significant effect. This proposed cell can be
used in design of CNTFET based low-power SRAM Memories.
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Author
Mr. S Rajendra Prasad received his BTech in Electronics and Communication
Engineering from SK University, AP and MTech from SV University, Tirupati, A.P.
Presently he is pursuing Ph.D from JNTU, Hyderabad. He has Published 8 Research Papers
in International/National Jurnals/Conferences. His areas of interest include Low-Power
SRAM Design, Low-Power High-performance Digital Circuit Design, VLSI Circuits
Design based on CNTFETs, Embedded Systems, Microprocessors and Microcontrollers.
Dr. B K Madhavi received Ph.D from JNTU, Hyderabad. She completed ME from
BITS-PILANI in the specialization of ‘Microelectronics’. She published 26 research
papers in various National and International Journals and Conferences. Presently she is
guiding 10 PhD Students and guided several BTech and MTech Projects. She is also
reviewed research papers for IETE. She participated in several workshops, summer and
winter schools, National, International conferences and also organized several
National level workshops and seminars etc. Her research interest include
Microelectronics (VLSI Design, Low Power VLSI, Mixed Signal Processing), Wireless communications.
Dr. K Lal Kishore is a Senior Professor in Electronics and Communications Engg.
Department of JNTUH University, Hyderabad. He has more than 130 Research
Publications to his credit so far. He has produced 10 Ph.Ds and many more Research
Scholars are working under his Guidance. He has won First Bapu Seetharam Memorial
Award and S.V. Aiya Memorial Award from IETE for Research Contribution, Best
Teacher Award from Govt. of A.P and many more National Level Awards. He has over 33
years of Experience in Teaching and Research. He has implemented number of Research
Projects and developed many Laboratories in the Department. He has Post-Graduate and Ph.D Degrees
from Indian Institute of Science (I.I.Sc) Bangalore. He wrote Six Text Books, on Electronic Devices,
Circuit Analysis, Linear I.C. Applications, Electronic Measurements and Instrumentation and VLSI Design.
He had held number of administrative positions in the JNT University, Hyderabd including that of Rector,
Registrar, Director, Academic and Planning, Director School of Information Technology, Principal etc.