IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
A REVIEW OF THE 0.09 µm STANDARD FULL ADDERSVLSICS Design
This paper presents power analysis of the seven full adder cells [6] reported as having a low PDP (Power Delay Product), by means of speed, power consumption and area. These full adders were designed upon various logic styles to derive the sum and carry outputs. The existed standard full adders and the proposed full adders [6] are designed and showed the better result comparison. This paper describes how the proposed full adders [6] are better in contrast to the standard full adders. And mentioned how the standard full adders are not giving faithful results . All these full adders designed using TDK 90 nm Technology and simulated using mentor graphics EDA tool with BSIMv3 (model 49). And the layouts of all these full adders designed in Icstation of Mentor Graphics and presented their areas. The total results of prelayout and postlayout simulation are tabulated.
HIGH SPEED MULTIPLE VALUED LOGIC FULL ADDER USING CARBON NANO TUBE FIELD EFFE...VLSICS Design
High speed Full-Adder (FA) module is a critical element in designing high performance arithmetic circuits. In this paper, we propose a new high speed multiple-valued logic FA module. The proposed FA is constructed by 14 transistors and 3 capacitors, using carbon nano-tube field effect transistor (CNFET) technology. Furthermore, our proposed technique has been examined in different voltages (i.e., 0.65v and 0.9v). The observed results reveal power consumption and power delay product (PDP) improvements compared to existing FA counterparts.
Design a Low Power High Speed Full Adder Using AVL Technique Based on CMOS Na...IOSR Journals
Abstract: Power and delay optimization is a very crucial issue in low voltage applications. In this paper, we present a design of Full Adder circuit using AVL techniques for low power operation. The approach for the design is based on XOR/XNOR & Transmission gate for single bit as hybrid design .By using this approach Full Adder is being designed using 12 transistors. We can reduce the value of total power dissipation by applying the AVLG (adaptive voltage level at ground) technology in which the ground potential is raised and AVLS (adaptive voltage level at supply) in which supply potential is increased. The main aim of the design is to investigate the power, Propagation Delay and Power delay Product for low voltage Full Adder for the proposed design style. The simulation results show that there is a significant reduction in power consumption for this proposed cell with the AVL technique. The circuit is designed using 65 nanometer CMOS technology and simulated using MicroWind and DSCH Ver. 3.1 Keywords: Full Adder, AVL Techniques, Low Power, VLSI, High Performance
Addition is a fundamental arithmetic operation that is broadly used in many VLSI systems, such as application-specific digital signal processing (DSP) architectures and microprocessors. This addition module is also the core of other arithmetic operations such as subtraction, multiplication, division and address generation. The prime objective of this project is to design a full-adder having low-power consumption and low propagation delay which may result in the efficient implementation of modern digital systems. This model is referred as “hybrid” because of the combination of two different design logic styles namely CMOS logic and pass transistor logic. Performance parameters such as power, delay and hence energy were compared with the existing designs such as complementary CMOS logic full adder. In the existing hybrid systems, over 28 transistors were used. While the optimized hybrid full adder circuit reduces this count to 8 transistors, it still obtains better energy efficiency. Further the proper working of proposed full adder is verified by applying it in a Ripple carry Adder circuit.
Welcome to International Journal of Engineering Research and Development (IJERD)IJERD Editor
call for paper 2012, hard copy of journal, research paper publishing, where to publish research paper,
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals
Design and Analysis of New Modified Feedthrough Logic (MFTL) Circuits Using C...IJERA Editor
It is a challenging task for a VLSI design engineer to develop low power VLSI circuits, without sacrificing its performance. Feedthrough Logic (FTL) is a new technology which could be considered better than the existing technologies for improving circuit efficiency. Modified Feedthrough Logic (MFTL), offers a better power factor than the FTL logic structures, and also shows an improvement in the speed factor. But the scenario again changes when the design extends to nano scales of device dimension, where many factors which were neglected otherwise need to be given more importance. To avoid or minimize problems like hot carrier effects, electro migration, drain induced barrier lowering and other issues that becomes prominent in nano scale MOSFET‟s, Carbon Nanotube Field Effect Transistor (CNTFET) is considered to be a promising candidate in future integrated circuits. Hence this work extends the advantages of MFTL logic into nano level by incorporating CNTFETs in place of MOSFETs. The modifications have been implemented using CNTFETs of 16nm technology from HSPICE library on a 10 chain inverter stage, an 8 bit RCA and a Vedic multiplier and performance factors like PDP and ADP are compared to that of the conventional MOSFET circuits.
THE INFLUENCE OF SILICON AREA ON THE PERFORMANCE OF THE FULL ADDERSIJCSEA Journal
Recently, the influence of the silicon area on the delay time, power dissipation and the leakage current is a
crucial issue when designing a full adder circuit. In this paper, an efficient full adder design referred to as
10-T is proposed. The new design utilized the use of XNOR gates instead of XOR in the full adder
implementation and, as a result, the delay time and power dissipation are significantly decreased. In
order, to show the influence of the silicon area and transistors count on the performance of the 10-T full
adder, it is compared to the most recent full adders : 28-T , 20T , 16-T , and 14 –T. Simulation result
based on HSPICE simulator using 16nm technology showed that the 10-T XNOR full adder significantly
improved the performance of full adder through decreasing the transistors count. In addition using the
multi-supply voltage of 130nm technology, in this case the proposed full adder demonstrated is the best
power consumption in comparison to other designs
A REVIEW OF THE 0.09 µm STANDARD FULL ADDERSVLSICS Design
This paper presents power analysis of the seven full adder cells [6] reported as having a low PDP (Power Delay Product), by means of speed, power consumption and area. These full adders were designed upon various logic styles to derive the sum and carry outputs. The existed standard full adders and the proposed full adders [6] are designed and showed the better result comparison. This paper describes how the proposed full adders [6] are better in contrast to the standard full adders. And mentioned how the standard full adders are not giving faithful results . All these full adders designed using TDK 90 nm Technology and simulated using mentor graphics EDA tool with BSIMv3 (model 49). And the layouts of all these full adders designed in Icstation of Mentor Graphics and presented their areas. The total results of prelayout and postlayout simulation are tabulated.
HIGH SPEED MULTIPLE VALUED LOGIC FULL ADDER USING CARBON NANO TUBE FIELD EFFE...VLSICS Design
High speed Full-Adder (FA) module is a critical element in designing high performance arithmetic circuits. In this paper, we propose a new high speed multiple-valued logic FA module. The proposed FA is constructed by 14 transistors and 3 capacitors, using carbon nano-tube field effect transistor (CNFET) technology. Furthermore, our proposed technique has been examined in different voltages (i.e., 0.65v and 0.9v). The observed results reveal power consumption and power delay product (PDP) improvements compared to existing FA counterparts.
Design a Low Power High Speed Full Adder Using AVL Technique Based on CMOS Na...IOSR Journals
Abstract: Power and delay optimization is a very crucial issue in low voltage applications. In this paper, we present a design of Full Adder circuit using AVL techniques for low power operation. The approach for the design is based on XOR/XNOR & Transmission gate for single bit as hybrid design .By using this approach Full Adder is being designed using 12 transistors. We can reduce the value of total power dissipation by applying the AVLG (adaptive voltage level at ground) technology in which the ground potential is raised and AVLS (adaptive voltage level at supply) in which supply potential is increased. The main aim of the design is to investigate the power, Propagation Delay and Power delay Product for low voltage Full Adder for the proposed design style. The simulation results show that there is a significant reduction in power consumption for this proposed cell with the AVL technique. The circuit is designed using 65 nanometer CMOS technology and simulated using MicroWind and DSCH Ver. 3.1 Keywords: Full Adder, AVL Techniques, Low Power, VLSI, High Performance
Addition is a fundamental arithmetic operation that is broadly used in many VLSI systems, such as application-specific digital signal processing (DSP) architectures and microprocessors. This addition module is also the core of other arithmetic operations such as subtraction, multiplication, division and address generation. The prime objective of this project is to design a full-adder having low-power consumption and low propagation delay which may result in the efficient implementation of modern digital systems. This model is referred as “hybrid” because of the combination of two different design logic styles namely CMOS logic and pass transistor logic. Performance parameters such as power, delay and hence energy were compared with the existing designs such as complementary CMOS logic full adder. In the existing hybrid systems, over 28 transistors were used. While the optimized hybrid full adder circuit reduces this count to 8 transistors, it still obtains better energy efficiency. Further the proper working of proposed full adder is verified by applying it in a Ripple carry Adder circuit.
Welcome to International Journal of Engineering Research and Development (IJERD)IJERD Editor
call for paper 2012, hard copy of journal, research paper publishing, where to publish research paper,
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals
Design and Analysis of New Modified Feedthrough Logic (MFTL) Circuits Using C...IJERA Editor
It is a challenging task for a VLSI design engineer to develop low power VLSI circuits, without sacrificing its performance. Feedthrough Logic (FTL) is a new technology which could be considered better than the existing technologies for improving circuit efficiency. Modified Feedthrough Logic (MFTL), offers a better power factor than the FTL logic structures, and also shows an improvement in the speed factor. But the scenario again changes when the design extends to nano scales of device dimension, where many factors which were neglected otherwise need to be given more importance. To avoid or minimize problems like hot carrier effects, electro migration, drain induced barrier lowering and other issues that becomes prominent in nano scale MOSFET‟s, Carbon Nanotube Field Effect Transistor (CNTFET) is considered to be a promising candidate in future integrated circuits. Hence this work extends the advantages of MFTL logic into nano level by incorporating CNTFETs in place of MOSFETs. The modifications have been implemented using CNTFETs of 16nm technology from HSPICE library on a 10 chain inverter stage, an 8 bit RCA and a Vedic multiplier and performance factors like PDP and ADP are compared to that of the conventional MOSFET circuits.
THE INFLUENCE OF SILICON AREA ON THE PERFORMANCE OF THE FULL ADDERSIJCSEA Journal
Recently, the influence of the silicon area on the delay time, power dissipation and the leakage current is a
crucial issue when designing a full adder circuit. In this paper, an efficient full adder design referred to as
10-T is proposed. The new design utilized the use of XNOR gates instead of XOR in the full adder
implementation and, as a result, the delay time and power dissipation are significantly decreased. In
order, to show the influence of the silicon area and transistors count on the performance of the 10-T full
adder, it is compared to the most recent full adders : 28-T , 20T , 16-T , and 14 –T. Simulation result
based on HSPICE simulator using 16nm technology showed that the 10-T XNOR full adder significantly
improved the performance of full adder through decreasing the transistors count. In addition using the
multi-supply voltage of 130nm technology, in this case the proposed full adder demonstrated is the best
power consumption in comparison to other designs
The main goal of this paper to produce new low power solutions for very large scale
integration(VLSI).The main focus of this research on the power consumption, which is showing an
ever-increasing growth with scaling down of the technologies. The full adder is the most important
component of any digital system applications. To limit the power dissipation, this full adder is
designed with adiabatic technique PFAL and it compare with partial adiabatic technique ECRL.
These analysis have done on TANNER simulator V 7 technology. The power is reduced up to 70-
80% as compared to other methods.
Mathematical Modelling of Semiconductor Devices and Circuits: A Review
Sanjay Kumar Roy, Manwinder Singh, Kamal Kumar Sharma
and Brahmadeo Prasad Singh
Implementation of Full Adder Cell Using High Performance CMOS Technologyijsrd.com
This paper proposed design and implementation of full adder cell which is efficient in terms of both speed and energy consumption which becomes even more significant as the world length of the adder increases. We are introducing adders for low power imprecise applications. In this we propose a full adder design having low complexity, higher computing speed, lower energy consumption, and lower operating voltage. We will explain how to realize a general full adder circuit based on transistor using CMOS technology. The performance of the proposed full adder is evaluated by the comparison of the simulation result. In this system, not signals are generated internally that control the selection of the output multiplexers. Instead, the input signal, exhibiting a full voltage swing and no extra delay, is used to drive the multiplexers, reducing the overall propagation delays. The capacitive load for the input has been reduced, as it is connected only to some transistor gates and some drain or source terminals. The design a full adder having low complexity, higher computing speed, lower energy consumption, and lower operating voltage. Full Adder models to make it understandable for designer. We are giving high throughput with less complex system by showing synthesizable and simulated results.
CNFET BASED BASIC GATES AND A NOVEL FULLADDER CELLVLSICS Design
In this paper two novel high performance designs for AND and OR basic gates and a novel Full-Adder Cell are presented. These designs are based on carbon nanotube technology. In order to compare the proposed designs with previous ones both MOSFET based and CNFET based circuits are selected. By the way the proposed designs have better performance in comparison with previous designs in terms of speed, power consumption and power-delay product (PDP).
Compact low power high slew-rate cmos buffer amplifier with power gating tech...VLSICS Design
A qualitative analysis of different parameters such as Phase noise, Slew rate and tranconductance by using
power gating reduction technique is presented. The circuit achieves the large driving capability by
employing simple comparators to sense the transients of the input to turn on the output stages, which are
statically off in the stable state. The effect of the different number of transistors and their topologies on the
phase noise and Slew rate is analyzed. Good agreement between qualitative and quantitative measurements
is observed. Scope of reducing of Noise and avoidance of Leakage due to various sources is discussed.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Power Optimized Multiplexer Based 1 Bit Full Adder Cell Using .18 µm CMOS Tec...iosrjce
In this paper, a multiplexer based 1 bit full adder cell using 10 transistors is reported ( MBFA-10T).
In addition to higher speed , low power and reduced transition activity, this design has no direct power supply
connections, results in reduced consumption of short circuit current. The design was implemented using
Cadence Virtuoso tools in 180-nm CMOS technology. Performance parameters like layout area, power delay
product(PDP), transistor count, average power and delay were compared with the existing logic design styles
like static CMOS logic, pass transistor logic( TFA-16T, 14 T) , transmission gate logic and so on. The intensive
simulation shows improved operation speeds and power savings compare to the conventional design styles.
For 1.8-V supply at 180-nm CMOS technology, the average power consumption (3.9230μW) ,delay (196.8ps)
,the power delay product (PDP) (0.772fJ) and lay out area(175.79 µm2) was found to be extremely low, when
compared with other potential design styles.
Phase-Shifted Full-Bridge Zero Voltage Switching DC-DC Converter Design with ...IJECEIAES
Design of phase-shifted full bridge zero voltage switching DC-DC converter has been very challenging due to circuit parasitic effect on the system dynamics. This paper presents steady-state analysis and iterative approach for the systemic design of phase-shifted full bridge DC-DC converter with improved dynamic performance and satisfactory operational requirement in terms of zero-voltage switching range, operating switching frequency and switching resonance. A 3 kW DC-DC converter is designed using the iterative design approach and the system dynamics performance was investigated in the MATLAB/Simulink environment. The converter zerovoltage switching simulation results were satisfactory with 90% efficiency under full load condition.
Design and Implementation of Submicron Level 10T Full Adder in ALU Using Cell...IJERA Editor
As technology scales into the nanometer regime leakage current, active power, delay and area are becoming important metric for the analysis and design of complex circuits. The main concern in mobile and battery based systems are leakage current and power dissipation. A transistor resizing approach for 10 transistor single bit full adder cells is used to determine optimal sleep transistor size which reduces power dissipation and leakage current. A submicron level 10-transistor single bit full adder cell is considered to achieve low leakage current, reduced power dissipation and high speed. In this paper initially 10T full adder cell is designed with submicron technique and later this is employed to design an ALU adder unit. The modified ALU is simulated and synthesized successfully on cadence 180nm technology.
DESIGN OF A HIGH PRECISION, WIDE RANGED ANALOG CLOCK GENERATOR WITH FIELD PRO...VLSICS Design
This paper presents a circuit of a high-precision, wide ranged, analog clock generator with on-chip programmability feature using Floating-gate transistors. The programmable oscillator can attain a continuous range of time-periods lying in the programming precision range of Floating Gates. The circuit consists of two sub circuits: Current Generator circuit and Wave Generator circuit. The current of current generator circuit is programmable and mirrored to the wave generator to generate the desired square wave. The topology is well suited to applications like clocking high performance ADCs and DACs as well as used as the internal clock in structured analog CMOS designs. A simulation model of the circuit was built in T-Spice, 0.35µm CMOS process. The circuit results in finely tuned clock with programmability precision of about 13bit [1]. Simulation results show high amount of temperature insensitivity (0.507ns/°C) for a large range of thermal conditions. The proposed circuit can compensate any change in temperature. The circuit design can be operated at low supply voltage i.e., 1v.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
10 Insightful Quotes On Designing A Better Customer ExperienceYuan Wang
In an ever-changing landscape of one digital disruption after another, companies and organisations are looking for new ways to understand their target markets and engage them better. Increasingly they invest in user experience (UX) and customer experience design (CX) capabilities by working with a specialist UX agency or developing their own UX lab. Some UX practitioners are touting leaner and faster ways of developing customer-centric products and services, via methodologies such as guerilla research, rapid prototyping and Agile UX. Others seek innovation and fulfilment by spending more time in research, being more inclusive, and designing for social goods.
Experience is more than just an interface. It is a relationship, as well as a series of touch points between your brand and your customer. Here are our top 10 highlights and takeaways from the recent UX Australia conference to help you transform your customer experience design.
For full article, continue reading at https://yump.com.au/10-ways-supercharge-customer-experience-design/
http://inarocket.com
Learn BEM fundamentals as fast as possible. What is BEM (Block, element, modifier), BEM syntax, how it works with a real example, etc.
The main goal of this paper to produce new low power solutions for very large scale
integration(VLSI).The main focus of this research on the power consumption, which is showing an
ever-increasing growth with scaling down of the technologies. The full adder is the most important
component of any digital system applications. To limit the power dissipation, this full adder is
designed with adiabatic technique PFAL and it compare with partial adiabatic technique ECRL.
These analysis have done on TANNER simulator V 7 technology. The power is reduced up to 70-
80% as compared to other methods.
Mathematical Modelling of Semiconductor Devices and Circuits: A Review
Sanjay Kumar Roy, Manwinder Singh, Kamal Kumar Sharma
and Brahmadeo Prasad Singh
Implementation of Full Adder Cell Using High Performance CMOS Technologyijsrd.com
This paper proposed design and implementation of full adder cell which is efficient in terms of both speed and energy consumption which becomes even more significant as the world length of the adder increases. We are introducing adders for low power imprecise applications. In this we propose a full adder design having low complexity, higher computing speed, lower energy consumption, and lower operating voltage. We will explain how to realize a general full adder circuit based on transistor using CMOS technology. The performance of the proposed full adder is evaluated by the comparison of the simulation result. In this system, not signals are generated internally that control the selection of the output multiplexers. Instead, the input signal, exhibiting a full voltage swing and no extra delay, is used to drive the multiplexers, reducing the overall propagation delays. The capacitive load for the input has been reduced, as it is connected only to some transistor gates and some drain or source terminals. The design a full adder having low complexity, higher computing speed, lower energy consumption, and lower operating voltage. Full Adder models to make it understandable for designer. We are giving high throughput with less complex system by showing synthesizable and simulated results.
CNFET BASED BASIC GATES AND A NOVEL FULLADDER CELLVLSICS Design
In this paper two novel high performance designs for AND and OR basic gates and a novel Full-Adder Cell are presented. These designs are based on carbon nanotube technology. In order to compare the proposed designs with previous ones both MOSFET based and CNFET based circuits are selected. By the way the proposed designs have better performance in comparison with previous designs in terms of speed, power consumption and power-delay product (PDP).
Compact low power high slew-rate cmos buffer amplifier with power gating tech...VLSICS Design
A qualitative analysis of different parameters such as Phase noise, Slew rate and tranconductance by using
power gating reduction technique is presented. The circuit achieves the large driving capability by
employing simple comparators to sense the transients of the input to turn on the output stages, which are
statically off in the stable state. The effect of the different number of transistors and their topologies on the
phase noise and Slew rate is analyzed. Good agreement between qualitative and quantitative measurements
is observed. Scope of reducing of Noise and avoidance of Leakage due to various sources is discussed.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Power Optimized Multiplexer Based 1 Bit Full Adder Cell Using .18 µm CMOS Tec...iosrjce
In this paper, a multiplexer based 1 bit full adder cell using 10 transistors is reported ( MBFA-10T).
In addition to higher speed , low power and reduced transition activity, this design has no direct power supply
connections, results in reduced consumption of short circuit current. The design was implemented using
Cadence Virtuoso tools in 180-nm CMOS technology. Performance parameters like layout area, power delay
product(PDP), transistor count, average power and delay were compared with the existing logic design styles
like static CMOS logic, pass transistor logic( TFA-16T, 14 T) , transmission gate logic and so on. The intensive
simulation shows improved operation speeds and power savings compare to the conventional design styles.
For 1.8-V supply at 180-nm CMOS technology, the average power consumption (3.9230μW) ,delay (196.8ps)
,the power delay product (PDP) (0.772fJ) and lay out area(175.79 µm2) was found to be extremely low, when
compared with other potential design styles.
Phase-Shifted Full-Bridge Zero Voltage Switching DC-DC Converter Design with ...IJECEIAES
Design of phase-shifted full bridge zero voltage switching DC-DC converter has been very challenging due to circuit parasitic effect on the system dynamics. This paper presents steady-state analysis and iterative approach for the systemic design of phase-shifted full bridge DC-DC converter with improved dynamic performance and satisfactory operational requirement in terms of zero-voltage switching range, operating switching frequency and switching resonance. A 3 kW DC-DC converter is designed using the iterative design approach and the system dynamics performance was investigated in the MATLAB/Simulink environment. The converter zerovoltage switching simulation results were satisfactory with 90% efficiency under full load condition.
Design and Implementation of Submicron Level 10T Full Adder in ALU Using Cell...IJERA Editor
As technology scales into the nanometer regime leakage current, active power, delay and area are becoming important metric for the analysis and design of complex circuits. The main concern in mobile and battery based systems are leakage current and power dissipation. A transistor resizing approach for 10 transistor single bit full adder cells is used to determine optimal sleep transistor size which reduces power dissipation and leakage current. A submicron level 10-transistor single bit full adder cell is considered to achieve low leakage current, reduced power dissipation and high speed. In this paper initially 10T full adder cell is designed with submicron technique and later this is employed to design an ALU adder unit. The modified ALU is simulated and synthesized successfully on cadence 180nm technology.
DESIGN OF A HIGH PRECISION, WIDE RANGED ANALOG CLOCK GENERATOR WITH FIELD PRO...VLSICS Design
This paper presents a circuit of a high-precision, wide ranged, analog clock generator with on-chip programmability feature using Floating-gate transistors. The programmable oscillator can attain a continuous range of time-periods lying in the programming precision range of Floating Gates. The circuit consists of two sub circuits: Current Generator circuit and Wave Generator circuit. The current of current generator circuit is programmable and mirrored to the wave generator to generate the desired square wave. The topology is well suited to applications like clocking high performance ADCs and DACs as well as used as the internal clock in structured analog CMOS designs. A simulation model of the circuit was built in T-Spice, 0.35µm CMOS process. The circuit results in finely tuned clock with programmability precision of about 13bit [1]. Simulation results show high amount of temperature insensitivity (0.507ns/°C) for a large range of thermal conditions. The proposed circuit can compensate any change in temperature. The circuit design can be operated at low supply voltage i.e., 1v.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
10 Insightful Quotes On Designing A Better Customer ExperienceYuan Wang
In an ever-changing landscape of one digital disruption after another, companies and organisations are looking for new ways to understand their target markets and engage them better. Increasingly they invest in user experience (UX) and customer experience design (CX) capabilities by working with a specialist UX agency or developing their own UX lab. Some UX practitioners are touting leaner and faster ways of developing customer-centric products and services, via methodologies such as guerilla research, rapid prototyping and Agile UX. Others seek innovation and fulfilment by spending more time in research, being more inclusive, and designing for social goods.
Experience is more than just an interface. It is a relationship, as well as a series of touch points between your brand and your customer. Here are our top 10 highlights and takeaways from the recent UX Australia conference to help you transform your customer experience design.
For full article, continue reading at https://yump.com.au/10-ways-supercharge-customer-experience-design/
http://inarocket.com
Learn BEM fundamentals as fast as possible. What is BEM (Block, element, modifier), BEM syntax, how it works with a real example, etc.
How to Build a Dynamic Social Media PlanPost Planner
Stop guessing and wasting your time on networks and strategies that don’t work!
Join Rebekah Radice and Katie Lance to learn how to optimize your social networks, the best kept secrets for hot content, top time management tools, and much more!
Watch the replay here: bit.ly/socialmedia-plan
Content personalisation is becoming more prevalent. A site, it's content and/or it's products, change dynamically according to the specific needs of the user. SEO needs to ensure we do not fall behind of this trend.
Lightning Talk #9: How UX and Data Storytelling Can Shape Policy by Mika Aldabaux singapore
How can we take UX and Data Storytelling out of the tech context and use them to change the way government behaves?
Showcasing the truth is the highest goal of data storytelling. Because the design of a chart can affect the interpretation of data in a major way, one must wield visual tools with care and deliberation. Using quantitative facts to evoke an emotional response is best achieved with the combination of UX and data storytelling.
Succession “Losers”: What Happens to Executives Passed Over for the CEO Job?
By David F. Larcker, Stephen A. Miles, and Brian Tayan
Stanford Closer Look Series
Overview:
Shareholders pay considerable attention to the choice of executive selected as the new CEO whenever a change in leadership takes place. However, without an inside look at the leading candidates to assume the CEO role, it is difficult for shareholders to tell whether the board has made the correct choice. In this Closer Look, we examine CEO succession events among the largest 100 companies over a ten-year period to determine what happens to the executives who were not selected (i.e., the “succession losers”) and how they perform relative to those who were selected (the “succession winners”).
We ask:
• Are the executives selected for the CEO role really better than those passed over?
• What are the implications for understanding the labor market for executive talent?
• Are differences in performance due to operating conditions or quality of available talent?
• Are boards better at identifying CEO talent than other research generally suggests?
DESIGN AND PERFORMANCE ANALYSIS OF HYBRID ADDERS FOR HIGH SPEED ARITHMETIC CI...VLSICS Design
Adder cells using Gate Diffusion Technique (GDI) & PTL-GDI technique are described in this paper. GDI technique allows reducing power consumption, propagation delay and low PDP (power delay product) whereas Pass Transistor Logic (PTL) reduces the count of transistors used to make different logic gates, by eliminating redundant transistors. Performance comparison with various Hybrid Adder is been presented. In this paper, we propose two new designs based on GDI & PTL techniques, which is found to be much more power efficient in comparison with existing design technique. Only 10 transistors are used to implement the SUM & CARRY function for both the designs. The SUM and CARRY cell are implemented in a cascaded way i.e. firstly the XOR cell is implemented and then using XOR as input SUM as well as CARRY cell is implemented. For Proposed GDI adder the SUM as well as CARRY cell is designed using GDI technique. On the other hand in Proposed PTL-GDI adder the SUM cell is constructed using PTL technique and the CARRY cell is designed using GDI technique. The advantages of both the designs are discussed. The significance of these designs is substantiated by the simulation results obtained from Cadence Virtuoso 180nm environment.
Comparative Performance Analysis of Low Power Full Adder Design in Different ...ijcisjournal
This paper gives the comparison of performance of full adder design in terms of area, power and delay in
different logic styles. Full adder design achieves low power using the Transmission Gate logic compared to
all other topologies such as Basic CMOS, Pass Transistor and GDI techniques but it make use of more
number of transistors compared to GDI. GDI occupies less area compared to all other logic design styles.
This paper presents the simulated outcome using Tanner tools and also H-Spice tool which shows power
and speed comparison of different full adder designs. All simulations have been performed in 90nm, 45nm
and 22nm scaling parameters using Predictive Technology Models in H-Spice tool.
THE INFLUENCE OF SILICON AREA ON THE PERFORMANCE OF THE FULL ADDERSIJCSEA Journal
Recently, the influence of the silicon area on the delay time, power dissipation and the leakage current is a
crucial issue when designing a full adder circuit. In this paper, an efficient full adder design referred to as
10-T is proposed. The new design utilized the use of XNOR gates instead of XOR in the full adder
implementation and, as a result, the delay time and power dissipation are significantly decreased. In
order, to show the influence of the silicon area and transistors count on the performance of the 10-T full
adder, it is compared to the most recent full adders : 28-T , 20T , 16-T , and 14 –T. Simulation result
based on HSPICE simulator using 16nm technology showed that the 10-T XNOR full adder significantly
improved the performance of full adder through decreasing the transistors count. In addition using the
multi-supply voltage of 130nm technology, in this case the proposed full adder demonstrated is the best
power consumption in comparison to other designs
THE INFLUENCE OF SILICON AREA ON THE PERFORMANCE OF THE FULL ADDERSIJCSEA Journal
Recently, the influence of the silicon area on the delay time, power dissipation and the leakage current is a
crucial issue when designing a full adder circuit. In this paper, an efficient full adder design referred to as
10-T is proposed. The new design utilized the use of XNOR gates instead of XOR in the full adder
implementation and, as a result, the delay time and power dissipation are significantly decreased. In
order, to show the influence of the silicon area and transistors count on the performance of the 10-T full
adder, it is compared to the most recent full adders : 28-T , 20T , 16-T , and 14 –T. Simulation result
based on HSPICE simulator using 16nm technology showed that the 10-T XNOR full adder significantly
improved the performance of full adder through decreasing the transistors count. In addition using the
multi-supply voltage of 130nm technology, in this case the proposed full adder demonstrated is the best
power consumption in comparison to other designs.
A comparative study of full adder using static cmos logic styleeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Implementation of Area Effective Carry Select AddersKumar Goud
Abstract: In the design of Integrated circuit area occupancy plays a vital role because of increasing the necessity of portable systems. Carry Select Adder (CSLA) is a fast adder used in data processing processors for performing fast arithmetic functions. From the structure of the CSLA, the scope is reducing the area of CSLA based on the efficient gate-level modification. In this paper 16 bit, 32 bit, 64 bit and 128 bit Regular Linear CSLA, Modified Linear CSLA, Regular Square-root CSLA (SQRT CSLA) and Modified SQRT CSLA architectures have been developed and compared. However, the Regular CSLA is still area-consuming due to the dual Ripple-Carry Adder (RCA) structure. For reducing area, the CSLA can be implemented by using a single RCA and an add-one circuit instead of using dual RCA. Comparing the Regular Linear CSLA with Regular SQRT CSLA, the Regular SQRT CSLA has reduced area as well as comparing the Modified Linear CSLA with Modified SQRT CSLA; the Modified SQRT CSLA has reduced area. The results and analysis show that the Modified Linear CSLA and Modified SQRT CSLA provide better outcomes than the Regular Linear CSLA and Regular SQRT CSLA respectively. This project was aimed for implementing high performance optimized FPGA architecture. Modelsim 10.0c is used for simulating the CSLA and synthesized using Xilinx PlanAhead13.4. Then the implementation is done in Virtex5 FPGA Kit.
Keywords: Field Programmable Gate Array (FPGA), efficient, Carry Select Adder (CSLA), Square-root CSLA (SQRTCSLA).
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Efficient implementation of 2 bit magnitude comparator using ptIJARIIT
Nowadays the requirements of low power electronics play a vital role in various fields. In this paper we introducing
the novel comparator is one of the fundamental units in VLSI design and also it can be employed in various applications like
Digital Signal Processors (DSP) and Data Processing, Communication Systems, Medical Electronics etc., Comparator is
involved to the most basic arithmetic operation of compression between any two variables either it maybe an equal one or
unequal. In early days, the comparator techniques used to implement energy optimization in low power circuits but the static
power dissipation need to improve the comparator using logic styles. In this paper, the 2-bit comparator has been designed by
using pass transistor logic (PTL). PTL provide good performance by reducing transistor count as well as power because PTL
logic helps in reducing the transistor count compared to other logic operation. The design was implemented in Cadence
virtuoso TMSC 180nm CMOS technology and it’s obtaining the total power dissipation 1.394μw. PTL logic is used to reduce
both transistor count and power dissipation in magnitude comparator is used to improve the good quality performance of this circuit.
This paper presents a recursive designing approach for high energy efficient carry select adder (CSA). Nowadays, the portable equipment’s like mobile phones and laptops have higher demands in the market. So, the designers must focus greater attention while designing such devices. Which means that have the devices must have lesser power consumption, low cost and have a better performance. The customers mainly focus on the equipment’s which have lesser power consumption, low cost and better performance. As we all know that the adders are the basic building block of microprocessors. The performance of the adders greatly influences the performance of those processors. The carry select adder is most suitable among other adders which have fast addition operation at low cost. The carry select adder (CSA) consists of chain full adders (FAs) and multiplexers. Here a carry select adder is designed with four FAs and four multiplexers. The proposed structure is assessed by the power consumption of the carry select adder using a 32-nm static CMOS technology for a wide range of supply voltages. The simulation results are obtained using Tanner EDA which reveals that the carry select adder has low power consumption.
Efficient implementation of full adder for power analysis in cmos technologyIJARIIT
In recent days, the real-time application and fast arithmetic operations require highly efficient arithmetic hardware
architecture to improve the system performances. The adder plays a vital role in digital circuits, the earlier hardware
architecture using conventional CMOS and transmission logic gate based full adder design. Moreover, the techniques using
more number of transistors and consume larger power and delay so we proposed the techniques pass-transistor logic and
transmission gate based hybrid pass logic. The hybrid technique is used to reduce the number of the transistor, so the delay
and power consumption will be reduced when compared with the earlier techniques. The proposed technique design was
implemented using 16 transistors in 180nm CMOS technology and it consumes 8.2075nW power and the delay reduced to
5.0146ns.
Addition is a fundamental arithmetic operation and acts as a building block for synthesizing of all other operations. A high-performance adder is one of the key components in the design of Application Specific Integrated Circuits (ASIC). In this work, three low power full adders are designed with full swing AND, OR and XOR gates to reduce threshold voltage problem which is commonly encountered in Gate Diffusion Input (GDI) logic. This problem usually does not allow the full adder circuits to operate without additional inverters. However, the three full adders are successfully realized using full swing gates with the significant improvement in their performance. The performance of the proposed design is simulated through SPICE simulations using 45 nm technology models.
In most of the modern day computers adder is an essential circuit. The primary requirement of adder is that, it is fast and efficient in terms of power consumption and chip area. Here we design a CSA (Carry Save Adder) using domino logic. CSA can be designed using two full adder circuits. The circuit is implemented in domino logic by switching PMOS to off state and NMOS to on state and adding a static inverter at the output. Domino Logic with CSA gives better result in terms of power dissipation, area, speed and reduction in transistors count required. To design an efficient integrated circuit in terms of area, power and speed has become a challenging task in modern VLSI design field .Performance analysis was carried out between multiplier using Carry Propagate Adder(CPA) and by using Carry Save Adder.
Implementation of pull up pull-down network for energy optimization in full a...IJARIIT
Nowadays the requirements of energy optimized low power circuits in higher-end applications such as
communication, IoT, biomedical systems etc., there are several techniques used to implement energy optimization in low power
circuits but the static power dissipation need to improve such kind of circuits. The conventional topology has been
implemented in basic logical gates but the delay and power much higher in each individual cell. Now we proposed an
unbalanced pull-up and pull-down network in full adder circuit using symbols. These techniques were employed to reduce the
static power dissipation and switching delay in each individual cell. The design was implemented in Cadence virtuoso TMSC
180nm CMOS technology and it’s obtaining the total power dissipation 5.128nW.The pull-up and pull-down network used to
reduce the static power dissipation in full adder is used to improve the operating speed of each individual.
Performance Analysis of Proposed Full Adder Cell at Submicron TechnologiesIJMTST Journal
This paper presents an analysis of high-speed and low-voltage full adder circuit analysis. The proposed circuit analyzed for parameters like logic levels and power consumption. Full adder is an important circuit for designing many types of processors like microprocessors, digital signal processors, image processing and various VLSI applications etc. Many blocks of the designs, adders lie in critical data path of the circuit which affects the overall performance of the system. In this regards this paper analyses the proposed full adder cell at block level. Ripple carry adder is taken as the benchmark circuit to analyze the proposed full adder cell at 45nm technology.
Kubernetes & AI - Beauty and the Beast !?! @KCD Istanbul 2024Tobias Schneck
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Neuro-symbolic is not enough, we need neuro-*semantic*Frank van Harmelen
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All of this illustrated with link prediction over knowledge graphs, but the argument is general.
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Ch33509513
1. Pardeep Kumar, Susmita Mishra, Amrita Singh / International Journal of Engineering
Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 3, May-Jun 2013, pp.509-513
509 | P a g e
Study of Existing Full Adders and To Design a LPFA (Low Power
Full Adder)
Pardeep Kumar, Susmita Mishra, Amrita Singh
1
Department of ECE, B.M.S.E.C, Muktsar, 2,3
Asstt. Professor, B.M.S.E.C, Muktsar
Abstract
This paper describes the different logic
style used for CMOS full adders and different
equation used to implement the required Boolean
logic for full adders. This paper also describes
that the speed of the design is limited by size of
the transistors, parasitic capacitance and delay
in the critical path. Power consumption and
speed are two important but conflicting design
aspects; hence a better metric to evaluate circuit
performance is power delay product (PDP).The
driving capability of a full adder is very
important, because, full adders are mostly used
in cascade configuration, where the output of one
provides the input for other. If the full adders
lack Driving capability then it requires
additional buffer, which consequently increases
the power dissipation. At last a new LPFA
Design is proposed with comparisons between
the various full adders to show the better
performance of LPFA in terms of power
consumption, area (number of transistors) and
delay. The LPFA and all other various full
adders are designed and simulated using mentor
graphics tool in 0.18 μm technology. The
frequency used is 100 MHz. the voltage and all
the various full adders and others designs are
simulated at a voltage supply of 1.8V at same
frequency.
Keywords: CMOS Transmission Gate (TG),
PassTransistor Logic (PTL), Complementary Pass-
transistor Logic (CPL), Gate Diffusion Input (GDI),
LPFA (Low Power Full Adder), GDI based full
adder Power, Delay
1. Introduction
ADDITION is one of the fundamental
arithmetic operations. It is used extensively in many
VLSI systems such as application-specific DSP
architectures and microprocessors. In addition to its
main task, which is adding binary numbers, it is the
nucleus of many other useful operations such as
subtraction, Multiplication, division, addresses
calculation, etc. In most of these systems the adder
is part of the critical path that determines the overall
performance of the system. That is why enhancing
the performance of the 1-bit full-adder cell (the
building block of the binary adder) is a significant
goal.
The choice of logic style to design digital circuits
strongly influences the circuit performance. The
delay time depends on the size of transistors, the
number of transistors per stack, the parasitic
capacitance including intrinsic capacitance and
capacitance due to intracell and intercell routing,
and the logic depth (i.e., number of logic gates in
the critical path). The dynamic power consumption
depends on the switching activity and the number
and size of transistors. Among other things, the die
area depends on the number and size of transistors
and routing complexity.
At the system level, in many synchronous
implementations of microprocessors, the adder lies
in the critical path because it is a key element in a
wide range of arithmetic units such as ALUs and
multipliers.
Extensive variants of full adders have been
investigated by the academic and industrial research
communities. The usual performance evaluations
are speed, power consumption, and area. However,
since mobile and embedded applications have
prioritized the power consumption to stand at the
top of circuit and system performance evaluations,
the goal of many of these full-adder variants has
traditionally been the reduction of transistor count.
However, Chang et al. have shown in that although
some of these full adders feature good behavior
when implementing a 1-bit cell, they may show
performance degradation when used to implement
more complex structures.
Recently, building low-power VLSI
systems has emerged as highly in demand because
of the fast growing technologies in mobile
communication and computation. The battery
technology doesn’t advance at the same rate as the
microelectronics technology. There is a limited
amount of power Available for the mobile systems.
So designers are faced with more constraints: high
speed, high throughput, small silicon area, and at
the same time, low-power consumption. So building
low-power, high-performance adder cells is of great
interest.
2. Equation used in CMOS full adders
A full adder performs the addition of two
bits A and B with the Carry (Cin) bit generated in
the previous stage. The integer equivalent of this
relation is shown by:
2. Pardeep Kumar, Susmita Mishra, Amrita Singh / International Journal of Engineering
Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 3, May-Jun 2013, pp.509-513
510 | P a g e
A+B+Cin=2xCout +Sum (1)
The conventional logic equation for Sum and Carry
are:
Cout= (A∙B) + (A+B)∙Cin (2)
Sum= (A∙B∙Cin) + (A+B+Cin) ∙Cout (3)
By modifying the equations (2) and (3) the
following logics were proposed:-
Sum= A B Cin (4)
Cout= Cin (A B) +A∙(A B) (5)
Sum= A B Cin (6)
Sum= (Cin∙(A B)) + (Cin∙(A B) (7)
Cout= Cin (A∙B) + Cin∙(A+B) (8)
Full Adder using CMOS Logic and will be called as
“Conventional CMOS design”.
3. Existing full adder circuits
There are standard implementations for the
full-adder cell that are used from last few years
some of them among these adders there are the
following:-
Figure.1- The Conventional CMOS full-adder
The CMOS full adder (CMOS)[1] has 28 transistors
and is based on the regular CMOS structure
The Mirror logic [6] style based full adder has 28
transistors
Figure-2: Mirror logic style based full adder
The DPL logic [3] style based full adder has 28
transistors
A Transmission gate full adder [4] using 18
transistors
A full adder cell using 14 transistors
A full adder cell using 10 transistors
Figure: 3-DPL logic style based full adder
Figure-4: Transmission gate full adder
3. Pardeep Kumar, Susmita Mishra, Amrita Singh / International Journal of Engineering
Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 3, May-Jun 2013, pp.509-513
511 | P a g e
The DPL provides a saving power of about 2% over
the conventional CMOS based full adder. But they
generally do not provide good advantage over the
delay. So the main advantage in PDP (power delay
product) is only due to lesser power consuming
Logic style. The TG-FA provides a power saving of
1% and delay reduction of about 2% over the
conventional CMOS Based full adder.
.
Fig-5:14-T full adder cell Figure-6:10-T full
adder cell
4. Design of Low Power XOR and Low
Power XNOR
The improved versions are illustrated in
Fig. 11 and Fig.12.In the improved versions both
designs use 4transistors to achieve the same
functions of XOR and XNOR.
Fig:-11: LP XOR gate Fig 12:-: LP XNOR gate
Analysis on XOR structure, the output
signals in the cases of input signal AB = 01, 10, 11
will be complete. When AB = 00, each PMOS will
be on and will pass a poor “LO’ signal level to the
output end. That is, if AB = 00, the output end will
display a voltage, threshold voltage ~Vpth, a little
higher than “LO”. For the XNOR function, the
output signal in the case of AB = 00, 01, 10 will be
complete. While AB = 11, each NMOS will be on
and pass the poor “HI” signal level to the output
end. The analysis of driving capability is the same
as XOR structure. The structures stated above are
the versions of 4 transistors without a driving
output.
Fig:-13: LP XOR gate Fig 14:-: LP XNOR gate
With driving outputs with driving outputs
By cascading a standard inverter to the LP
XNOR circuit, a new type of XOR, as shown in Fig.
13 and Fig 14, will have a driving output, and the
signal level at the output end will be perfect in all
cases. The same property is present in the XNOR
structure.
The output waveforms for XOR and
XNOR for are given inputs A and B are shown in
Fig 15, 16 and Fig 17.
Fig-15:-showing the input signals A and B.
Fig:-16:- Showing the output of 6-transistor
XOR.
Fig:-17:- Showing the output of 6-transistor
XNOR
4. Pardeep Kumar, Susmita Mishra, Amrita Singh / International Journal of Engineering
Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 3, May-Jun 2013, pp.509-513
512 | P a g e
5. Design of Low Power Adder Using LP
XOR and XNOR
The Low power full adder which takes
lesser number of transistors than the all other
previously discussed configurations. The major
drawback of this method is that although it utilizes
lesser number of transistors but it does not provide
full swing at the output which is needed to drive any
external load. So to avoid this type of problem we
will form the XOR by using XNOR followed by an
inverter. Figure:-50 shown below is the schematic
for the LOW POWER FULL ADDER (LPFA).
Figure 50:- LPFA (Low Power Full Adder)
schematic
Now next we will show the sum and carry output
waveform of LPFA (Low Power Full Adder).
Figure 51:-Input and Sum output waveform of
LPFA
Figure 52:- Input and Carry output waveform of
LPFA
Figure 53:-Showing average current of LPFA
Now we will use this average current waveform to
find the dynamic power dissipation.
Dynamic power dissipation P= (average current)
x (voltage supply (Vdd))
SoP = (10.5152µA) x (1.8V) =18.92736 µW
6. Conclusion and Future work
As observed from the discussion about
the full adder that various designs have their own
advantage and disadvantage in terms of area, delay
and power consumption. So reducing any of these
parameters will leads to a high performance design
of full adder design.
5. Pardeep Kumar, Susmita Mishra, Amrita Singh / International Journal of Engineering
Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 3, May-Jun 2013, pp.509-513
513 | P a g e
Hence we can see that LPFA (Low Power Full
Adder) is better than all the other full adder designs
in terms of Power consumption, Area (Number of
Transistor), Delay, PDP (Power Delay Product.
Future work will be focused on the
reduction of any of the parameter shown above i.e.
Area, Delay and Power. There is also another term
i.e. PDP (power delay product) this is generally
used for to make a trade-off between power
consumption and delay.
Table 5:- Showing the comparison of
performance Conventional CMOS full Adder,
BBL-PT based full adder, HYBRID FULL
ADDER and LPFA
Desig
n
Del
ay(
ps)
Static
Power
Dissipa
tion(p
W)
Dynam
ic
Power
Dissipa
tion(µ
W)
Tota
l
Pow
er(µ
W)
Tra
nsist
or
Cou
nt
Conv
entio
nal
CMO
S full
adder
124 143.59
2
23.744
3
23.74
443
28
BBL-
PT
logic
based
full
adder
110.
3 126.30
8
22.606
38
22.60
6506
27
Hybri
d full
adder
142 158.67
4
29.787
1
29.78
7258
30
Low
Powe
r full
adder
(LPF
A)
101.
2
113.86
9
18.927
36
18.92
7473
26
Figure-5
References
[1]. I.Hassoune, A.Neve, J.Legat, and
D.Flandre, “Investigation of low-power
circuit techniques for a hybrid full-adder
cell,” in Proc. PATMOS 2004, pp. 189–
197, Springer-Verlag
[2]. A.M.Shams, Tarek k.darwish,”
performance analysis of low-power 1-bit
CMOS full adder cells IEEE Trans. Very
Large Scale Integ. (VLSI) Syst vol. 10 no
.1, pp.20-29, feb.2002.
[3]. C.-H. Chang, M. Zhang, “A review of
0.18 m full adder performances for tree
structured arithmetic circuits,” I EEE
Trans. Very Large Scale Integration.
(VLSI) Syst. vol. 13, no. 6, pp. 686–694,
Jun. 2005.
[4]. M.aguir re, M.linares “an alternative
logic app roach to implement high speed
low power full adder cells”SBBCI SEP
2005 PP. 166-171.
[5] A.K. Aggarwal, S. wairya, and
S.Tiwari,”a new full adder for high
speed low power digital circuits “world
science of journal 7 special issue of
computer and IT: June 2009,pp.- 138-144.
[6] M.Hossein, R.F.Mirzaee, K.Navi and
T.Nikoubin” new high performance
majority function based full adder cell” 14
inter national CSI conference 2009, pp.
100- 104.
[7] A.M.Shams,” A new full adder cell for
low power applications“ centre for
advance computer studies, university of
southwestern Louisiana.
[8] D.Radhakrishnan,” low power CMOS full
adder” IEE proc: - circuits devices system
vol. 148 no. 1 Feb. 2001.pp- 19-24.
[9] John p. Uyemura “Introduction to VLSI
circuits and systems”