This article presents novel high speed and low power full adder cells based on carbon nanotube field effect transistor (CNFET). Four full adder cells are proposed in this article. First one named CN9P4G) and second one (CN9P8GBUFF) utilizes 13 and 17 CNFETs respectively. Third design that we named CN10PFS uses only 10 transistors and is full swing. Finally, CN8P10G uses 18 transistors and divided into two modules, causing Sum and Cout signals are produced in a parallel manner. All inputs have been used straight, without inverting. These designs also used the special feature of CNFET that is controlling the threshold voltage by adjusting the diameters of CNFETs to achieve the best performance and right voltage levels. All simulation performed using Synopsys HSPICE software and the proposed designs are compared to other classical and modern CMOS and CNFET-based full adder cells in terms of delay, power consumption and power delay product.
Designing High-Speed, Low-Power Full Adder Cells Based on Carbon Nanotube Tec...VLSICS Design
This article presents novel high speed and low power full adder cells based on carbon nanotube field effect
transistor (CNFET). Four full adder cells are proposed in this article. First one (named CN9P4G) and
second one (CN9P8GBUFF) utilizes 13 and 17 CNFETs respectively. Third design that we named
CN10PFS uses only 10 transistors and is full swing. Finally, CN8P10G uses 18 transistors and divided into
two modules, causing Sum and Cout signals are produced in a parallel manner. All inputs have been used
straight, without inverting. These designs also used the special feature of CNFET that is controlling the
threshold voltage by adjusting the diameters of CNFETs to achieve the best performance and right voltage
levels. All simulation performed using Synopsys HSPICE software and the proposed designs are compared
to other classical and modern CMOS and CNFET-based full adder cells in terms of delay, power
consumption and power delay product.
CNFET BASED BASIC GATES AND A NOVEL FULLADDER CELLVLSICS Design
In this paper two novel high performance designs for AND and OR basic gates and a novel Full-Adder Cell are presented. These designs are based on carbon nanotube technology. In order to compare the proposed designs with previous ones both MOSFET based and CNFET based circuits are selected. By the way the proposed designs have better performance in comparison with previous designs in terms of speed, power consumption and power-delay product (PDP).
HIGH SPEED MULTIPLE VALUED LOGIC FULL ADDER USING CARBON NANO TUBE FIELD EFFE...VLSICS Design
High speed Full-Adder (FA) module is a critical element in designing high performance arithmetic circuits. In this paper, we propose a new high speed multiple-valued logic FA module. The proposed FA is constructed by 14 transistors and 3 capacitors, using carbon nano-tube field effect transistor (CNFET) technology. Furthermore, our proposed technique has been examined in different voltages (i.e., 0.65v and 0.9v). The observed results reveal power consumption and power delay product (PDP) improvements compared to existing FA counterparts.
A Low Power High Bandwidth Four Quadrant Analog Multiplier in 32 NM CNFET Tec...VLSICS Design
Carbon Nanotube Field Effect Transistor (CNFET) is a promising new technology that overcomes several limitations of traditional silicon integrated circuit technology. In recent years, the potential of CNFET for analog circuit applications has been explored. This paper proposes a novel four quadrant analog multiplier design using CNFETs. The simulation based on 32nm CNFET technology shows that the proposed multiplier has very low harmonic distortion (<0.45%), large input range (±400mV), large bandwidth (~50GHz) and low power consumption (~247µW), while operating at a supply voltage of ±0.9V.
Design of a CMOS-based microwave active channelized bandpass filterTELKOMNIKA JOURNAL
A two-branch microwave active bandpass filter is designed through the channelized filtering technique as well as the transversal concept. Both the main and the auxiliary branches, connected without power dividers/combiners, rely on C-coupled active third order Chebyshev bandpass filters. A lumped element signal delay circuit is also introduced in the main channel. Active inductors based on the gyrator-C topology, are involved in the Chebyshev filters’ structure. CMOS-based Operational Transconductor Amplifier (OTA) circuits are the building blocks of these inductors. The proposed active transversal channelized filter produces an elliptic narrow band response, centered at 1.13 GHz. Simulation results, obtained by means of the PSPICE code according to the 0.18 μm TSMC MOS technology, indicate excellent performances illustrating good impedance matching, low insertion losses and high selectivity. Finally, the noise analysis shows that the filter has a low noise figure in the bandwidth.
Performance Analysis of Interconnect Drivers for Ultralow Power ApplicationsIDES Editor
ultralow power consumption requirement of low
throughput applications needs to operate circuits in
subthreshold region where subthreshold leakage current is used
as active current for necessary computations. This paper
investigates the impact of interconnect drivers on digital circuit
performance in subthreshold region. In particular, we have
investigates the performance of Si-MOSFET and CNFETs at
32nm deep submicron technology node. Performance Analysis
is carried out for different interconnect drivers driving global
interconnect. We have proposed an optimized CNFET driver
which gives the significant improvement in delay and PDP over
conventional CNFET in subthreshold for global and semi-global
interconnect length. HSPICE device model files generated from
“Nano CMOS” tool are use for Si-MOSFET to analyze the
impact of Process and Temperature (P, T) variations on
robustness of circuit for fair comparison with CNFET.
Variability of design metric parameters is evaluated by applying
Gaussian distribution using Monte Carlo simulation run.
Interconnected Serialized Architecture for Transmission SystemsIJERD Editor
Transmission system with proposed multiplexer-flip-flops (MUX-FFs) has a high throughput and low-cost solution for serial link transmitters. MUX-FFs is designed with proposed multiplexer-latches that possess a logic function of various combinational circuits and storing capacity of sequential circuits. Pipeline arrangement with MUX-FFs composed of cascaded latches and MUX-latches with this many latch gates for sequential can be removed. Simulation results show that a 8-to-1 serializer with MUX-FFs reduces 63% gate-count compared to traditional pipeline transmission architecture. The measured results shows that the MUX-FFs and the proposed transmission architecture are almost bit error free and high speed in transmission.
Designing High-Speed, Low-Power Full Adder Cells Based on Carbon Nanotube Tec...VLSICS Design
This article presents novel high speed and low power full adder cells based on carbon nanotube field effect
transistor (CNFET). Four full adder cells are proposed in this article. First one (named CN9P4G) and
second one (CN9P8GBUFF) utilizes 13 and 17 CNFETs respectively. Third design that we named
CN10PFS uses only 10 transistors and is full swing. Finally, CN8P10G uses 18 transistors and divided into
two modules, causing Sum and Cout signals are produced in a parallel manner. All inputs have been used
straight, without inverting. These designs also used the special feature of CNFET that is controlling the
threshold voltage by adjusting the diameters of CNFETs to achieve the best performance and right voltage
levels. All simulation performed using Synopsys HSPICE software and the proposed designs are compared
to other classical and modern CMOS and CNFET-based full adder cells in terms of delay, power
consumption and power delay product.
CNFET BASED BASIC GATES AND A NOVEL FULLADDER CELLVLSICS Design
In this paper two novel high performance designs for AND and OR basic gates and a novel Full-Adder Cell are presented. These designs are based on carbon nanotube technology. In order to compare the proposed designs with previous ones both MOSFET based and CNFET based circuits are selected. By the way the proposed designs have better performance in comparison with previous designs in terms of speed, power consumption and power-delay product (PDP).
HIGH SPEED MULTIPLE VALUED LOGIC FULL ADDER USING CARBON NANO TUBE FIELD EFFE...VLSICS Design
High speed Full-Adder (FA) module is a critical element in designing high performance arithmetic circuits. In this paper, we propose a new high speed multiple-valued logic FA module. The proposed FA is constructed by 14 transistors and 3 capacitors, using carbon nano-tube field effect transistor (CNFET) technology. Furthermore, our proposed technique has been examined in different voltages (i.e., 0.65v and 0.9v). The observed results reveal power consumption and power delay product (PDP) improvements compared to existing FA counterparts.
A Low Power High Bandwidth Four Quadrant Analog Multiplier in 32 NM CNFET Tec...VLSICS Design
Carbon Nanotube Field Effect Transistor (CNFET) is a promising new technology that overcomes several limitations of traditional silicon integrated circuit technology. In recent years, the potential of CNFET for analog circuit applications has been explored. This paper proposes a novel four quadrant analog multiplier design using CNFETs. The simulation based on 32nm CNFET technology shows that the proposed multiplier has very low harmonic distortion (<0.45%), large input range (±400mV), large bandwidth (~50GHz) and low power consumption (~247µW), while operating at a supply voltage of ±0.9V.
Design of a CMOS-based microwave active channelized bandpass filterTELKOMNIKA JOURNAL
A two-branch microwave active bandpass filter is designed through the channelized filtering technique as well as the transversal concept. Both the main and the auxiliary branches, connected without power dividers/combiners, rely on C-coupled active third order Chebyshev bandpass filters. A lumped element signal delay circuit is also introduced in the main channel. Active inductors based on the gyrator-C topology, are involved in the Chebyshev filters’ structure. CMOS-based Operational Transconductor Amplifier (OTA) circuits are the building blocks of these inductors. The proposed active transversal channelized filter produces an elliptic narrow band response, centered at 1.13 GHz. Simulation results, obtained by means of the PSPICE code according to the 0.18 μm TSMC MOS technology, indicate excellent performances illustrating good impedance matching, low insertion losses and high selectivity. Finally, the noise analysis shows that the filter has a low noise figure in the bandwidth.
Performance Analysis of Interconnect Drivers for Ultralow Power ApplicationsIDES Editor
ultralow power consumption requirement of low
throughput applications needs to operate circuits in
subthreshold region where subthreshold leakage current is used
as active current for necessary computations. This paper
investigates the impact of interconnect drivers on digital circuit
performance in subthreshold region. In particular, we have
investigates the performance of Si-MOSFET and CNFETs at
32nm deep submicron technology node. Performance Analysis
is carried out for different interconnect drivers driving global
interconnect. We have proposed an optimized CNFET driver
which gives the significant improvement in delay and PDP over
conventional CNFET in subthreshold for global and semi-global
interconnect length. HSPICE device model files generated from
“Nano CMOS” tool are use for Si-MOSFET to analyze the
impact of Process and Temperature (P, T) variations on
robustness of circuit for fair comparison with CNFET.
Variability of design metric parameters is evaluated by applying
Gaussian distribution using Monte Carlo simulation run.
Interconnected Serialized Architecture for Transmission SystemsIJERD Editor
Transmission system with proposed multiplexer-flip-flops (MUX-FFs) has a high throughput and low-cost solution for serial link transmitters. MUX-FFs is designed with proposed multiplexer-latches that possess a logic function of various combinational circuits and storing capacity of sequential circuits. Pipeline arrangement with MUX-FFs composed of cascaded latches and MUX-latches with this many latch gates for sequential can be removed. Simulation results show that a 8-to-1 serializer with MUX-FFs reduces 63% gate-count compared to traditional pipeline transmission architecture. The measured results shows that the MUX-FFs and the proposed transmission architecture are almost bit error free and high speed in transmission.
DESIGN OF LOW WRITE-POWER CONSUMPTION SRAM CELL BASED ON CNTFET AT 32nm TECHN...VLSICS Design
The SRAM which functions as the cache for system-on-chip is vital in the electronic industry. Carbon Nanotube Field Effect Transistor (CNFET) is used for high performance, high stability and low-power circuit designs as an alternative material to silicon in recent years. Therefore Design of SRAM Cell based on CNTFET is important for Low-power cache memory. In cells, the bit-lines are the most power consuming components because of larger power dissipation in driving long bit-line with large capacitance. The cache write consumes considerable large power due to full voltage swing on the bit-line. This Paper proposes a novel 7T SRAM cell based on CNTFET that only depends on one of bit lines for Write operation and reduce the write-power consumption. The read cycle also improved because of careful transistor
sizing. HSPICE simulations of this circuit using Stanford CNFET model shows that 37.2% write power saving, read cycle improvement of 38.6%.
A parity generator is a circuit that generates redundant bits used for error detection
and is used when transmitting binary information. Previous parity generator circuits
based on quantum-dot cellular automata (QCA) are designed to reduce the area of the
circuit. Input cells of existing circuit are designed inside the circuit and the circuit’s
signal is not propagated properly due to the influence between adjacent wires. In
addition, existing circuits consume many clocks because the XOR gate, which is an
essential component of the parity generator circuit, consumes many clocks. In order to
solve this problem, we design a 3-bit odd parity generator circuit using QCA for fast
operation. The proposed circuit uses an XOR gate that can operate one clock faster
than the existing XOR gate to reduce the clock, and by extending this XOR gate, the
output value can be obtained faster than the conventional circuit. In the proposed
circuit, the result is verified through simulation and the performance is compared with
the existing circuit
BER ANALYSIS FOR DOWNLINK MIMO-NOMA SYSTEMS OVER RAYLEIGH FADING CHANNELSIJCNCJournal
The Multiple-input multiple-output (MIMO) technique combined with non-orthogonal multiple access (NOMA) has been considered to enhance total system performance. This paper studies the bit error rate of two-user power-domain NOMA systems using successive interference cancellation receivers, with zeroforcing equalization over quasi-static Rayleigh fading channels. Successive interference cancellation technique at NOMA receivers has been the popular research topic due to its simple implementation, despite its vulnerability to error propagation. Closed-form expressions are derived for downlink NOMA in single-input single-output and uncorrelated quasi-static MIMO Rayleigh fading channel. Analytical results are consolidated with Monte Carlo simulation.
DESIGN AND MODELLING OF DIFFERENT SRAM’S BASED ON CNTFET 32NM TECHNOLOGYVLSICS Design
Carbon nanotube field-effect transistor (CNTFET) refers to a field-effect transistor that utilizes a single carbon nanotube or an array of carbon nanotubes as the channel material instead of bulk silicon in the traditional MOSFET structure. Since it was first demonstrated in 1998, there have been tremendous developments in CNTFETs, which promise for an alternative material to replace silicon in future electronics. Carbon nanotubes are promising materials for the nano-scale electron devices such as nanotube FETs for ultra-high density integrated circuits and quantum-effect devices for novel intelligent circuits, which are expected to bring a breakthrough in the present silicon technology. A Static Random Access Memory (SRAM) is designed to plug two needs: i) The SRAM provides as cache memory, communicating between central processing unit and Dynamic Random Access Memory (DRAM). ii) The SRAM technology act as driving force for low power application since SRAM is portable compared to DRAM, and SRAM doesn’t require any refresh current. On the basis of acquired knowledge, we present
different SRAM's designed for the conventional CNTFET. HSPICE simulations of this circuit using Stanford CNTFET model shows a great improvement in power saving.
Design and Analysis of New Modified Feedthrough Logic (MFTL) Circuits Using C...IJERA Editor
It is a challenging task for a VLSI design engineer to develop low power VLSI circuits, without sacrificing its performance. Feedthrough Logic (FTL) is a new technology which could be considered better than the existing technologies for improving circuit efficiency. Modified Feedthrough Logic (MFTL), offers a better power factor than the FTL logic structures, and also shows an improvement in the speed factor. But the scenario again changes when the design extends to nano scales of device dimension, where many factors which were neglected otherwise need to be given more importance. To avoid or minimize problems like hot carrier effects, electro migration, drain induced barrier lowering and other issues that becomes prominent in nano scale MOSFET‟s, Carbon Nanotube Field Effect Transistor (CNTFET) is considered to be a promising candidate in future integrated circuits. Hence this work extends the advantages of MFTL logic into nano level by incorporating CNTFETs in place of MOSFETs. The modifications have been implemented using CNTFETs of 16nm technology from HSPICE library on a 10 chain inverter stage, an 8 bit RCA and a Vedic multiplier and performance factors like PDP and ADP are compared to that of the conventional MOSFET circuits.
Digital multipliers are among the most critical arithmetic functional units. The overall performance of these systems depends on the throughput of the multiplier. Meanwhile, the negative bias temperature instability effect occurs when a pMOS transistor is under negative bias (Vgs = −Vdd), increasing the threshold voltage of the pMOS transistor, and reducing multiplier speed. A similar phenomenon, positive bias temperature instability, occurs when an nMOS transistor is under positive bias. Both effects degrade transistor speed, and in the long term, the system may fail due to timing violations. Therefore, it is important to design reliable high performance multipliers. In this paper, we propose an aging-aware multiplier design with novel adaptive hold logic (AHL) circuit. The multiplier is able to provide higher throughput through the variable latency and can adjust the AHL circuit to mitigate performance degradation that is due to the aging effect. Moreover, the proposed architecture can be applied to a column- or row-bypassing multiplier. The experimental results show that our proposed architecture with 16 ×16 and 32 ×32 column-bypassing multipliers can attain up to 62.88% and 76.28% performance improvement, respectively, compared with 16×16 and 32×32 fixed-latency column-bypassing multipliers. Furthermore, our proposed architecture with 16 × 16 and 32 × 32 row-bypassing multipliers can achieve up to 80.17% and 69.40% performance improvement as compared with 16×16 and 32 × 32 fixed-latency row-bypassing multipliers.
DESIGN OF A HIGH PRECISION, WIDE RANGED ANALOG CLOCK GENERATOR WITH FIELD PRO...VLSICS Design
This paper presents a circuit of a high-precision, wide ranged, analog clock generator with on-chip programmability feature using Floating-gate transistors. The programmable oscillator can attain a continuous range of time-periods lying in the programming precision range of Floating Gates. The circuit consists of two sub circuits: Current Generator circuit and Wave Generator circuit. The current of current generator circuit is programmable and mirrored to the wave generator to generate the desired square wave. The topology is well suited to applications like clocking high performance ADCs and DACs as well as used as the internal clock in structured analog CMOS designs. A simulation model of the circuit was built in T-Spice, 0.35µm CMOS process. The circuit results in finely tuned clock with programmability precision of about 13bit [1]. Simulation results show high amount of temperature insensitivity (0.507ns/°C) for a large range of thermal conditions. The proposed circuit can compensate any change in temperature. The circuit design can be operated at low supply voltage i.e., 1v.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Design and Analysis of Power and Variability Aware Digital Summing CircuitIDES Editor
Due to aggressive scaling and process imperfection
in sub-45 nm technology node Vt (threshold voltage) shift is
more pronounced causing large variations in circuit response.
Therefore, this paper presents the analyses of various popular
1-bit digital summing circuits in light of PVT (process, voltage
and temperature) variations to verify their functionality and
robustness. The investigation is carried with ±3ó process
parameters and ±10% VDD (supply voltage) variation by applying
Gaussian distribution and Monte Carlo analysis at 22 nm
technology node on HSPICE environment. Design guidelines
are derived to select the most suitable topology for the design
features required. Transmission Gate (TG)-based digital
summing circuit is found to be the most robust against PVT
variations. Hence, a TG-based digital summing circuit is
implemented using carbon nanotube field effect transistor
(CNFET). This implementation offers tighter spread in
propagation delay (3×), power dissipation (1.14×) and EDP
(energy delay product) (1.1×) at nominal voltage of VDD = 0.95V
compared to MOSFET-based (TG – topology) digital summing
circuit implying its robustness against PVT variations.
Theoretical Analysis of a two-stage Sagnac loop filter Using Jones Matrices IJECEIAES
In this work, a theoretical analysis of a Sagnac loop filter (SLF) with twostage polarization maintaining fibers (PMFs) and polarization controllers (PCs) is presented. The transmission function of this two-stage SLF is calculated in detail by using Jones matrix. The calculation is performed in order to investigate the filtering characteristics. The theoretical results show that the wavelength interval is depending on the dynamic settings of the length of the PMFs and the polarization angle of the PCs. By changing the polarization angle of the PCs, a multiple of single, dual or triple wavelength in each channel can be achieved. Based on this study, a flat multiwavelength spectrum can be obtained by adjusting the PMFs and the PCs in the twostage SLF. This finding significantly contributes to the generation of multiwavelength fiber laser (MWFL) that can be used for many optical applications.
Performance Comparison of CMOS and Finfet Based Circuits At 45nm Technology U...IJERA Editor
According to the Moore’s Law, the number of transistors in a unit chip area double every two years. But the existing technology of integrated circuit formation is posing limitations to this law. CMOS technology shows certain limitations as the device is reduced more and more in the nanometer regime out of which power dissipation is an important issue. FinFET is evolving to be a promising technology in this regard. This paper aims to analyze and compare the characteristics of CMOS and FinFET circuits at 45nm technology. Inverter circuit is implemented in order to study the basic characteristics such as voltage transfer characteristics, leakage current and power dissipation. Further the efficiency of FinFET to reduce power as compared to CMOS is proved using SRAM circuit. The results show that the average power is reduced by 92.93% in read operation and by 97.8% in write operation.
HYBRID LS-LMMSE CHANNEL ESTIMATION Technique for LTE Downlink Systemsijngnjournal
In this paper, we propose to improve the performance of the channel estimation for LTE Downlink systems under the effect of the channel length. As LTE Downlink system is a MIMO-OFDMA based system, a cyclic prefix (CP) is inserted at the beginning of each transmitted OFDM symbol in order to mitigate both intercarrier interference (ICI) and inter-symbol interference (ISI). The inserted CP is usually equal to or longer than the channel length. However, the cyclic prefix can be shorter because of some unforeseen channel behaviour. Previous works have shown that in the case where the cyclic prefix is equal to or longer than the channel length, LMMSE performs better than LSE but at the cost of computational complexity .In the other case, LMMSE performs also better than LS only for low SNR values. However, LS shows better performance for LTE Downlink systems for high SNR values. Therefore, we propose a hybrid LS-LMMSE channel estimation technique robust to the channel length effect. MATLAB Monte –Carlo simulations areused to evaluate the performance of the proposed estimator in terms of Mean Square Error (MSE) and Bit Error Rate (BER) for 2x2 LTE Downlink systems.
A coupled-line balun for ultra-wideband single-balanced diode mixerTELKOMNIKA JOURNAL
A multi-section coupled-line balun design for an ultra-wideband diode mixer is presented in this paper. The multi-section coupled-line balun was used to interface with the diode mixer in which it can deliver a good impedance matching between the diode mixer and input/output ports. The mixer design operates with a Local Oscillator (LO) power level of 10 dBm, Radio Frequency (RF) power level of -20 dBm and Intermediate Frequency (IF) of 100 MHz with the balun characteristic of 180° phase shift over UWB frequency (3.1 to 10.6 GHz), the mixer design demonstrated a good conversion loss of -8 to -16 dB over the frequency range from 3.1 to 10.6 GHz. Therefore, the proposed multi-section coupled-line balun for application of UWB mixer showed a good isolation between the mixer’s ports.
Integrated Active Filters using low gain modulesIDES Editor
New integrated filters in CMOS technology are
presented which use current mirror based amplifiers to create
low gain modules as structural active blocks. The simplest
current amplifiers are purposely chosen. Wave techniques are
used for obtaining high reliability and low sensitivity filters
of any type. The derived filters are modular, simple in structure
and easy to design. Examples in simulation level are given
A NOVEL FULL ADDER CELL BASED ON CARBON NANOTUBE FIELD EFFECT TRANSISTORSVLSICS Design
Presenting a novel full adder cell will be increases all the arithmetic logic unit performance. In this paper, We present two new full adder cell designs using carbon nanotube field effect transistors (CNTFETs). In the first design we have 42 transistors and 5 pull-up resistance so that we have achieved an improvement in the output parameters. Simulations were carried out using HSPICE based on the CNTFET model with 0.9V VDD. The denouments results in that we have a considerable improvement in power, Delay and power delay product than the previous works.
ENERGY EFFICIENT FULL ADDER CELL DESIGN WITH USING CARBON NANOTUBE FIELD EFFE...VLSICS Design
Full Adder is one of the critical parts of logical and arithmetic units. So, presenting a low power full adder cell reduces the power consumption of the entire circuit. Also, using Nano-scale transistors, because of their unique characteristics will save energy consumption and decrease the chip area. In this paper we presented a low power full adder cell by using carbon nanotube field effect transistors (CNTFETs). Simulation results were carried out using HSPICE based on the CNTFET model in 32 nanometer technology in Different values of temperature and VDD.
DESIGN OF LOW WRITE-POWER CONSUMPTION SRAM CELL BASED ON CNTFET AT 32nm TECHN...VLSICS Design
The SRAM which functions as the cache for system-on-chip is vital in the electronic industry. Carbon Nanotube Field Effect Transistor (CNFET) is used for high performance, high stability and low-power circuit designs as an alternative material to silicon in recent years. Therefore Design of SRAM Cell based on CNTFET is important for Low-power cache memory. In cells, the bit-lines are the most power consuming components because of larger power dissipation in driving long bit-line with large capacitance. The cache write consumes considerable large power due to full voltage swing on the bit-line. This Paper proposes a novel 7T SRAM cell based on CNTFET that only depends on one of bit lines for Write operation and reduce the write-power consumption. The read cycle also improved because of careful transistor
sizing. HSPICE simulations of this circuit using Stanford CNFET model shows that 37.2% write power saving, read cycle improvement of 38.6%.
A parity generator is a circuit that generates redundant bits used for error detection
and is used when transmitting binary information. Previous parity generator circuits
based on quantum-dot cellular automata (QCA) are designed to reduce the area of the
circuit. Input cells of existing circuit are designed inside the circuit and the circuit’s
signal is not propagated properly due to the influence between adjacent wires. In
addition, existing circuits consume many clocks because the XOR gate, which is an
essential component of the parity generator circuit, consumes many clocks. In order to
solve this problem, we design a 3-bit odd parity generator circuit using QCA for fast
operation. The proposed circuit uses an XOR gate that can operate one clock faster
than the existing XOR gate to reduce the clock, and by extending this XOR gate, the
output value can be obtained faster than the conventional circuit. In the proposed
circuit, the result is verified through simulation and the performance is compared with
the existing circuit
BER ANALYSIS FOR DOWNLINK MIMO-NOMA SYSTEMS OVER RAYLEIGH FADING CHANNELSIJCNCJournal
The Multiple-input multiple-output (MIMO) technique combined with non-orthogonal multiple access (NOMA) has been considered to enhance total system performance. This paper studies the bit error rate of two-user power-domain NOMA systems using successive interference cancellation receivers, with zeroforcing equalization over quasi-static Rayleigh fading channels. Successive interference cancellation technique at NOMA receivers has been the popular research topic due to its simple implementation, despite its vulnerability to error propagation. Closed-form expressions are derived for downlink NOMA in single-input single-output and uncorrelated quasi-static MIMO Rayleigh fading channel. Analytical results are consolidated with Monte Carlo simulation.
DESIGN AND MODELLING OF DIFFERENT SRAM’S BASED ON CNTFET 32NM TECHNOLOGYVLSICS Design
Carbon nanotube field-effect transistor (CNTFET) refers to a field-effect transistor that utilizes a single carbon nanotube or an array of carbon nanotubes as the channel material instead of bulk silicon in the traditional MOSFET structure. Since it was first demonstrated in 1998, there have been tremendous developments in CNTFETs, which promise for an alternative material to replace silicon in future electronics. Carbon nanotubes are promising materials for the nano-scale electron devices such as nanotube FETs for ultra-high density integrated circuits and quantum-effect devices for novel intelligent circuits, which are expected to bring a breakthrough in the present silicon technology. A Static Random Access Memory (SRAM) is designed to plug two needs: i) The SRAM provides as cache memory, communicating between central processing unit and Dynamic Random Access Memory (DRAM). ii) The SRAM technology act as driving force for low power application since SRAM is portable compared to DRAM, and SRAM doesn’t require any refresh current. On the basis of acquired knowledge, we present
different SRAM's designed for the conventional CNTFET. HSPICE simulations of this circuit using Stanford CNTFET model shows a great improvement in power saving.
Design and Analysis of New Modified Feedthrough Logic (MFTL) Circuits Using C...IJERA Editor
It is a challenging task for a VLSI design engineer to develop low power VLSI circuits, without sacrificing its performance. Feedthrough Logic (FTL) is a new technology which could be considered better than the existing technologies for improving circuit efficiency. Modified Feedthrough Logic (MFTL), offers a better power factor than the FTL logic structures, and also shows an improvement in the speed factor. But the scenario again changes when the design extends to nano scales of device dimension, where many factors which were neglected otherwise need to be given more importance. To avoid or minimize problems like hot carrier effects, electro migration, drain induced barrier lowering and other issues that becomes prominent in nano scale MOSFET‟s, Carbon Nanotube Field Effect Transistor (CNTFET) is considered to be a promising candidate in future integrated circuits. Hence this work extends the advantages of MFTL logic into nano level by incorporating CNTFETs in place of MOSFETs. The modifications have been implemented using CNTFETs of 16nm technology from HSPICE library on a 10 chain inverter stage, an 8 bit RCA and a Vedic multiplier and performance factors like PDP and ADP are compared to that of the conventional MOSFET circuits.
Digital multipliers are among the most critical arithmetic functional units. The overall performance of these systems depends on the throughput of the multiplier. Meanwhile, the negative bias temperature instability effect occurs when a pMOS transistor is under negative bias (Vgs = −Vdd), increasing the threshold voltage of the pMOS transistor, and reducing multiplier speed. A similar phenomenon, positive bias temperature instability, occurs when an nMOS transistor is under positive bias. Both effects degrade transistor speed, and in the long term, the system may fail due to timing violations. Therefore, it is important to design reliable high performance multipliers. In this paper, we propose an aging-aware multiplier design with novel adaptive hold logic (AHL) circuit. The multiplier is able to provide higher throughput through the variable latency and can adjust the AHL circuit to mitigate performance degradation that is due to the aging effect. Moreover, the proposed architecture can be applied to a column- or row-bypassing multiplier. The experimental results show that our proposed architecture with 16 ×16 and 32 ×32 column-bypassing multipliers can attain up to 62.88% and 76.28% performance improvement, respectively, compared with 16×16 and 32×32 fixed-latency column-bypassing multipliers. Furthermore, our proposed architecture with 16 × 16 and 32 × 32 row-bypassing multipliers can achieve up to 80.17% and 69.40% performance improvement as compared with 16×16 and 32 × 32 fixed-latency row-bypassing multipliers.
DESIGN OF A HIGH PRECISION, WIDE RANGED ANALOG CLOCK GENERATOR WITH FIELD PRO...VLSICS Design
This paper presents a circuit of a high-precision, wide ranged, analog clock generator with on-chip programmability feature using Floating-gate transistors. The programmable oscillator can attain a continuous range of time-periods lying in the programming precision range of Floating Gates. The circuit consists of two sub circuits: Current Generator circuit and Wave Generator circuit. The current of current generator circuit is programmable and mirrored to the wave generator to generate the desired square wave. The topology is well suited to applications like clocking high performance ADCs and DACs as well as used as the internal clock in structured analog CMOS designs. A simulation model of the circuit was built in T-Spice, 0.35µm CMOS process. The circuit results in finely tuned clock with programmability precision of about 13bit [1]. Simulation results show high amount of temperature insensitivity (0.507ns/°C) for a large range of thermal conditions. The proposed circuit can compensate any change in temperature. The circuit design can be operated at low supply voltage i.e., 1v.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Design and Analysis of Power and Variability Aware Digital Summing CircuitIDES Editor
Due to aggressive scaling and process imperfection
in sub-45 nm technology node Vt (threshold voltage) shift is
more pronounced causing large variations in circuit response.
Therefore, this paper presents the analyses of various popular
1-bit digital summing circuits in light of PVT (process, voltage
and temperature) variations to verify their functionality and
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parameters and ±10% VDD (supply voltage) variation by applying
Gaussian distribution and Monte Carlo analysis at 22 nm
technology node on HSPICE environment. Design guidelines
are derived to select the most suitable topology for the design
features required. Transmission Gate (TG)-based digital
summing circuit is found to be the most robust against PVT
variations. Hence, a TG-based digital summing circuit is
implemented using carbon nanotube field effect transistor
(CNFET). This implementation offers tighter spread in
propagation delay (3×), power dissipation (1.14×) and EDP
(energy delay product) (1.1×) at nominal voltage of VDD = 0.95V
compared to MOSFET-based (TG – topology) digital summing
circuit implying its robustness against PVT variations.
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DESIGNING HIGH-SPEED, LOW-POWER FULL ADDER CELLS BASED ON CARBON NANOTUBE TECHNOLOGY
1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.5, October 2014
DOI : 10.5121/vlsic.2014.5503 31
DESIGNING HIGH-SPEED, LOW-POWER FULL
ADDER CELLS BASED ON CARBON NANOTUBE
TECHNOLOGY
Mehdi Masoudi1
, Milad Mazaheri1
, Aliakbar Rezaei1
and Keivan Navi4
1
Department of Computer Engineering,
Science and Research Branch of IAU, Tehran, Iran
4
Department of Electrical and Computer Engineering,
Shahid Beheshti University, Tehran, Iran
ABSTRACT
This article presents novel high speed and low power full adder cells based on carbon nanotube field effect
transistor (CNFET). Four full adder cells are proposed in this article. First one (named CN9P4G) and
second one (CN9P8GBUFF) utilizes 13 and 17 CNFETs respectively. Third design that we named
CN10PFS uses only 10 transistors and is full swing. Finally, CN8P10G uses 18 transistors and divided into
two modules, causing Sum and Cout signals are produced in a parallel manner. All inputs have been used
straight, without inverting. These designs also used the special feature of CNFET that is controlling the
threshold voltage by adjusting the diameters of CNFETs to achieve the best performance and right voltage
levels. All simulation performed using Synopsys HSPICE software and the proposed designs are compared
to other classical and modern CMOS and CNFET-based full adder cells in terms of delay, power
consumption and power delay product.
KEYWORDS
Full Adder, CNT, Carbon Nanotube Field Effect Transistor, High Speed, Low Power, High Performance &
Power Delay Product
1. INTRODUCTION
In digital electronic world, delay and power consumption improvement are the most important
performance parameters of a circuit. To reach this goal, we can reduce scaling of the feature size.
In complementary metal oxide semiconductor (CMOS) technology, reducing the length of
channel to below about 65nm leads to critical problems and challenges such as decreasing gate
control, short channel effect, high power density, high sensitivity to process variation and
exponential leakage current increment [1]. For this reasons reducing the transistors size finally
will stop at a point, leading to taking advantage of new technologies that do not have above
problems may be felt. Therefore, new technologies such as benzene rings, quantum dot cellular
automata (QCA), single electron transistor (SET), carbon nanotube field effect transistor
(CNFET) and others have risen up [2-7].
Special properties of the carbon nanotubes (CNTs) cause to be utilized in various industries such
as nanoelectronic. Some of these features are high thermal conductivity, high tensile strength,
super conductivity, extreme rigidity and be conductor or semiconductor basis on structure.
2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.5, October 2014
32
Carbon nanotube field effect transistor (CNFET) is an appropriate alternative for CMOS. Owing
to similarity between CNFET and CMOS in case of operation principle and the device structure,
we can perform the established CMOS design infrastructure and CMOS manufacturing process in
the CNFET technology [2]. CNFET is one of the molecular devices that avoid most fundamental
silicon transistor restrictions and have ballistic or near ballistic transport in its channel and have
high current carry ability [6-8]. Generally CNFET is faster and use lesser power consumption
compared to silicon-based MOSFET and for this reason it is very suitable for high frequency and
low voltage applications. Another useful trait of CNFET is that P-CNFET and N-CNFET have
the same mobility and the same current drive capability, which is very important for transistor
sizing in the complex circuits [9].
Recently some designs have been performed by CNFETs such as Galois field circuits [10],
multiple valued logic circuits [1, 10, 11], interconnection networks [12-14] and CNFET full
adders [13, 15]. Full adder cell is a basic element for complex circuits also most of arithmetic
operations can be implemented by full adder cells. So performance increment of full adder causes
to improve system performance [16]. Many efforts have been done to increase the efficiency of
this element. Full adder performance improvement can be performed in various stages such as
algorithm, circuit and technology. In this paper we present design details of high speed and low
power full adder cells based on nanotechnology.
The rest of this paper is organized as follows. In section 2 a brief description about CNFET is
provided. Previous works are presented in section 3. The proposed full adder cells are presented
in section 4. Experimental results, analyses and comparisons are presented in section 5 and finally
section 6 concludes the paper.
2. CARBON NANOTUBE FIELD EFFECT TRANSISTORS (CNFETS)
Carbon nanotube in theoretical definition is a sheet of graphite which is rolled up along a
wrapping vector [17]. CNT can be single-wall (SWCNT) or multi-wall (MWCNT) [18]. Single-
wall CNT is made by one layer of graphite and multi-wall CNT is made by more than one layer
of graphite, then it is rolled up and all cylinders center is same. Carbon nanotubes are represented
by a vector is called chirality vector. According to Figure 1, chirality vector is shown by and
is obtained by: where are lattice unit vectors and are positive
integers which specify the tube’s structure [19]. Depending on and we have three different
kinds of nanotube: zigzag, armchair and chiral (Figure 1(a)) and the SWCNT has different
manners such that if then SWCNT will be conductor otherwise SWCNT will
be semiconductor [6, 20]. Conductive CNT is used as nanowires and semiconductive CNT is
applied as transistor channel [6]. In CNFETs, one or more semiconductive SWCNTs can be used
and a typical CNFET is illustrated in Figure 1(b).
Figure 1. (a) Representation of a SWNT by a chiral vector [8]¸ (b) schematic of CNFET [21]
3. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.5, October 2014
33
of CNFET is calculated approximately based on following equation:
where pitch is the distance between the centers of two
neighbor SWCNTs under the same gate, is the minimum width of the gate and N is the
number of nanotubes.
The diameter of nanotube is given by Equation (1) [22].
The threshold voltage of CNFET is an inverse function of the diameter of CNT. We use this
ability to control by changing the . The CNFET threshold voltage ( ) is calculated
based on Equation (2) [22].
Where parameter is the band gap energy, parameter a is the carbon-to-carbon
atom distance, the carbon bond energy, e is the unit electron charge and
is the diameter of CNT.
Depending on the type of connections between source and drain with CNT channel and type of
source, drain and gate, there are three main CNFETs. The first type is schottky barrier CNFET
(SB-CNFET), which the CNT directly contacts to metal source. Schottky barrier junction limits
the transconductance in the ON state, thus ION/IOFF ratio becomes rather low. SB-CNFET is
appropriate for medium to high-performance applications. The second type of CNFET is the
band-to-band tunneling CNFET (T-CNFET). T-CNFET has super cut-off characteristics and low
ON current. These specifications make it suitable for low power and subthreshold application but
it is not appropriate for very high speed applications. The third type of CNFET is MOSFET-like
CNFETs. Source and drain are doped with positive impurities, so a semiconductor-semiconductor
junction between source-drain and channel is made and source-channel junction is not schottky
barrier. As a result MOSFET-like CNFETs have high ON current, high ION/IOFF ratio and
scalability that make it suitable for high performance applications [6, 23, 24]. In this paper we
employ MOSFET-like CNFETs for all proposed designs.
3. PREVIOUS WORKS
As mentioned before, CNFET is a suitable alternative for silicon-based technology that does not
have MOSFET problems. Many full adder designs by MOSFET and CNFET are proposed so far
and each of them has their advantages and disadvantages. In this paper we select 5 popular full
adder cells that three of them are designed with 32nm MOSFET technology and two of them
designed with 32nm CNFET technology. In this section a brief description of some prior works is
presented.
First one is conventional CMOS full adder (CCMOS). It has 28 transistors and consumes high
power and area[25, 26]. This design is based on standard CMOS topology and has full swing
4. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.5, October 2014
34
output that increases noise margin and reliability. Because of using high number of PMOS in pull
up network, this design has high input capacitance, leading to high delay and dynamic power
consumption. Although, using inverters on the output nodes decreases the rise-time and fall-time
delay and increases the driving ability. Next sample full adder cell is TG-CMOS which has 20
transistors [27]. This full adder uses conventional transmission gates on its structure. In TG-
CMOS full adder all outputs are obtained based on XOR/XNOR gates and afterwards uses MUX
structure. This design has low power dissipation because of using transmission gate but utilizes
high number of transistors.
Next design, CMOS-Bridge uses 24 transistors and takes advantage of the high-performance
bridge structure [28]. In this design Cout signal is produced based on a CMOS style and Sum
signal is generated from Cout by means of a bridge circuit. In addition, to generate Cout and Sum
from and and for enhancing the driving capability, two inverters are utilized at the
output nodes.
Next full adder is proposed in [29] and has been designed by CNFETs (Figure 2(a)) (we named it
CNT-FA1 in this paper). It uses 14 transistors plus three capacitors. This design is based on
majority function and is adjusted by changing the diameters of CNFETs. CNT-FA1 provides
good delay and power properties.
Full adder cell that proposed in [30] (we named it CNT-FA2 in this paper) uses majority function
plus inverter to generate and also by meaning to adjusting the and as result, adjusting
the Vth in PCNFET and NCNFET, NAND and NOR has been created by inverter structure
(Figure 2(b)). This design uses two pass transistors after NAND and NOR to generate
output and using pass transistor causes to the output does not be full swing but the final inverter
fixes it and makes full swing output. This design is symmetric and delay, power consumption and
PDP parameters are suitable.
Figure 2. (a) CNT-FA1 full adder, (b) CNT-FA2 full adder
4. PROPOSED DESIGNS
In this section we propose four new full adder cells. The logic formula for a one-bit full adder is
shown in Equation (3). The inputs are A, B, C (C is carry input) and outputs are Sum and Cout.
XOR is shown by symbol.
5. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.5, October 2014
35
According to Equation (3), we can generate Sum by using XOR twice. First, A and B become
XOR and then the result of previous stage become XOR with C. A XOR module is illustrated in
Figure 3. This module uses two pass transistors and two pull down transistors. Pass transistors can
cover the 3 states of inputs that are 00, 01, 10 and one more remained state (11) is handled by pull
down network. By using twice of this module, is obtained. All proposed designs use
this module to generate Sum signal.
Figure 3. XOR module
According to Equation (4), we can use to generate Cout. So in the first proposed design, we
have used a transmission gate to lead C into Cout when is high. In this status two states
remain, when both A and B are high or both A and B are low. First one covered by a pair series of
NCNFETs and second one covered by another pair series of PCNFETs. This design uses 13
transistors. We named it CN9P4G and shown in Figure 4.
Figure 4. CN9P4G (Proposed1)
This design and others that will present later, depending on input values can have threshold losing
in output voltages and are not full swing. For solving this problem we have some method such
asusing transmission gate instead of pass transistor or using output buffers, but these methods
cause to increase transistor using and critical path and in result increasing power consumption and
delay. CNFETs have a special property that can be used for this case. According to Equation (2),
6. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.5, October 2014
36
the threshold voltage is inversely proportional to the diameter of its CNT. So by increasing the
diameter of CNT, can be reduced. Decreasing of leads to better driving capability and
higher speed and the full swing problem can be solved. According to Equation (1), is
obtained by chiral vector with pair.
So as a result we use for all PCNFETs and NCNFETs. By
this amount of diameter, will be very low.
According to simulation results, voltage drop is very lower than the value of the threshold. This is
due to the very high-speed operation of CNFETs with large diameters in subthreshold region.
Larger CNT diameter leads to have smaller band gap, and smaller band gap leads to higher on-
currents and shorter propagation delay. In addition, CNFETs with smaller band gap and as result
smaller threshold voltage, are less sensitive to process variations and it leads to better
manufacturability [31].
In first proposed design (CN9P4G) two states are exist that Cout is not full swing, when
ABC=001 or ABC=110. When these input patterns occur, pass transistors will have current in
subthreshold region and causes to destroyed output voltage. To fix this problem we use a buffer in
Cout output in second proposed design, CN9P8GBUFF (Figure 5). Using buffer causes to
increase critical path to 5 transistors and consequently more power consumption and delay rather
than first design (CN9P4G). Transistors using is also increased to 17, but outputs become full
swing.
Figure 5. CN9P8GBUFF (Proposed2)
In proposed design 3, Cout is generated in another way and transistor using decrement is also
significant (Figure 6). In this design we implement Equation (5) by a NCNFET and a PCNFET
pass transistor.
7. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.5, October 2014
37
Total used transistors are 10. This design due to using large diameter CNFETs
is full swing.
Figure 6. CN10PFS (Proposed3)
Next design (CN8P10G) includes two modules to generate Sum and Cout signals separately
(Figure 7). CN8P10G has a parallel manner in producing Sum and Cout and uses 18 transistors.
Sum made by using XOR module (Figure 3) twice like other proposed designs. Cout signal has
been generated by using Equation (6). Also all output voltages are full swing.
Figure 7. CN8P10G (Proposed4)
5. SIMULATION RESULTS ANALYSIS AND COMPARISON
All proposed designs and previous designs were described in section 3 and 4, have been
simulated by Synopsys HSPICE 2010. CMOS-based circuits are simulated using 32nm CMOS
technology and CNFET-based circuits are simulated using compact SPICE model for 32nm [8,
32-34]. Compact SPICE model has been designed for unipolar MOSFET-like CNFET devices
and each transistor can have one or more CNTs. This model considered schottky barrier effects,
parasitics, CNT charge screening effects, CNT Source/Drain and gate resistances and
8. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.5, October 2014
38
capacitances. The parameters of this CNFET model, corresponding values and a brief description
are presented in Table 1.
Table 1. CNFET model parameters
Parameter Description Value
Lch Physical channel length 32nm
Lgeff The mean free path in the intrinsic CNT channel 100nm
Lss The length of doped CNT source-side extension region 32nm
Ldd The length of doped CNT drain-side extension region 32nm
Kgate The dielectric constant of high-k top gate dielectric material 16
Tox The thickness of high-k top gate dielectric material 4nm
Csub The coupling capacitance between the channel region and the substrate 40 pF/m
Efi The fermi level of the doped S/D tube 6 eV
All four proposed designs output waves are shown in Figure 8. As can be seen CN9P4G is not
full swing for 001 and 110 input patterns and all other designs are full swing.
Figure 8. The input and output signals of 4 proposed full adder
9. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.5, October 2014
39
Main comparison factor in this paper is PDP (Power Delay Product), so in variation of load
capacitor, frequency, power voltage and temperature, all PDPs have been calculated.
Table 2 shows simulation results for all designs at 250 MHz frequency, 2.1 femto Farad load
capacitor and 25° temperature in variation of supply voltage from 0.5v to 0.8v. Delay, power
consumption and PDP of our designs have been shown in this Table. Our proposed full adders
have lower delay, power and PDP rather than other mentioned previous circuits. For example,
according to Table 2, PDP of CN8P10G at 2.1 femto Farad capacitor and power voltage 0.65 has
86.1% improvement rather than CMOS-bridge, 80.9% improvement rather than C-CMOS, 76.9%
improvement rather than TG-CMOS, 79.3% improvement rather than CNT-FA1 and 66.7%
improvement rather than CNT-FA2.
Table 2. Simulation results at frequency=250MHz and load capacitor=2.1 femto Farad
Vdd=0.5 v Vdd=0.65 v Vdd=0.8 v
Delay(E-10s)
CMOS-Bridge 4.9264 1.926 12.002
CCMOS 3.9300 1.444 9.4001
TG-CMOS 2.3753 0.88103 5.4938
CNT-FA1 3.0340 0.8747 4.8074
CNT-FA2 2.1070 0.79694 5.8841
CN9P4G(P1) 0.40743 0.29928 0.27675
CN9P8GBUFF(P2) 0.43620 0.32865 0.27409
CN10PFS(P3) 0.45567 0.34379 0.28079
CN8P10G(p4) 0.27607 0.27331 0.86408
Power(E-7w)
CMOS-Bridge 1.6830 3.0314 5.2361
CCMOS 1.6369 2.926 5.0607
TG-CMOS 2.1678 3.9688 7.6154
CNT-FA1 1.5523 4.4724 3.1228
CNT-FA2 1.3761 3.0466 1.6917
CN9P4G(P1) 1.9720 3.0276 4.3138
CN9P8GBUFF(P2) 2.1721 3.3545 4.9056
CN10PFS(P3) 1.8339 2.8507 4.1671
CN8P10G(p4) 1.8620 2.9572 4.3012
PDP(E-17J)
CMOS-Bridge 8.2742 5.8384 6.2844
CCMOS 6.4329 4.2253 4.7571
TG-CMOS 5.1492 3.4966 4.1837
CNT-FA1 4.7097 3.912 15.013
CNT-FA2 2.8995 2.4279 9.9541
CN9P4G(P1) 0.80345 0.9061 1.1938
CN9P8GBUFF(P2) 0.94746 1.1024 1.3446
CN10PFS(P3) 0.83566 0.98004 1.1701
CN8P10G(p4) 0.51404 0.80823 3.7166
In the next evaluation, load capacitor is increased from 1.4 to 4.9 femto Farad and other
parameters are fixed at Vdd=0.65V, frequency=250MHz and temperature=25°. All delays,
powers and PDPs are calculated and are shown in Figure 9, Figure 10 and Figure 11 respectively.
10. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.5, October 2014
40
Figure 9. Delay of the circuits versus load capacitor variations
Figure 10. Power consumption of the circuits versus load capacitor variations
Figure 11. PDP of the circuits versus load capacitor variations
11. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.5, October 2014
41
Another changed parameter is frequency (Figure 12). This simulation has been performed in
Vdd=0.65V, Cload=2.1 femto Farad and temperature=25°. CN8P10G has lower PDP in selected
frequencies and also has lower increment ratio.
Figure 12. PDP of the circuits versus frequency variations
Figure 13 shows results with temperature variations from 0° to 70°, frequency=250MHz, load
capacitor=2.1 femto Farad and power voltage=0.65V. PDP for all designs has been calculated. In
this analysis, presented designs have lower PDP in all temperature.
Figure 13. PDP of the circuits versus temperature variations
6. CONCLUSIONS
In this article some new full adder designs have been presented which are high speed, low power
and high performance. By using exclusive properties of CNTFET, the efficiency of these designs
was improved. Circuits were simulated in various conditions and simulation results approved the
efficiency of proposed designs rather than other CMOS and CNFET-based designs that
investigated before.
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42
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AUTHORS
Mehdi Masoudi received his B.Sc. degree in hardware engineering from Shahid Beheshti
University, Tehran, Iran, in 2007 and M.Sc. degree in computer architecture from IAU
Science and Research branch, Tehran, Iran, in 2013. He is a research member at
Nanotechnology and Quantum Computing Laboratory of Shahid Beheshti University. His
research interests include High Performance VLSI Designs, Nanoelectronics and new
emerging technologies specially CNFET.
Milad Mazaheri received his M.Sc. degree in computer architecture from Science and
Research Branch, IAU, Tehran, Iran in 2013. He is currently pursuing his Ph.D. degree in
computer architecture from Science and Research Branch of IAU, Tehran, Iran. His
research interests include Photonic Networks-on-chip, VLSI Systems Design, Embedded
Systems, Multiprocessor Systems, Fault Tolerant Design and Computer Architecture.
Aliakbar Reazei received his B.Sc. degree in hardware engineering from Shahid Beheshti
University, Tehran, Iran, in 2007 and M.Sc. degree in computer architecture from IAU
Science and Research branch, Tehran, Iran, in 2013. He is a research member at
Nanotechnology and Quantum Computing Laboratory of Shahid Beheshti University. His
research interests include High Performance VLSI Designs, Sensor Networks and
Computer Architecture.
Keivan Navi received his M.Sc. degree in electronics engineering from Sharif University
of Technology, Tehran, Iran in 1990. He also received his Ph.D. degree in computer
architecture from Paris XI University, Paris, France in 1995. He is currently Professor in
Faculty of Electrical and Computer Engineering of Shahid Beheshti University. His
research interests include Nanoelectronics with emphasis on CNFET, QCA and SET,
Interconnection Network Design, Quantum Computing and Cryptography. He has been a
visiting professor at the University of California, Irvine.