This document discusses various aspects of computer organization and assembly language. It covers the central processing unit including the register set, arithmetic logic unit, control unit, and data path. It also describes different instruction cycle models and bus organizations such as one-bus, two-bus, and three-bus. Interrupts and how they allow other modules to interrupt normal program processing are explained. The control unit and how it manages computer resources through control and timing signals is covered. Microprogrammed and hardwired control unit designs are compared.

1. COMPUTER ORGANIZATION
& ASSEMBLY LANGUAGE
LECTURE # 10
BY MUHAMMAD JAFER
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2. CENTERAL PROCESSING UNIT
• Register Set
• Athematic Logic Unit
• Control Unit
• Data path
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3. INSTRUCTION CYCLE
• Instruction Register
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4. DATA PATH
• Capable of performing certain operation on data
• Athematic Logic Unit
• External Busses & Internal Busses
• Both can have different design
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5. ONE-BUS ORGANIZATION
• Single Bus
• One instruction fetching per CPU cycle
• Simple & Cheapest
• Slow
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6. TWO-BUS ORGANIZATION
• two Bus
• Two instruction fetching per CPU cycle
• In-bus & Out-bus design
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7. THREE-BUS ORGANIZATION
• Three Bus
• Two In-bus & one Out-bus design
• More busses will have data transfer faster
• More complex hardware design
• Expensive
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8. INSTRUCTION CYCLE EXAMPLES
• MOV AL,5
• ADD AL,[003]
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9. COMPLEX INSTRUCTION CYCLE
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10. INTERRUPTS
• Mechanism by which other modules (e.g. I/O)
may interrupt normal sequence of processing
• Program
• e.g. overflow, division by zero
• Timer
• Generated by internal processor timer
• Used in pre-emptive multi-tasking
• I/O
• from I/O controller
• Hardware failure
• e.g. memory parity error
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11. IF INTERRUPTS
•Suspend execution of current program
•Save context
•Set PC to start address of interrupt
handler routine
•Process interrupt
•Restore context and continue interrupted
program
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12. IF INTERRUPTS
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13. IF INTERRUPTS
•Suspend execution of current program
•Save context
•Set PC to start address of interrupt
handler routine
•Process interrupt
•Restore context and continue interrupted
program
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14. PROGRAM TIMING
SHORT I/O WAIT
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15. PROGRAM TIMING
LONG I/O WAIT
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16. CONTROL UNIT
• Part of CPU
• Management of Computer Resources
• Control and Timing Signals
• Directs Flow of Data
• CU Types
• Mircoprogrammed
• Hardwire
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17. MICROPROGRAMMED
• Memory Units storing Control Signals
• Inaccessible Memory Units in RAM or ROM
• Control Word is microinstruction
• Microinstruction = 1/More Microoperations
• Sequence of microinstructions are microprograms
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18. HARDWIRED
• Fixed Logical Instructions
• Far more faster
• Not cheaper & Complex
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19. CHAPTER REVIEW
• Fundamentals of Computer Organization and
Architecture by Mostafa Abd-Al-Barr & Hesham
AlRewini
• Chapter # 5
• CPU Basics
• Register Set
• Datapath
• CPU Instruction Cycle
• Control Unit
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