This document summarizes a presentation given at the 9th International SoC Conference on November 2nd-3rd, 2011. The presentation discusses trends in processor design, including the transition to multi-core and heterogeneous systems. It introduces Fusion System Architecture (FSA), which combines CPU and GPU capabilities on a single die. The presentation also discusses challenges in areas like power management, high-speed interconnects, 3D stacking, verification efforts, IP integration, and TLM-RTL co-simulation.
EFFICIENT POWER MANAGEMENT TECHNIQUES SUCH AS SKIN TEMPERATURE AWARE POWER MANAGEMENT AND BATTERY BOOST FOR IMPROVED ENERGY EFFICIENCY [PERFORMANCE/WATT]
DEVELOPING PERFORMANCE ANALYSIS ENVIRONMENT BY REUSING EXISTING VERIFICATION ENVIRONMENT
HOLISTIC VIEW OF SOC VERIFICATION :
EVOLUTION OF UVM METHDOLOGY, UVM 1.2 AND CHALLENGES WITH MULTI LANGUAGE SUPPORT/AMS SUPPORT.
EDA INDUSTRY/TOOL CHALLENGES WITH HW-SW DEBUG, VP MODEL VERIFICATION.
H/W ASSISTED SIMULATION ACCELERATION, CHOOSING EMULATION CONFIGURATION FOR YOUR DESIGN.
Tyrone-Intel oneAPI Webinar: Optimized Tools for Performance-Driven, Cross-Ar...Tyrone Systems
Modern workloads are incredibly diverse and so are architectures. No single architecture is best for every workload. Maximizing performance takes a mix of architectures deployed in CPU, GPU, FPGA, and other future accelerators. Intel® oneAPI products deliver the tools needed to deploy applications and solutions across SVMS architectures. Learn about oneAPI and how they can be used in multiple domains including HPC, IoT, Data Science, and AI.
Bringing Engineering Analysis Codes Into Real-Time Full-Scope SimulatorsGSE Systems, Inc.
Presented at the 2013 Nuclear Simulation and Training China Forum in Beijing. For more information on GSE's real-time simulators and engineering capabilities, go to www.gses.com, follow GSE on Twitter @GSESystems and connect on Facebook.com/GSESystems
EFFICIENT POWER MANAGEMENT TECHNIQUES SUCH AS SKIN TEMPERATURE AWARE POWER MANAGEMENT AND BATTERY BOOST FOR IMPROVED ENERGY EFFICIENCY [PERFORMANCE/WATT]
DEVELOPING PERFORMANCE ANALYSIS ENVIRONMENT BY REUSING EXISTING VERIFICATION ENVIRONMENT
HOLISTIC VIEW OF SOC VERIFICATION :
EVOLUTION OF UVM METHDOLOGY, UVM 1.2 AND CHALLENGES WITH MULTI LANGUAGE SUPPORT/AMS SUPPORT.
EDA INDUSTRY/TOOL CHALLENGES WITH HW-SW DEBUG, VP MODEL VERIFICATION.
H/W ASSISTED SIMULATION ACCELERATION, CHOOSING EMULATION CONFIGURATION FOR YOUR DESIGN.
Tyrone-Intel oneAPI Webinar: Optimized Tools for Performance-Driven, Cross-Ar...Tyrone Systems
Modern workloads are incredibly diverse and so are architectures. No single architecture is best for every workload. Maximizing performance takes a mix of architectures deployed in CPU, GPU, FPGA, and other future accelerators. Intel® oneAPI products deliver the tools needed to deploy applications and solutions across SVMS architectures. Learn about oneAPI and how they can be used in multiple domains including HPC, IoT, Data Science, and AI.
Bringing Engineering Analysis Codes Into Real-Time Full-Scope SimulatorsGSE Systems, Inc.
Presented at the 2013 Nuclear Simulation and Training China Forum in Beijing. For more information on GSE's real-time simulators and engineering capabilities, go to www.gses.com, follow GSE on Twitter @GSESystems and connect on Facebook.com/GSESystems
HC-4020, Enhancing OpenCL performance in AfterShot Pro with HSA, by Michael W...AMD Developer Central
Presentation Hc-4020, Enhancing OpenCL performance in AfterShot Pro with HSA, by Michael Wootton at the AMD Developer Summit (APU13) November 11-13, 2013.
IMAGE CAPTURE, PROCESSING AND TRANSFER VIA ETHERNET UNDER CONTROL OF MATLAB G...Christopher Diamantopoulos
This implemented DSP system utilizes TCP socket communication. Upon message reception, it decides the appropriate process to be executed based on cases which can be categorized as follows:
1) image capture
2) image transfer
3) image processing
4) sensor calibration
A user-friendly MATLAB GUI, named DIPeth, facilitates the system's control.
Preparing Codes for Intel Knights Landing (KNL)AllineaSoftware
Getting ready for the next generation of Intel Xeon Phi processors: we outline the steps to tune, profile and then optimize applications to target many core
LAS16-400: Mini Conference 3 AOSP (Session 1)Linaro
LAS16-400: Mini Conference 3 AOSP (Session 1)
Speakers: Thomas Gall, Bernhard Rosenkränzer
Date: September 29, 2016
★ Session Description ★
The Android Open Source Project is one community which is strategic to Linaro and it’s members. The purpose of this mini conference is to gather fellow Android engineers together from the community, member companies, and Linaro to discuss engineering activities and improve collaboration across different groups.
Within this mini conference we encourage discussion and presentations to advance engineering topics, forge consensus and educate each other.
The tentative agenda for this mini conference includes :
- Quick introduction
- Filesystems - Between requirements for encryption and standing concerns about degrading performance as an Android file system age, let’s have some discussion involving current data, known issues and towards improvements in this area for Android.
- HAL consolidation - Review current status and discuss next steps to work on.
One build for many devices: device/build configuration. Next features and platforms to add. Gaps in HiKey support vs. AOSP build.
- Graphics - YUV support in mesa and hwc.
- WiFi and sensor HAL status and next steps
- New developments with AOSP + the Kernel - With regards to the Google Common Kernel tree and upstream Linux kernel activities related to Android, there are a few topics up for discussion:
- - Updates on HiKey in AOSP
- - EAS in common.git & integration with AOSP userspace
- - New Sync API in 4.6+ kernels, and how it will affects graphics drivers
- AOSP transition to clang - As everyone knows GCC in AOSP has been deprecated. Let’s cover current status, issues and next steps. Let’s also discuss the elephant in the room, building the kernel with clang.
- Out of tree AOSP User space Patches - This is a discussion with the goal of organized action to see forward progress on AOSP user space patches that aren’t in AOSP for whatever reason.
- Android is used in some environments where booting can be frequent and affect the product experience. Do you want to wait for a minute while your car boots? We’ll spend time brainstorming on improving Android boot time.
★ Resources ★
Etherpad: pad.linaro.org/p/las16-400
Presentations & Videos: http://connect.linaro.org/resource/las16/las16-400/
★ Event Details ★
Linaro Connect Las Vegas 2016 – #LAS16
September 26-30, 2016
http://www.linaro.org
http://connect.linaro.org
AMD is introducing “Seattle,” a 64-bit ARM-based server System-on a –Chip (SoC) built on the same technology that powers billions of today’s most popular mobile devices.
System on Chip (SoC) for mobile phonesJeffrey Funk
These slides use concepts (e.g., scaling) from my (Jeff Funk) course entitled analyzing hi-tech opportunities to look at how reductions in the feature sizes for integrated circuits (ICs) are enabling increases in the functionality of IC chips and thus the placements of larger systems on them. In turn, these increases in functionality of ICs are enabling increases in the functionality of mobile phones while at the same time creating new challenges for IC and mobile phone suppliers.
The Microarchitecure Of FPGA Based Soft ProcessorDeepak Tomar
this presentation is on the Paper "The Microarchitecure Of FPGA Based Soft Processor" by Peter Yiannacouras, Jonathan Rose and
J Gregory Steffan
Dept. of Electrical and Computer Engineering
University of Toronto
It’s surprisingly straightforward to migrate feature code from the CPU to the DSP – and determine the resulting benefits to the end application. In this session we’ll demonstrate Qualcomm® Hexagon™ SDK installation, code generation, profiling and execution of dynamic code modules on a Qualcomm® Snapdragon™ hardware target, and you’ll learn how to analyze the resulting performance benefits. Qualcomm Snapdragon and Qualcomm Hexagon are products of Qualcomm Technologies, Inc.
Learn more about Hexagon SDK: https://developer.qualcomm.com/hexagon
Watch this presentation on YouTube:
https://www.youtube.com/watch?v=x6mKEWLzJM0
Implementation of Soft-core Processor on FPGADeepak Kumar
We can add a soft-core processor to a FPGA-based system after it's already designed. However, adding a hard-core processor requires either a different FPGA, or an additional chip on the board.
Shrinking the Distance between Customers and Great Open Networking Platforms
In the data center, open networking is delivering CapEx reductions, improving operational efficiency and OpEx, and enabling use of standard Linux tools. Join us to learn how recent advancements in open networking are shrinking the time and distance between great new switching platforms and the customers who benefit from modern technology, modern economics, and platforms that just work.
Learn more about the tremendous value Open Data Plane brings to NFV
Bob Monkman, Networking Segment Marketing Manager, ARM
Bill Fischofer, Senior Software Engineer, Linaro Networking Group
Moderator:
Brandon Lewis, OpenSystems Media
HC-4020, Enhancing OpenCL performance in AfterShot Pro with HSA, by Michael W...AMD Developer Central
Presentation Hc-4020, Enhancing OpenCL performance in AfterShot Pro with HSA, by Michael Wootton at the AMD Developer Summit (APU13) November 11-13, 2013.
IMAGE CAPTURE, PROCESSING AND TRANSFER VIA ETHERNET UNDER CONTROL OF MATLAB G...Christopher Diamantopoulos
This implemented DSP system utilizes TCP socket communication. Upon message reception, it decides the appropriate process to be executed based on cases which can be categorized as follows:
1) image capture
2) image transfer
3) image processing
4) sensor calibration
A user-friendly MATLAB GUI, named DIPeth, facilitates the system's control.
Preparing Codes for Intel Knights Landing (KNL)AllineaSoftware
Getting ready for the next generation of Intel Xeon Phi processors: we outline the steps to tune, profile and then optimize applications to target many core
LAS16-400: Mini Conference 3 AOSP (Session 1)Linaro
LAS16-400: Mini Conference 3 AOSP (Session 1)
Speakers: Thomas Gall, Bernhard Rosenkränzer
Date: September 29, 2016
★ Session Description ★
The Android Open Source Project is one community which is strategic to Linaro and it’s members. The purpose of this mini conference is to gather fellow Android engineers together from the community, member companies, and Linaro to discuss engineering activities and improve collaboration across different groups.
Within this mini conference we encourage discussion and presentations to advance engineering topics, forge consensus and educate each other.
The tentative agenda for this mini conference includes :
- Quick introduction
- Filesystems - Between requirements for encryption and standing concerns about degrading performance as an Android file system age, let’s have some discussion involving current data, known issues and towards improvements in this area for Android.
- HAL consolidation - Review current status and discuss next steps to work on.
One build for many devices: device/build configuration. Next features and platforms to add. Gaps in HiKey support vs. AOSP build.
- Graphics - YUV support in mesa and hwc.
- WiFi and sensor HAL status and next steps
- New developments with AOSP + the Kernel - With regards to the Google Common Kernel tree and upstream Linux kernel activities related to Android, there are a few topics up for discussion:
- - Updates on HiKey in AOSP
- - EAS in common.git & integration with AOSP userspace
- - New Sync API in 4.6+ kernels, and how it will affects graphics drivers
- AOSP transition to clang - As everyone knows GCC in AOSP has been deprecated. Let’s cover current status, issues and next steps. Let’s also discuss the elephant in the room, building the kernel with clang.
- Out of tree AOSP User space Patches - This is a discussion with the goal of organized action to see forward progress on AOSP user space patches that aren’t in AOSP for whatever reason.
- Android is used in some environments where booting can be frequent and affect the product experience. Do you want to wait for a minute while your car boots? We’ll spend time brainstorming on improving Android boot time.
★ Resources ★
Etherpad: pad.linaro.org/p/las16-400
Presentations & Videos: http://connect.linaro.org/resource/las16/las16-400/
★ Event Details ★
Linaro Connect Las Vegas 2016 – #LAS16
September 26-30, 2016
http://www.linaro.org
http://connect.linaro.org
AMD is introducing “Seattle,” a 64-bit ARM-based server System-on a –Chip (SoC) built on the same technology that powers billions of today’s most popular mobile devices.
System on Chip (SoC) for mobile phonesJeffrey Funk
These slides use concepts (e.g., scaling) from my (Jeff Funk) course entitled analyzing hi-tech opportunities to look at how reductions in the feature sizes for integrated circuits (ICs) are enabling increases in the functionality of IC chips and thus the placements of larger systems on them. In turn, these increases in functionality of ICs are enabling increases in the functionality of mobile phones while at the same time creating new challenges for IC and mobile phone suppliers.
The Microarchitecure Of FPGA Based Soft ProcessorDeepak Tomar
this presentation is on the Paper "The Microarchitecure Of FPGA Based Soft Processor" by Peter Yiannacouras, Jonathan Rose and
J Gregory Steffan
Dept. of Electrical and Computer Engineering
University of Toronto
It’s surprisingly straightforward to migrate feature code from the CPU to the DSP – and determine the resulting benefits to the end application. In this session we’ll demonstrate Qualcomm® Hexagon™ SDK installation, code generation, profiling and execution of dynamic code modules on a Qualcomm® Snapdragon™ hardware target, and you’ll learn how to analyze the resulting performance benefits. Qualcomm Snapdragon and Qualcomm Hexagon are products of Qualcomm Technologies, Inc.
Learn more about Hexagon SDK: https://developer.qualcomm.com/hexagon
Watch this presentation on YouTube:
https://www.youtube.com/watch?v=x6mKEWLzJM0
Implementation of Soft-core Processor on FPGADeepak Kumar
We can add a soft-core processor to a FPGA-based system after it's already designed. However, adding a hard-core processor requires either a different FPGA, or an additional chip on the board.
Shrinking the Distance between Customers and Great Open Networking Platforms
In the data center, open networking is delivering CapEx reductions, improving operational efficiency and OpEx, and enabling use of standard Linux tools. Join us to learn how recent advancements in open networking are shrinking the time and distance between great new switching platforms and the customers who benefit from modern technology, modern economics, and platforms that just work.
Learn more about the tremendous value Open Data Plane brings to NFV
Bob Monkman, Networking Segment Marketing Manager, ARM
Bill Fischofer, Senior Software Engineer, Linaro Networking Group
Moderator:
Brandon Lewis, OpenSystems Media
POLYTEDA LLC, a provider of semiconductor design software and PV-services announced the general availability of PowerDRC/LVS version 2.2.
This release is dedicated to delivering fill layer generation for multi-CPU mode, new KLayout integration functionality and other significant improvements for multi-CPU mode
System on Chip is a an IC that integrates all the components of an electronic system. This presentation is based on the current trends and challenges in the IP based SOC design.
The charter of the ODSA (Open Domain Specification Architecture) Workgroup is to define an open specification that enables building of Domain Specific Accelerator silicon using best-of-breed components from the industry made available as chiplet dies that can be integrated together as Lego blocks on an organic substrate packaging layer. The resulting multi-chip module (MCM) silicon can be produced at significantly lower development and manufacturing costs, and will deliver much needed performance per watt and performance per dollar efficiencies in networking, security, machine learning and other applications. The ODSA Workgroup also intends to deliver implementations of the specification as board-level prototypes, RTL code and libraries.
The charter of the ODSA (Open Domain Specification Architecture) Workgroup is to define an open specification that enables building of Domain Specific Accelerator silicon using best-of-breed components from the industry made available as chiplet dies that can be integrated together as Lego blocks on an organic substrate packaging layer. The resulting multi-chip module (MCM) silicon can be produced at significantly lower development and manufacturing costs, and will deliver much needed performance per watt and performance per dollar efficiencies in networking, security, machine learning and other applications. The ODSA Workgroup also intends to deliver implementations of the specification as board-level prototypes, RTL code and libraries.
[EWiLi2016] Towards a performance-aware power capping orchestrator for the Xe...Matteo Ferroni
In the last few years, multi-core processors entered into the domain of embedded systems: this, together with virtualization techniques, allows multiple applications to easily run on the same System-on-Chip (SoC). As power consumption remains one of the most impacting costs on any digital system, several approaches have been explored in literature to cope with power caps, trying to maximize the performance of the hosted applications. In this paper, we present some preliminary results and opportunities towards a performance-aware power capping orchestrator for the Xen hypervisor. The proposed solution, called XeMPUPiL, uses the Intel Running Average Power Limit (RAPL) hardware interface to set a strict limit on the processor’s power consumption, while a software-level Observe-Decide-Act (ODA) loop performs an exploration of the available resource allocations to find the most power efficient one for the running workload. We show how XeMPUPiL is able to achieve higher performance under different power caps for almost all the different classes of benchmarks analyzed (e.g., CPU-, memory- and IO-bound).
Full paper: http://ceur-ws.org/Vol-1697/EWiLi16_17.pdf
Tool-Driven Technology Transfer in Software EngineeringHeiko Koziolek
This talk presentst the tool-driven technology transfer process ABB Corporate Research applies in selected software engineering University collaborations. As an example, we have created an add-in to a popular UML tool and developed the tooling in close interaction with the target users. Centering the technology transfer around tool implementations brings many benefits such as the need to make conceptual contributions applicable and the ability to quickly benefit from the new concepts. A challenge to this form of technology transfer is the long-term commitment to the maintenance of the tooling, which we try to address by creating an open developer community. Tool-driven technology transfer projects have proven to be valuable a instrument of bringing advanced software engineering technologies into our organization.
OS for AI: Elastic Microservices & the Next Gen of MLNordic APIs
AI has been a hot topic lately, with advances being made constantly in what is possible, there has not been as much discussion of the infrastructure and scaling challenges that come with it. How do you support dozens of different languages and frameworks, and make them interoperate invisibly? How do you scale to run abstract code from thousands of different developers, simultaneously and elastically, while maintaining less than 15ms of overhead?
At Algorithmia, we’ve built, deployed, and scaled thousands of algorithms and machine learning models, using every kind of framework (from scikit-learn to tensorflow). We’ve seen many of the challenges faced in this area, and in this talk I’ll share some insights into the problems you’re likely to face, and how to approach solving them.
In brief, we’ll examine the need for, and implementations of, a complete “Operating System for AI” – a common interface for different algorithms to be used and combined, and a general architecture for serverless machine learning which is discoverable, versioned, scalable and sharable.
Similar to FUSION APU & TRENDS/ CHALLENGES IN FUTURE SoC DESIGN (20)
An Approach to Overcome Modeling Inaccuracies for Performance Simulation Sig...Pankaj Singh
RNM is finding prominence in functional verification signoff, However there is clear modeling gap when it comes to performance simulation of high-speed SerDes. Sometimes the pre-silicon simulation results show passing results with respect to Jitter tolerance (JTOL) specification which may not match the actual silicon validation results. These performance issues manifest due to inaccuracies of model where it may not comprehend the actual circuit behavior. There is no clear methodology to overcome these model gaps for performance simulation signoff.
This paper discusses in detail the techniques used to accurately model and verify high-speed SerDes systems for performance simulation.
Overcoming challenges of_verifying complex mixed signal designsPankaj Singh
Efficient and Innovative Digital Mixed-Signal (DMS) verification methodology is required to enable effective verification of RX path of SERDES. This presentation describes the usage of Real value models and Capture -Verify approach to verify complex high speed mixed signal design.
Real value models are the backbone of DMS methodology. Real value models are created for all critical modules in Receive path like Equalizer and Sampler and its associated peripheral modules. It is critical to make sure created models are functionally equivalent to respective designs. This is achieved by verifying each created model with respective designs for all functional modes. While the Real Value models are effective in meeting overcoming the simulation performance bottleneck by achieving 10x faster simulation time; the Nonlinearity factors of the front-end design are not represented accurately in discrete domain real value models for next generation of SerDes Design at very high data rate.
To overcome this problem, a novel approach called ‘capture and verify’ is used for verifying the jitter tolerance and eye parameters. In this approach, waveforms from spice level verification of Equalizer for different functional modes are captured and stored. These stored waveforms are used to generate run time table-based models to accurately represent the analog modules. These run time models are used in top-level simulations along with real value models thereby achieving required goal of simulation performance without compromising on accuracy of results.
The complete Design Verification (DV) environment is developed using UVM-e Methodology. Verification environment contains model for transmitter with all de-emphasis settings along with protocol compliant channels with multiple attenuations. DV infrastructure has hooks to plug-in required channel models to verify SERDES. This verification environment is also capable of verifying the clock data recovery (CDR) path of the design using protocol compliant jitter and Spread-Spectrum Clocking (SSC) stimulus.
The real value modelling bridges the gap between the performance requirements of the simulation and accuracy limitations of design. A significant speed-up in simulation performance is achieved (almost 10X in this case) by replacing with functionally equivalent real value models for mixed signal designs. Usage of Capture and Verify methodology with spice simulation waveforms for critical blocks ensures non-linearity of the next generation high speed SerDes design is well captured in simulations provide complete comprehensive solution for high speed mixed signal designs.
Qualifying a high performance memory subsysten for Functional SafetyPankaj Singh
Addressing the Challenges of Safety verification for LPDDR4.
✓Avoid traditional approach of starting functional safety after functional verification : Iterative and expensive development phase
1. Functional Safety Need to be Architected and not added later.
2. Safety Analysis must start prior to implementation. ‘Design for safety/verification’
3. Reuse & Synergize : Nominal and Functional Safety Verification.
✓Fault optimization with formal and other techniques is necessary to overcome challenges with scaling simulation and analysis.
✓Integrated push button fault simulation flow is need of hour and saves verification engineers time.
✓Analog defect modelling and coverage can be performed based on IEEE P2427.
Safety Verification and Software aspects of Automotive SoCPankaj Singh
IP-SoC Conference 2017 Grenoble
Automotive industry has evolved over last 100 years. Electronic systems were
introduced into the automotive industry in 1960. Since then the complexity has grown
many fold and today’s automobiles have as many as 150 programmable computing
elements or Electronic Control Units(ECUs) with several wiring connections.
The software content has also increased significantly with today’s car having more than
100 million of lines of software code.
This increased hardware and software complexity increases the risk of failure that could
impact negatively on vehicle safety. This has led to concerns regarding the validation of
failure modes and the detection mechanisms. Car maker and suppliers need to prove
that, despite increasing complexity, their electronic systems will deliver the required
functionality safely and reliably.
This presentation describes the challenges and methodology related to Safety
verification and Software development aspects of Automotive Microcontroller SoC.
1.Car Security
Understanding the Car Onboard Communication / Connection and inherent Security Weakness
2.Addressing the Security Concerns : System’s Viewpoint
Hardware Security Module & Secure Hardware Extension
Look at Software Principle of MAC and Associated Hardware
3.Achieving Security implementation checks via Software and Addressing the Hardware Safety aspect.
Closing the Loop for Security Safeness: Complete Solution to Ensure Security/Safety Compliance with Software
Panel:The secret of Indian leadership in Electronic Design skill... From Desi...Pankaj Singh
Panel Discussion: D&R IP-SoC, Bangalore 2015. Topic:The secret of Indian leadership in Electronic Design skill... From Design to Services to Embedded Software
Power Optimization with Efficient Test Logic Partitioning for Full Chip DesignPankaj Singh
This paper introduces efficient test logic partitioning to not only optimize and reduce the overall test power during silicon validation but also reduce power in functional mode by shutting off test logic. Approach used in optimizing test power has been successful in reducing overall functional mode leakage power by 50% without any additional area overhead or test time increase. Results shared are based on WIMAX full chip SoC design.
UiPath Test Automation using UiPath Test Suite series, part 4DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 4. In this session, we will cover Test Manager overview along with SAP heatmap.
The UiPath Test Manager overview with SAP heatmap webinar offers a concise yet comprehensive exploration of the role of a Test Manager within SAP environments, coupled with the utilization of heatmaps for effective testing strategies.
Participants will gain insights into the responsibilities, challenges, and best practices associated with test management in SAP projects. Additionally, the webinar delves into the significance of heatmaps as a visual aid for identifying testing priorities, areas of risk, and resource allocation within SAP landscapes. Through this session, attendees can expect to enhance their understanding of test management principles while learning practical approaches to optimize testing processes in SAP environments using heatmap visualization techniques
What will you get from this session?
1. Insights into SAP testing best practices
2. Heatmap utilization for testing
3. Optimization of testing processes
4. Demo
Topics covered:
Execution from the test manager
Orchestrator execution result
Defect reporting
SAP heatmap example with demo
Speaker:
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
Generative AI Deep Dive: Advancing from Proof of Concept to ProductionAggregage
Join Maher Hanafi, VP of Engineering at Betterworks, in this new session where he'll share a practical framework to transform Gen AI prototypes into impactful products! He'll delve into the complexities of data collection and management, model selection and optimization, and ensuring security, scalability, and responsible use.
Encryption in Microsoft 365 - ExpertsLive Netherlands 2024Albert Hoitingh
In this session I delve into the encryption technology used in Microsoft 365 and Microsoft Purview. Including the concepts of Customer Key and Double Key Encryption.
DevOps and Testing slides at DASA ConnectKari Kakkonen
My and Rik Marselis slides at 30.5.2024 DASA Connect conference. We discuss about what is testing, then what is agile testing and finally what is Testing in DevOps. Finally we had lovely workshop with the participants trying to find out different ways to think about quality and testing in different parts of the DevOps infinity loop.
Le nuove frontiere dell'AI nell'RPA con UiPath Autopilot™UiPathCommunity
In questo evento online gratuito, organizzato dalla Community Italiana di UiPath, potrai esplorare le nuove funzionalità di Autopilot, il tool che integra l'Intelligenza Artificiale nei processi di sviluppo e utilizzo delle Automazioni.
📕 Vedremo insieme alcuni esempi dell'utilizzo di Autopilot in diversi tool della Suite UiPath:
Autopilot per Studio Web
Autopilot per Studio
Autopilot per Apps
Clipboard AI
GenAI applicata alla Document Understanding
👨🏫👨💻 Speakers:
Stefano Negro, UiPath MVPx3, RPA Tech Lead @ BSP Consultant
Flavio Martinelli, UiPath MVP 2023, Technical Account Manager @UiPath
Andrei Tasca, RPA Solutions Team Lead @NTT Data
LF Energy Webinar: Electrical Grid Modelling and Simulation Through PowSyBl -...DanBrown980551
Do you want to learn how to model and simulate an electrical network from scratch in under an hour?
Then welcome to this PowSyBl workshop, hosted by Rte, the French Transmission System Operator (TSO)!
During the webinar, you will discover the PowSyBl ecosystem as well as handle and study an electrical network through an interactive Python notebook.
PowSyBl is an open source project hosted by LF Energy, which offers a comprehensive set of features for electrical grid modelling and simulation. Among other advanced features, PowSyBl provides:
- A fully editable and extendable library for grid component modelling;
- Visualization tools to display your network;
- Grid simulation tools, such as power flows, security analyses (with or without remedial actions) and sensitivity analyses;
The framework is mostly written in Java, with a Python binding so that Python developers can access PowSyBl functionalities as well.
What you will learn during the webinar:
- For beginners: discover PowSyBl's functionalities through a quick general presentation and the notebook, without needing any expert coding skills;
- For advanced developers: master the skills to efficiently apply PowSyBl functionalities to your real-world scenarios.
Dev Dives: Train smarter, not harder – active learning and UiPath LLMs for do...UiPathCommunity
💥 Speed, accuracy, and scaling – discover the superpowers of GenAI in action with UiPath Document Understanding and Communications Mining™:
See how to accelerate model training and optimize model performance with active learning
Learn about the latest enhancements to out-of-the-box document processing – with little to no training required
Get an exclusive demo of the new family of UiPath LLMs – GenAI models specialized for processing different types of documents and messages
This is a hands-on session specifically designed for automation developers and AI enthusiasts seeking to enhance their knowledge in leveraging the latest intelligent document processing capabilities offered by UiPath.
Speakers:
👨🏫 Andras Palfi, Senior Product Manager, UiPath
👩🏫 Lenka Dulovicova, Product Program Manager, UiPath
FIDO Alliance Osaka Seminar: Passkeys at Amazon.pdf
FUSION APU & TRENDS/ CHALLENGES IN FUTURE SoC DESIGN
1. FUSION APU AND TRENDS/
CHALLENGES IN FUTURE
SOC (PROCESSOR) DESIGN
Pankaj Singh,
Acknowledgement:
Denis Foley. Sr. Fellow, AMD
9th International SoC Conference
2nd & 3rd November 2011
2. 2 | 9th Intl. SoC Conference| Nov 2nd,3rd, 2011
TODAY’S TOPICS
Trends:
– Three Eras of Processor Performance
– Evolution of Heterogeneous Computing
FSA and Open Standard:
– Why Fusion ?
– Open Standard, Open CL
Power, Performance
High Speed, Scalable Interconnect: NoC’s
3-D Stacking
SoC Trends & Challenges
– Verification Effort
– IP Integration
– TLM, RTL Co-simulation challenges.
3. 3 | 9th Intl. SoC Conference| Nov 2nd,3rd, 2011
TRENDS: THREE ERAS OF PROCESSOR PERFORMANCE
Single-Core
Era
Single-threadPerformance
?
Time
we are
here
o
Enabled by:
Moore’s Law
Voltage Scaling
MicroArchitecture
Constrained by:
Power
Complexity
Multi-Core
Era
ThroughputPerformance
Time
(# of Processors)
we are
here
o
Enabled by:
Moore’s Law
Desire for Throughput
20 years of SMP arch
Constrained by:
Power
Parallel SW availability
Scalability
Heterogeneous
Systems Era
TargetedApplication
Performance
Time
(Data-parallel exploitation)
we are
here
o
Enabled by:
Moore’s Law
Abundant data parallelism
Power efficient GPUs
Currently constrained by:
Programming models
Communication overheads
4. 4 | 9th Intl. SoC Conference| Nov 2nd,3rd, 2011
TRENDS: EVOLUTION OF HETEROGENEOUS COMPUTINGArchitectureMaturity&ProgrammerAccessibility
PoorExcellent
2012 - 20202009 - 20112002 - 2008
Graphics & Proprietary
Driver-based APIs
Proprietary Drivers Era
“Adventurous” programmers
Exploit early programmable
“shader cores” in the GPU
Make your program look like
“graphics” to the GPU
CUDA™, Brook+, etc
OpenCL™, DirectCompute
Driver-based APIs
Standards Drivers Era
Expert programmers
C and C++ subsets
Compute centric APIs , data
types
Multiple address spaces with
explicit data movement
Specialized work queue based
structures
Kernel mode dispatch
Fusion™ System Architecture
GPU Peer Processor
Architected Era
Mainstream programmers
Full C++
GPU as a co-processor
Unified coherent address space
Task parallel runtimes
Nested Data Parallel programs
User mode dispatch
Pre-emption and context
switching
More uptodate information on FSA:
http://developer.amd.com/afds/pages/keynote.aspx#/Dev_AFDS_Reb_2
5. 5 | 9th Intl. SoC Conference| Nov 2nd,3rd, 2011
FSA & OPEN STANDARD: ENTER FUSION
Dual Core CPU Northbridge DirectX®11 GPU
FUSION APU
(Accelerated Processing Unit)
Heterogeneous compute engine combining
x86 compute and parallel processing
capabilities of the GPU on a single die
6. 6 | 9th Intl. SoC Conference| Nov 2nd,3rd, 2011
FSA & OPEN STANDARD: WHY FUSION?
6
Integrating CPUs, Northbridge and GPU enables:
– Unified Memory
– High-bandwidth, low latency access by GPU
– Saves on interface power and PHY area
– Shared Power Control and TDP envelope
Potential bandwidth bottleneck
Relatively long memory latency
7. 7 | 9th Intl. SoC Conference| Nov 2nd,3rd, 2011
COMMITTED TO OPEN STANDARDS
AMD drives open and de-facto
standards
– Compete on the best
implementation
Open standards are the basis for
large ecosystems
Open standards always win over
time
– SW developers want their
applications to run on multiple
platforms from multiple
hardware vendors
DirectX®
8. 8 | 9th Intl. SoC Conference| Nov 2nd,3rd, 2011
OPENCL™ AND FSA
FSA is an optimized platform
architecture for OpenCL™
– Not an alternative to OpenCL™
OpenCL™ on FSA will benefit from
– Avoidance of wasteful copies
– Low latency dispatch
– Improved memory model
– Shared pointers
FSA also exposes a lower level
programming interface, for those
that want the ultimate in control
and performance
Optimized libraries may choose
the lower level interface
10. 10 | 9th Intl. SoC Conference| Nov 2nd,3rd, 2011
POWER-THERMAL EFFECTS IN SYSTEMS ON CHIPS
¡ Local failures !
Part not working
Complex SoCs: High power density
Non-uniform power dissipation: Hotspots
Spatial gradients: Cause malfunctions
High on-chip temperatures cause
malfunctions affecting reliability.
Power consumption depends on
frequency
Setting frequencies to control power and
temperature
11. 11 | 9th Intl. SoC Conference| Nov 2nd,3rd, 2011
OPTIONS FOR POWER SAVINGS
Convergence of Performance and Low Power
– Notebook->Netbook-> Tablet
Tablet<-Smartphone
12. 12 | 9th Intl. SoC Conference| Nov 2nd,3rd, 2011
PERFORMANCE AND POWER
S3 idle Static
Screen
MM07 Media
Playback
Full
Compute
APU Power vs. Use Case
Performance
Power
Performance versus Power Efficiency
Power Management versus Power reduction
Performance & Thermal Design Power
14. 14 | 9th Intl. SoC Conference| Nov 2nd,3rd, 2011
NOC’S: FROM BUSES TO NETWORKS:
[Friedman Harel:10]
Note: This slide presents industry specific information does not relate to AMD NoC status
15. 15 | 9th Intl. SoC Conference| Nov 2nd,3rd, 2011
NOC CHALLENGES: CAD TOOLS
Capturing application traffic.
Which Topology ?
Mapping? Routes to use?
Fixing communication
architecture : parameters.
Verification for correctness, performance.
Build models.
QoS under un-reliable conditions.
Key to success: Automate & integrate the steps.
Mesh Topology
homogeneous systems, with
regular tiles
Customized Topology
heterogeneous systems, with
different cores & irregular FP
Software Services
Mapping, QoS, middleware...
Architecture
Packeting, buffering, flow control...
Physical Implementation
Synchronization, wires, power...
CAD Tools
16. 16 | 9th Intl. SoC Conference| Nov 2nd,3rd, 2011
Synchronous Delay Insensitive
Global None
Timing Assumptions
Less Detection
Local Clocks, Interaction
with data (becoming aperiodic)
A complete spectrum of approaches to system-timing exist
[Mullins06-07]
NOC CHALLENGES: BEYOND GLOBAL SYNCHRONY
Delay Insensitive
18. 18 | 9th Intl. SoC Conference| Nov 2nd,3rd, 2011
3-D STACKING
Supporting Heterogeneous computing: high density, high performance,
high memory B.W requirement.
3-D NoC’s option
Futuristic view:
Integrating Bio-sensor
Note:
This slide presents industry specific information does not relate to AMD 3-D stacking status
20. 20 | 9th Intl. SoC Conference| Nov 2nd,3rd, 2011
WHAT’S NEW IN SOC DESIGN?
Larger and more complex chips with heavy use of pre-existing cores.
Heavy use of multi core processors and DSPs.
Complex Interconnect.
Shorter time to market and Smaller design teams.
… and software.
Leads to:
– Increased verification effort: Debugging is harder.
– Integration is more difficult.
– Need for scalable and high speed interconnect.
– SW / HW co-simulation is a major issue.
– Power –Performance challenge.
– How do we treat the system software?
21. 21 | 9th Intl. SoC Conference| Nov 2nd,3rd, 2011
VERIFICATION EFFORT
Debugging
– Seamless debug across
h/w and software[especially SW]
Testbench Development:
– Several methodologies
VMM,OVMUVM.
New developments
[Unified strategy]
– UCIS,UVM TLM2.0
– Coverage trend
Address Gaps in VHDL,
System C coverage
22. 22 | 9th Intl. SoC Conference| Nov 2nd,3rd, 2011
VERIFICATION EFFORT
Creating/Running Testcase:
– Direct & Random
– Run time improvement
Save-restore.
Verification Cycle per second instead of Cycles per second:
Configuring environment to dynamically select relevant
design/core.
Alternate options
23. 23 | 9th Intl. SoC Conference| Nov 2nd,3rd, 2011
Emulation Focus Areas:
1. Tests/regression run with Long run time
2. Corner case bugs that may escape traditional verification
3. Replicating System level scenarios
Ongoing Initiatives/Need:
1.Seemless support for assertions.
2.Improve portability between Simulation & Emulation
3. Common model from TLM-HDL-Emulation
VERIFICATION EFFORT
Alternate Options
24. 24 | 9th Intl. SoC Conference| Nov 2nd,3rd, 2011
IP INTEGRATION CHALLENGE
Integration of IP :
– Multiple IP’s, various configurations, design languages
– IP’s to be in Sync: macro’s , libraries.
– Complexity increases with mixed language designs
SYSTEM
C
SVLO
G
VERILOG
VHDL
Unique Strengths
of Languages
Diversity of Design
Teams
Importing Existing
IP
Legacy Testbench
Environment
25. 25 | 9th Intl. SoC Conference| Nov 2nd,3rd, 2011
IP INTEGRATION CHALLENGE COMPARISON OF CHOICES
Direct
Instantiation
SV Bind
Construct
SystemC
Control/Observe
SCV-
Connect()
SC-DPI
Source Code
Available
Yes Yes Yes Yes Yes
One IP
Compiled
Yes Yes Yes Yes Yes
Both IP
Compiled
No Yes No No No
Performance ++++ (3) +++ (2) + (1) + (1) +++++(4)
Delta Delay Yes Yes No No No
Languages
Supported
SV, SC,
VHDL
SV, SC,
VHDL
SC + SV/VHDL
SC +
SV/VHDL
SC + SV
Gap: No standardized automated methodology for integration.
Recommended Approach:
• Understand IP blocks: language, source code availability.
• Understand connection: 1-1, distributed, method port
• Option for optimized solution to quickly build a system
26. 26 | 9th Intl. SoC Conference| Nov 2nd,3rd, 2011
IP INTEGRATION CHALLENGE: GAPS WITH ANALOG IP
INTEGRATION IN SOC
Table1. Gaps with Analog IP Integration in SoC
Gaps Root Cause
Testchip setup
-Testchip scenario is different
-Tester used for testchip differs
Inbuilt debug
-Incomplete inbuilt SoC test/debug capability or derisk option for basic
functionality such as PLL clock
IP I/F verification -Incomplete test setup
Review process
-No common detailed review process between IP and SoC team. Incorrect
assumption based on past analog IP working silicon
IP Modelling
-Mismtach in version between IP simulation model and spice netlist
-Limitations of behavioral model to replicate actual analog IP functionality
-Timing issue
-DFT issue
EDA tools -Gaps in analog and digital simulation environment
27. 27 | 9th Intl. SoC Conference| Nov 2nd,3rd, 2011
Verification Environment Bring-up
– Automated Assertions for early checks.
– Review forces, tie-off and relevant checkers from IP to SoC
– Bottleneck for SoC team to get started with verification: Option to use
fake model for initial bring up. Usage of system model.
– Super Block Concept: pre-verified IP blocks at similar frequency &
interface
Requirement:
Current solution: In-house methodology and process. No clear solution
from EDA vendors.
IP INTEGRATION CHALLENGE
IP
Block1
IP
Block2
Minimum
Manual
Effort
Hookup
Using ICU
No BUGS!
28. 28 | 9th Intl. SoC Conference| Nov 2nd,3rd, 2011
TLM, RTL Co-simulation
Traditional use of System level models : Architecture profiling &
Performance Analysis
Increasing Demand for Co-simulation: Tradeoff between Accuracy and
Performance.
Open Challenges
Different level of Abstraction.
Need for improvement in Integration methodology and Test bench
development
Seamless Debug and Coverage methodology.
Using System Level model for HDL generation
Legacy system model not written with conversion in mind.
Current limitation: Incomplete translation.
Lack of reliable Equivalence Check tool.
Need: Merge top down (SystemC) and bottom-up (System Verilog)
methodology/flow.
Gaps/Work to do: How to do Power analysis
30. 30 | 9th Intl. SoC Conference| Nov 2nd,3rd, 2011
REFERENCES
[1] Wilson Research Group-MGC study blog 2011.
[2] AMD Coolchip2011 presentation. Denis Foley, AMD Sr. Fellow.
[3] Fusion Processors and HPC-2011, Chuck Moore, AMD Corporate
Fellow & Technology Group CTO
[3] AMD Fusion Developer Summit 2011. Phil Rogers, AMD Corporate
Fellow
[4] Fully Asynchronous framework for GALS network on chip. Friedman H
[5]Future of EE, NoC’s presentation. Dr. Srinivasan Murali
[6] Analog IP integration in SoC, IP reuse’09. Mixed language IP integration
DVCoN 2010. Extending Fucntional coverage to SystemC, VHDL-IP’10.
Pankaj S
31. 31 | 9th Intl. SoC Conference| Nov 2nd,3rd, 2011
GLOSSARY
GPU – Graphics processing unit
APU: Accelerated Processing Unit
Open CL: Open Computing Language
TDP – Thermal Design power – a measure of a design
infrastructure’s ability to cool a device
NoC: Network On Chip
TLM: Transaction Level Modeling
Turbo Core – AMD boost mechanism
QoS: Quality of Service
UVM: Universal Verification Methodology
UCIS: Unified Coverage Interoperability Standard