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Seminario utovrm
The document discusses system level design methodologies. It recommends implementing collaboration tools for large teams, defining version control strategies, and verification methodologies. For architectural design, it advises breaking the design into subsystems, defining each subsystem's functionality and interfaces. It also discusses collaboration tools, version control, verification approaches, documentation best practices, and considering open source solutions.
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Seminario utovrm
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- 2. Agenda Part 1 Microprocessor andsilicon technology Evolution Memories Bus architectures System On Chip Part 2 GPU FPGA Architectural design Collaboration tools Open Source 02/02/2015
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- 4. Electronic System Design Architecturaldesign • Break down the design in subsystems • Define subsystems functionality • Define interfaces (Busses, protocols, APIs etc) Methodologies • Implement collaboration tools for large, dislocated teams • Define version control strategies • Define verification methodologies Experience is key NEVER reinvent the wheel Introduction 02/02/2015
- 5. History In the beginning… Discretecomponents (resistors, transistors) Multiple transistors to form a single gate Even a simple counter required multiple boards 02/02/2015
- 6. History The integrated circuit(1950-1960) Invented in 1950 Technology available in 1960 Multiple Logic gates in a single device (chip) 02/02/2015
- 7. Notes • Great inventionsare visionary • Not necessarily an invention is feasible immediately • Designer shall foresee technological breakthroughs 02/02/2015
- 8. History Intel 8086 (1978) 29Ktransistors, 3 µm 10 MHz First “true” 16 bit microprocessor Required several external peripherals • Interrupt controller • DMA • Timer Backwards compatible with 8080 (1974) • First “usable” microprocessor, 4500 transistors, 10 µm • Required +12V and -5V supplies • 2 MHz 02/02/2015
- 9. Notes • First microprocessorsare 40 years old • Latest x86 core i7 is backwards compatible with something from 36 years ago! 02/02/2015
- 10. History Programmable Logic Array(1977) Fuse based Can implement any combinatorial logic Programmable at production time 02/02/2015
- 11. History PLD (1983) More complexthan PLA, reprogrammable Introduce macrocell concept • Small PLA with a Flip Flop • External interconnect 02/02/2015
- 12. History LCA (1985) Programmable seaof gates, 1µm RAM based with external configuration memory Up to 7600 logic gates (484 CLBs) 02/02/2015
- 13. Notes • Moving fromOTP to reprogrammable made big difference • Programmable logic is key when ASSPs are not available • Same design flow as ASICs 02/02/2015
- 14. History Dynamic RAM Invented in1966, First useful device in 1973 Drastically reduces transistor count from SRAM Requires refresh Multiplexed addressing • Reduces access time • Increases latency Banking • Read/write multiple rows at the same time 02/02/2015
- 15. History DRAMs or HDDscan have very long access times Random access to high latency devices kills performance Access to adjacent data requires very low latency Cache memory Whenever random data is requested, cache stores adjacent locations in «cache lines» Subsequent accesses to data in cache has low latency Multiple levels of cache improve performance 02/02/2015
- 16. Notes • Thinking outsidethe box allows revolutionary solutions • Tradeoffs are acceptable when benefits prevail • New technologies limitations stimulate more innovation 02/02/2015
- 17. History Intel 80486 (1989) 1.2Mtransistors, 1µm 50 MHz / 40 MIPS First to embed cache (16KB) • Reduce DRAM latency penalty First to embed FPU 32 bit data bus 02/02/2015
- 18. Notes • 10x technologyshrink in 15 years (101µm) • Embedding of widely used external coprocessors 02/02/2015
- 19. History Pentium (1993) 3.3M transistors,800nm 66MHz, no direct connection to memory In 1996 introduced MMX Distributed architectures Microprocessor Memory interface bridge Peripheral and bus bridge External superIO 02/02/2015
- 20. Notes • Processor doesn’tinterface directly with memory anymore • Northbridge routes processor accesses among memory and high speed busses abstracting them • Peripherals get integrated in Southbridge 02/02/2015
- 21. History Parallel bus topology(ISA, PCI, AGP) Separate or multiplexed address/data Limited by signaling technology • Few MHz with TTL • Up to 150 MHz with LVCMOS Dual and Quad data rate to further improve bandwidth (mainly on memories) • Some use of differential signaling 02/02/2015
- 22. History Peripheral Component Interconnect Configurationspace • Automatic card detection and configuration • Extended card information • Standardized register set Dynamic device address mapping • No more conflicts among multiple cards on the same bus Introduces bursting 02/02/2015
- 23. Serial busses (PCIe,USB, HDMI, etc) Smaller number of traces Very low voltage differential signaling Clocked or self clocking Multi Gbit per lane PCIe • 1.0 – 2GBit/sec per lane • 2.0 – 4GBit/sec per lane • 3.0 – 8Gbit/sec per lane USB • 1.0 – 12 Mbit/sec • 2.0 – 480 Mbit/sec • 3.0 – 5GBit/sec History 02/02/2015
- 24. History 02/02/2015 PCI Express Introduces layered,packetized bus Star connection rather than one to many Allows tree configuration via PCI-PCI bridges Scalable bandwidth • Pin compatible connectors from 1 to 16 lanes • Increasing bit rate at each generation Overhead • Protocol & flow control • Encoding – 20% on Gen1&2 (8b10b) – 1.54% on Gen3 (128/130)
- 25. Notes • Communication betweensubsystems is key • Bandwidth can be increased without brute force • High speed, low voltage serial is faster and more energy efficient than parallel LVCMOS 02/02/2015
- 26. System on Chip Systemon Chip Microprocessor plus multiple peripherals and memory in a single chip IP blocks from multiple vendors are integrated in a single device Typical Smartphone SoC Processor from ARM GPU from Adreno Peripherals from Synopsys etc 02/02/2015
- 27. Interconnect Interconnection between IPblocks Ensure interoperability Maximize performance Address system complexity Multiple masters Locked transfers Cache coherency Testability Multicore debugging System trace Performance counters 02/02/2015
- 28. AXI Interconnect processors andhigh performance peripherals Multilayer matrix configuration AXI-Stream Streaming interface for packetized data flow Multiple data widths within same interconnect Backpressure support APB Interconnect low speed peripherals ATB Add tracing capability to any peripheral Interconnect 02/02/2015
- 29. Notes • Single chipintegrates all peripherals except memories • IP blocks from different vendors • Interconnect standardization (AMBA) • Test and debugging challenges 02/02/2015
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- 35. Today Systems are notonly made of Hardware 02/02/2015
- 36. Notes • Big -Little Architecture • Heterogeneous processors for different tasks • Codecs implemented in software • Application specific interfaces 02/02/2015
- 37. Quiz Time Most commonperformance bottlenecks 02/02/2015
- 38. Bottlenecks Memory Latency DDR clockspeeds exceed multiple GHz Column access time in the order of 5ns Row access time still in the order of 50ns Can be worked around with multiple levels of Cache memory Bandwidth Clock frequency is limited by technology Large busses are expensive Can be worked around with distributed memory 02/02/2015
- 39. GPUs Graphics Processing Unit Startedas dedicated vertex processors Evolved thowards SW programmable shaders Now used for massively parallel computation • OpenCL • Cuda Massively parallel Hundreds of parallel processors Multiple chips can be teamed for increased performance 02/02/2015
- 40. Today GPU Architecture Each Corehas high speed memory Cores grouped in clusters each cluster has local memory Each cluster can access device memory Host memory can be transferred to device memory via DMA Different levels of memory latency Each core in a cluster executes the same code 02/02/2015
- 41. Today GK110 Kepler (Nvidia) 7Gtransistors (28nm) 1.5MB on chip L2 cache 15 SMX units (64KB RAM each) • 192 single precision cores • 64 double precision cores • 32 Special function units + 32 load/store units External DDR5 6x64 bit memory controllers Up to 6 GHz clock speed 02/02/2015
- 42. Notes • Peripherals maybe more complex than main processor • Eliminating bottlenecks by architecture, not just brute force • Transforming dedicated HW in SW programmable devices creates value 02/02/2015
- 43. Today Soc FPGA High gatecount FPGA+Dual core Cortex A9 • Lower integration than ASSPs • Higher Flexibility than ASSPs Direct interconnection between FPGA and Processor • Possibility to accelerate software with FPGA IP • Lower system cost implementing in software less critical Ips • On the fly reprogramming to repurpose hardware on demand 02/02/2015
- 44. Trends High density FPGA+SoC 14nm trigate Embedded 64 bit quad core Cortex A53 1 GHz system speeds 56 GBps transceivers Support for 2.7 TBps HMC Support for 1.3 TBps DDR4 02/02/2015
- 45. Trends Silicon shrink notfavorable anymore 02/02/2015
- 46. Notes • Integration ofhard IP with programmable fabric • ASIC design cost skyrocketing is favoring FPGAs • Large library of IP cores (including open source) • FPGA to accelerate critical algorithms 02/02/2015
- 47. Trends Silicon feature sizereaching single atom level Quantum effects not negligible anymore Light sources for lithography unavailable New technologies to increase density 02/02/2015
- 48. Trends 02/02/2015 Stacked die, MCM Multipledies in a single package Wired interconnect 3d interconnect Interposers through silicon vias
- 49. Trends Hybrid memory cube Integratememory + controller in a single package Optimize memory performance (speed/power) Connect multiple concurrent processors to a single device 02/02/2015
- 50. Summary • Chip densityis increasing regardless of physical limits • Systems are gradually being condensed to a single chip • Chips requiring multiple technologies are manufactured with MCM or 3D processes • System components from multiple vendors are integrated in single chips • Software IS a system component 02/02/2015 What we learnt
- 51. Summary • Whenever Moore’slaw is hitting a wall breakthroughs keep it going • Thinking outside the box is vital for innovation • System design requires knowledge of leading edge technologies • System optimization requires in depth knowledge IP block functionality at all levels 02/02/2015
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- 54. Theory Electronic System Design Methodologies •Implement collaboration/Knowledge management tools • Define version control strategies • Define verification methodologies Architectural design • Break down the design in subsystems • Define subsystems functionality • Define interfaces (Busses, protocols, APIs etc) Subsystem implementation • Unit test design • RTL coding • Simulation • Synthesis and timing closure (ASIC/FPGA) 02/02/2015
- 55. Methodologies System design requiresorganization Even small groups can have communication issues Even a single developer can miss information Collaboration/Knowledge management tools Requirement and bug tracking Revision control Project planning Build automation 02/02/2015
- 56. Methodologies Requirement tracking Keep trackof specifications Clearly define dependencies Help partitioning in smaller tasks Bug Tracking Track issues and their solutions • Solutions to old problems can shorten new ones • Knowledge of issues can prevent repeating mistakes Clearly identify which changes have been adopted for a specific issue • Regression testing 02/02/2015
- 57. Methodologies – VersionControl Version Control Keep track of modifications and their reasons • Always comment your commits • Possibly reference bug tracker Allow multiple developers to work concurrently Branch/tag • Branching allows separate development environments for each developer • Developers can commit broken code in branches • Merge branches only when code is reliable • Tag when code is stable or on milestones 02/02/2015
- 58. Methodologies - verification Verification Testingis crucial to ensure quality Each IP shall include its test unit Systems shall have test benches Test cases shall be carefully planned Coverage shall be known Coding tests can take more time than coding IP block Plan testing before coding Better specifications and clearer requirements Quality is NOT a cost02/02/2015
- 59. Methodologies - Documentation Alwaysdocument your work! Sharing knowledge improves teamwork Documentation adds value to your work You can’t remember everything Issues Synchronization with artifact versions Completeness 02/02/2015
- 60. Methodologies - Documentation Doxygen Documentyour code within the code Automatic hierarchy documentation Can be used with most programming languages • Can be extended to any file with plugins Can generate graphs with dot plugin Multiple outputs (PDF, Word, HTML, etc) Automatic generation always in sync with code 02/02/2015
- 61. Architectural design Before youstart… Search for existing solutions • Literature • Patents • Open source List requirements • Define input and outputs • Clearly understand criticalities List use cases • Define what resources are required for each scenario 02/02/2015
- 62. Architectural design Partition designin independent units Small • Easy to maintain • Simple to understand Reusable • Generalize a problem whenever possible • Create a library of tested, robust building blocks Documented • Possibly use self documentation tools • Test bench with use cases 02/02/2015
- 63. Architectural design -Interfaces Always try to use standard interfaces Blocks can be reused more easily Understand implications of an interface architecture If non standard interface is required… Define a standard (and document it) Check it against known use cases Explore interface weak points and benefits 02/02/2015
- 64. Open Source Benefits Collaborative design improvesquality, stability through peer review Huge code base for software and hardware IP Drawbacks Heterogeneous code styles and interfaces No warranty on quality/functionality Limited support from community 02/02/2015
- 65. Open Source Business models OpenSource libraries and interfaces • Company releases parts of code to community • Community improves code functionality and reliability • Establish trust with customers and partners Open Source applications and platforms • Sell support and customization services • Sell HW products • Gain visibility and business opportunities • Possibility of mixed Open/Closed source approach 02/02/2015
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