This implemented DSP system utilizes TCP socket communication. Upon message reception, it decides the appropriate process to be executed based on cases which can be categorized as follows:
1) image capture
2) image transfer
3) image processing
4) sensor calibration
A user-friendly MATLAB GUI, named DIPeth, facilitates the system's control.
It’s surprisingly straightforward to migrate feature code from the CPU to the DSP – and determine the resulting benefits to the end application. In this session we’ll demonstrate Qualcomm® Hexagon™ SDK installation, code generation, profiling and execution of dynamic code modules on a Qualcomm® Snapdragon™ hardware target, and you’ll learn how to analyze the resulting performance benefits. Qualcomm Snapdragon and Qualcomm Hexagon are products of Qualcomm Technologies, Inc.
Learn more about Hexagon SDK: https://developer.qualcomm.com/hexagon
Watch this presentation on YouTube:
https://www.youtube.com/watch?v=x6mKEWLzJM0
It’s surprisingly straightforward to migrate feature code from the CPU to the DSP – and determine the resulting benefits to the end application. In this session we’ll demonstrate Qualcomm® Hexagon™ SDK installation, code generation, profiling and execution of dynamic code modules on a Qualcomm® Snapdragon™ hardware target, and you’ll learn how to analyze the resulting performance benefits. Qualcomm Snapdragon and Qualcomm Hexagon are products of Qualcomm Technologies, Inc.
Learn more about Hexagon SDK: https://developer.qualcomm.com/hexagon
Watch this presentation on YouTube:
https://www.youtube.com/watch?v=x6mKEWLzJM0
Learn about the new 28-nm Stratix V FPGA family from Altera. Built for bandwidth, this family includes 28-Gbps transceivers, embedded HardCopy blocks, and variable-precision DSP blocks.
Energy efficient AI workload partitioning on multi-core systemsDeepak Shankar
o create an AI system, the semiconductor, software, and systems team need to work together. Multi-core systems can provide extremely low latency and higher throughput at lower power consumption. But concurrent access to shared resources by multiple of AI workloads running on different cores can create higher worst-case execution time (WCET) and causes multiple system failures. Architecture exploration can be used to efficiently balance the compute, communication, synchronization, and storage. In this Webinar, we will be using Workloads from automotive, and data centers to demonstrate the methodology.
VisualSim Architect enables designers to assemble architecture models that extend from the smallest IoT to full automotive, and Radar systems to Data Centers. These models will include any combination of software, processors, ECU, RTOS and networks. Using this platform, software designer can explore the partitioning of the AI tasks (software or model) on to cores based on the latency, bandwidth, and power constraints. Within the IoT, the processor, A/D, Bluetooth and software can be modeled while an automotive design will require the network, ECU and firmware. Both have a unique mechanism to define the traffic, test scenarios and AI workloads. Hardware engineers can select cores, cores per cluster, cache hierarchy, memory controller, accelerators, and the interface topology. Software engineers can tune the partitioning, synchronization overhead, memory access schedules and scheduling.
SDVIs and In-Situ Visualization on TACC's StampedeIntel® Software
Speaker: Paul Navrátil, Texas Advanced Computing Center (TACC)
The design emphasis for supercomputing systems has moved from raw performance to performance-per-watt, and as a result, supercomputing architectures are converging on processors with wide vector units and many processing cores per chip. Such processors are capable of performant image rendering purely in software. This improved capability is fortuitous, since the prevailing homogeneous system designs lack dedicated, hardware-accelerated rendering subsystems for use in data visualization. Reliance on this “software-defined” rendering capability will grow in importance since, due to growing data sizes, visualizations must be performed on the same machine where the data is produced. Further, as data sizes outgrow disk I/O capacity, visualization will be increasingly incorporated into the simulation code itself (in situ visualization).
This talk presents recent work in high-fidelity visualization using the OSPRay ray tracing framework on TACC’s local and remote visualization systems. We present work using OSPRay within ParaView Catalyst in situ framework from Kitware, including capitalizing on opportunities to reduce data costs migrating through VTK filters for visualization. We highlight the performance opportunities and advantages of Intel® Advanced Vector Extensions 512, the memory system improvements possible with Intel® Xeon Phi™ processor multi-channel DRAM (MCDRAM) and the Intel® Omni-Path Architecture interconnect.
Best Practices and Performance Studies for High-Performance Computing ClustersIntel® Software
This session focuses on key system tunables for maximizing application performance of high-performance computing (HPC) workloads, and addresses porting, optimizing, and running applications to maximize performance. We present practical tips and techniques for building and running applications on multicore processors. We analyze sample performance and scaling data from various applications, and identify the best options.
Learn about the new 28-nm Stratix V FPGA family from Altera. Built for bandwidth, this family includes 28-Gbps transceivers, embedded HardCopy blocks, and variable-precision DSP blocks.
Energy efficient AI workload partitioning on multi-core systemsDeepak Shankar
o create an AI system, the semiconductor, software, and systems team need to work together. Multi-core systems can provide extremely low latency and higher throughput at lower power consumption. But concurrent access to shared resources by multiple of AI workloads running on different cores can create higher worst-case execution time (WCET) and causes multiple system failures. Architecture exploration can be used to efficiently balance the compute, communication, synchronization, and storage. In this Webinar, we will be using Workloads from automotive, and data centers to demonstrate the methodology.
VisualSim Architect enables designers to assemble architecture models that extend from the smallest IoT to full automotive, and Radar systems to Data Centers. These models will include any combination of software, processors, ECU, RTOS and networks. Using this platform, software designer can explore the partitioning of the AI tasks (software or model) on to cores based on the latency, bandwidth, and power constraints. Within the IoT, the processor, A/D, Bluetooth and software can be modeled while an automotive design will require the network, ECU and firmware. Both have a unique mechanism to define the traffic, test scenarios and AI workloads. Hardware engineers can select cores, cores per cluster, cache hierarchy, memory controller, accelerators, and the interface topology. Software engineers can tune the partitioning, synchronization overhead, memory access schedules and scheduling.
SDVIs and In-Situ Visualization on TACC's StampedeIntel® Software
Speaker: Paul Navrátil, Texas Advanced Computing Center (TACC)
The design emphasis for supercomputing systems has moved from raw performance to performance-per-watt, and as a result, supercomputing architectures are converging on processors with wide vector units and many processing cores per chip. Such processors are capable of performant image rendering purely in software. This improved capability is fortuitous, since the prevailing homogeneous system designs lack dedicated, hardware-accelerated rendering subsystems for use in data visualization. Reliance on this “software-defined” rendering capability will grow in importance since, due to growing data sizes, visualizations must be performed on the same machine where the data is produced. Further, as data sizes outgrow disk I/O capacity, visualization will be increasingly incorporated into the simulation code itself (in situ visualization).
This talk presents recent work in high-fidelity visualization using the OSPRay ray tracing framework on TACC’s local and remote visualization systems. We present work using OSPRay within ParaView Catalyst in situ framework from Kitware, including capitalizing on opportunities to reduce data costs migrating through VTK filters for visualization. We highlight the performance opportunities and advantages of Intel® Advanced Vector Extensions 512, the memory system improvements possible with Intel® Xeon Phi™ processor multi-channel DRAM (MCDRAM) and the Intel® Omni-Path Architecture interconnect.
Best Practices and Performance Studies for High-Performance Computing ClustersIntel® Software
This session focuses on key system tunables for maximizing application performance of high-performance computing (HPC) workloads, and addresses porting, optimizing, and running applications to maximize performance. We present practical tips and techniques for building and running applications on multicore processors. We analyze sample performance and scaling data from various applications, and identify the best options.
Introduction to Software Defined Visualization (SDVis)Intel® Software
Software defined visualization (SDVis) is an open-source initiative from Intel and industry collaborators. Improve the visual fidelity, performance, and efficiency of prominent visualization solutions, while supporting the rapidly growing big data use on workstations through high-performance computing (HPC) on supercomputing clusters without memory limitations and cost of GPU-based solutions.
Industrial Automation Technical Support including: Tasks estimation, research and technical documentation writing, manual preparation; Real-time operation systems; Porting of existing Software to new target Hardware; Software and Hardware optimization; Hardware bring-up; Drivers development, redesign, upgrades; Design and implementation of embedded Software; Testing software development and verification.
For the full video of this presentation, please visit: https://www.edge-ai-vision.com/2022/06/seamless-deployment-of-multimedia-and-machine-learning-applications-at-the-edge-a-presentation-from-qualcomm/
Megha Daga, Senior Director of Product Management for AIoT at Qualcomm, presents the “Seamless Deployment of Multimedia and Machine Learning Applications at the Edge” tutorial at the May 2022 Embedded Vision Summit.
There has been an explosion of opportunities for edge compute solutions across the internet of things. This growth in opportunities and the diversity of applications is leading to fragmentation in the IoT space both in hardware and software, which creates challenges for developers. In addition, customers and developers are facing challenges in efficient data management and optimized application deployment on embedded edge platforms.
In this session, Daga introduces the Qualcomm Intelligent Multimedia SDK, which empowers developers to tackle these challenges and deploy edge compute applications in a scalable, flexible and optimized way. The Qualcomm Intelligent Multimedia SDK easily decodes and organizes sensor data and executes applications efficiently on edge platforms.
Plan with confidence: Route to a successful Do178c multicore certificationMassimo Talia
The modern approach Multi-Processor in the civil and military Embedded equipments certification. The Processor assessment is conduct by Rockwell Collins Inc., the operating system selection is conducted by Windriver Inc.
For the full video of this presentation, please visit:
https://www.edge-ai-vision.com/2020/12/making-edge-ai-inference-programming-easier-and-flexible-a-presentation-from-texas-instruments/
For more information about edge AI and computer vision, please visit:
https://www.edge-ai-vision.com
Manisha Agrawal, Product Marketing Engineer at Texas Instruments, presents the “Making Edge AI Inference Programming Easier and Flexible” tutorial at the September 2020 Embedded Vision Summit.
Deploying an AI model at the edge doesn’t have to be challenging—but it often is. Embedded processing vendors have unique sets of software tools for deploying models. It takes time and investment to learn to use proprietary tools and to optimize the edge implementation to achieve your desired performance. While embedded vendors are providing proprietary tools for model deployment, the open source community is also advancing to standardize the model deployment process and make it hardware agnostic.
Texas Instruments has adopted open source software frameworks to make model deployment easier and more flexible. In this talk, you will learn about the struggles developers face when deploying models for inference on embedded processors and how TI addresses these critical software development challenges. You will also discover how TI enables faster time-to-market using a flexible open source development approach without the need to compromise performance, accuracy or power requirements.
The number of internet-connected devices is growing exponentially, enabling an increasing number of edge applications in environments such as smart cities, retail, and industry 4.0. These intelligent solutions often require processing large amounts of data, running models to enable image recognition, predictive analytics, autonomous systems, and more. Increasing system workloads and data processing capacity at the edge is essential to minimize latency, improve responsiveness, and reduce network traffic back to data centers. Purpose-built systems such as Supermicro’s short-depth, multi-node SuperEdge, powered by 3rd Gen Intel® Xeon® Scalable processors, increase compute and I/O density at the edge and enable businesses to further accelerate innovation.
Join this webinar to discover new insights in edge-to-cloud infrastructures and learn how Supermicro SuperEdge multi-node solutions leverage data center scale, performance, and efficiency for 5G, IoT, and Edge applications.
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IMAGE CAPTURE, PROCESSING AND TRANSFER VIA ETHERNET UNDER CONTROL OF MATLAB GUI, USING TI TMS320C6713 DSP & ITS DSK_EYE DAUTERCARD
1. IMAGE CAPTURE, PROCESSING AND TRANSFER VIA
ETHERNET UNDER CONTROL OF MATLAB GUI, USING
TI TMS320C6713 DSP & ITS DSK_EYE DAUTERCARD
Christopher Diamantopoulos
Spiros Oikonomou
University of Patras, June 2015 || rev 1.2
2. > TI TMS320C6713 DSP_
The TMS320C6713 device belongs to the floating-point DSP
generation in the TMS320C6000™ DSP platform. The C6713
device is based on the high-performance, advanced very-
long-instruction-word (VLIW) architecture developed by
Texas Instruments (TI)
HARDWARE
SOFTWARE
GUI
TESTING
2
3. The TMS320C6713 device belongs to the floating-point DSP
generation in the TMS320C6000™ DSP platform. The C6713
device is based on the high-performance, advanced very-
long-instruction-word (VLIW) architecture developed by
Texas Instruments (TI)
Feature highlights
Eight 32-Bit Instructions/Cycle
32/64-Bit Data Word
225-, 200-MHz (GDP), and 200-, 167-MHz (PYP) Clock
Rates
4.4-, 5-, 6-Instruction Cycle Times
1800/1350, 1600/1200, and 1336/1000 MIPS /MFLOPS
Highly Optimized C/C++ Compiler
Two ALUs (Fixed-Point)
Four ALUs (Floating- and Fixed-Point)
Two Multipliers (Floating- and Fixed-Point)
Load-Store Architecture With 32 32-Bit General-Purpose
Registers
32-Bit External Memory Interface (EMIF)
• Glueless Interface to SRAM, EPROM, Flash, SBSRAM,
and SDRAM
• 512M-Byte Total Addressable External Memory Space
Two Inter-Integrated Circuit Bus (I2C Bus™) Multi-Master
and Slave Interfaces
Two Multichannel Buffered Serial Ports
• Serial-Peripheral-Interface (SPI)
> TI TMS320C6713 DSP_
HARDWARE
SOFTWARE
GUI
TESTING
3
4. > bitec dsk eye gigabit daughtercard_
The DSKeye gigabit from Bitec is a TI DSK daughterboard
gathering the latest FPGA technology, a 5.2 mega pixel
camera and user configurable interface options to deliver
a Smart Camera system for development and research at a
fraction of the cost normally associated with such
technology.
HARDWARE
SOFTWARE
GUI
TESTING
4
5. The DSKeye gigabit from Bitec is a TI DSK daughterboard
gathering the latest FPGA technology, a 5.2 mega pixel
camera and user configurable interface options to deliver
a Smart Camera system for development and research at a
fraction of the cost normally associated with such
technology.
Feature highlights
ASIXTM AX88180 + Marvell 88E1111
Compatible with IEEE802.3, IEEE802.3u and 802.3ab
standards
Support 10/100/1000Mbps data rate
Support full duplex operation with 1000Mbps
Support full and half duplex operations with 10/100
Mbps
Support Wake-on-LAN function
Cyclone II EP2C8
8256 logic elements
165888 RAM bits
Large capacity for user defined signal processing logic
> bitec dsk eye gigabit daughtercard_
HARDWARE
SOFTWARE
GUI
TESTING
5
6. The DSKeye gigabit from Bitec is a TI DSK daughterboard
gathering the latest FPGA technology, a 5.2 mega pixel
camera and user configurable interface options to deliver
a Smart Camera system for development and research at a
fraction of the cost normally associated with such
technology.
LWIP TCP/IP stack
• A port of the lwIP stack is included with the DSK-EYE
gigabit. This port allows users to write TCP compatible
applications using a set of APIs. At the highest level,
the user can choose to access the TCP stack using the
standard Berkley sockets interface.
• TCP/IP parameters such as the MAC and IP address etc.
can be modified in lwip_NetStart.c file. Default IP and
MAC parameters are the following:
IP4_ADDR(&gw, 192,168,11,1);
IP4_ADDR(&ipaddr, 192,168,11,33);
IP4_ADDR(&netmask, 255,255,255,0);
> bitec dsk eye gigabit daughtercard_
HARDWARE
SOFTWARE
GUI
TESTING
6
7. > Omnivision ov5610 cmos sensor_
The OV5610 (color) CAMERACHIPTM is a high performance 5.17
mega-pixel sensor for digital still image and video
camera products
HARDWARE
SOFTWARE
GUI
TESTING
7
8. The OV5610 (color) CAMERACHIPTM is a high performance 5.17
mega-pixel sensor for digital still image and video
camera products
Feature highlights
Array size:
• QSXGA (2592x1944)
• SXGA (1280x960)
• VGA (640x480)
• HF (320x200)
Optical black level calibration
Video or snapshot operations
Programmable/Auto Exposure and Gain Control
Programmable/Auto White Balance Control
Horizontal and vertical sub-sampling (4:2 and 4:2)
High frame rate output mode
Programmable image windowing/zooming/panning
Variable frame rate control
On-chip R/G/B Channel and Luminance Average Counter
Internal/External frame synchronization
Serial bus interface
Power-on reset and power-down modes
> Omnivision ov5610 cmos sensor_
HARDWARE
SOFTWARE
GUI
TESTING
8
9. The OV5610 (color) CAMERACHIPTM is a high performance 5.17
mega-pixel sensor for digital still image and video
camera products
Image encoding
The camera image is encoded in a Bayer pattern.
OV5610 API
A limited API exists for the OV5610 camera chip. This API
is used by the DSK-EYE API but is also accessible for
user applications. A series of MACROS are available which
allow easy access to the internal registers of the
camera.
> Omnivision ov5610 cmos sensor_
HARDWARE
SOFTWARE
GUI
TESTING
9
10. I²C (Inter-Integrated Circuit), is a multi-master, multi-
slave, single-ended, serial computer bus invented by
Philips Semiconductor (now NXP Semiconductors). It is
typically used for attaching lower-speed peripheral ICs
to processors and microcontrollers.
"I2C" by en:user:Cburnett - Own work made with. Inkscape Licensed under CC BY-SA
3.0 via Wikimedia Commons
Main advantages
uses only two bidirectional open-drain lines, Serial
Data Line (SDA) and Serial Clock Line (SCL)
ACK (acknowledged) bit for an address, ensures that
data are sent
Main disdvantages
maximum number of nodes is limited by the address space
and by the total bus capacitance
shared bus hanging for malfunctioning devices
> i2c protocol_
HARDWARE
SOFTWARE
GUI
TESTING
10
11. Code Composer Studio is an integrated development
environment (IDE) that supports TI's Processors. It
comprises a suite of tools used to develop and debug
embedded applications. It includes an optimizing C/C++
compiler, source code editor, project build environment,
debugger, profiler, and many other features.
HARDWARE
SOFTWARE
GUI
TESTING
> Code comporer studio_
11
12. Code Composer Studio is an integrated development
environment (IDE) that supports TI's Processors. It
comprises a suite of tools used to develop and debug
embedded applications. It includes an optimizing C/C++
compiler, source code editor, project build environment,
debugger, profiler, and many other features.
Project migration & building process
dsk6713_webview.pjt web server example project was used
as base. It is built for CCS 3.1 and it utilizes two
dependent projects:
• DSK6713_camera.pjt: generates the camera library file
DSK6713_camera.lib compiling three c programs (i2c.c,
ov5610.c & dskeye.c)
• DSK6713_LWIP.pjt: generates the communication library
file DSK6713_lwip.lib compiling a bunch of c programs
DSP/BIOS configuration file was converted from .cdb
format to .tcf, using the provided tool
cdb2tcf.exe (the generated file replaced the old one
under DSP/BIOS Config project branch)
HARDWARE
SOFTWARE
GUI
TESTING
> Code comporer studio_
12
13. Code Composer Studio is an integrated development
environment (IDE) that supports TI's Processors. It
comprises a suite of tools used to develop and debug
embedded applications. It includes an optimizing C/C++
compiler, source code editor, project build environment,
debugger, profiler, and many other features.
Project migration & building process
C programming
> Code comporer studio_
HARDWARE
SOFTWARE
GUI
TESTING
DIPeth.c
This is the main program. It opens TCP connection & listens to
port 80 for incoming characters. An extensive case statement
triggers all the appropriate processes.
Image_Processing_API.c
Handles all Image Processing
functions, such as space
conversions, histogram
manipulation or image
filtering
System_Design_API.c
Handles OV5610 register R/W
functions & image transfers
13
14. Code Composer Studio is an integrated development
environment (IDE) that supports TI's Processors. It
comprises a suite of tools used to develop and debug
embedded applications. It includes an optimizing C/C++
compiler, source code editor, project build environment,
debugger, profiler, and many other features.
Project migration & building process
Build options of the main project were modified and
.out file was generated after project build process:
• compiler settings
• linker settings
• main program (DIPeth.c) optimization of execution
> Code comporer studio_
-o1 -
fr"C:CCStudio_v3.3MyProjectsDSK_EYEexampleswebviewDSK6713Deb
ug" -i"$(Proj_dir)......srclwipcommonarchC6xinclude" -
i"$(Proj_dir)......srclwipcommonlwipsrcincludeipv4" -
i"$(Proj_dir)......srclwipcommonlwipsrcinclude" -d"_DEBUG"
-d"CHIP_6713" -ml3 -mv6700
-c -m".Debugdsk6713_webview.map" -o".Debugdsk6713_webview.out" -
w -x
HARDWARE
SOFTWARE
GUI
TESTING
Project level options
And -o3
And Not -o1
14
15. Bayer colour filter array is a popular format for digital
acquisition of colour images. Half of the total number of
pixels are green (G), while a quarter of the total number
is assigned to both red (R) and blue (B).
Four possible interpolating cases
the value for the blue component on a shaded G pixel
will be the average of the blue pixels, while the value
for the red component will be the average of the two
red pixels
For the value of the blue component to be interpolated
for a R pixel. we take the average of the four nearest
blue pixels cornering the R pixel
Similarly, to determine the value of the red component
on a B pixel we take the average of the four nearest
red pixels cornering the B pixel
> Bayer to rgb conversion_
HARDWARE
SOFTWARE
GUI
TESTING
15
16. Bayer colour filter array is a popular format for digital
acquisition of colour images. Half of the total number of
pixels are green (G), while a quarter of the total number
is assigned to both red (R) and blue (B).
Two possible G component interpolating cases
* For faster execution, the third calculation could be used for
both cases
> Bayer to rgb conversion_
HARDWARE
SOFTWARE
GUI
TESTING
16
17. The Transmission Control Protocol provides a
communication service at an intermediate level between an
application program and the Internet Protocol. It
provides host-to-host connectivity at the Transport Layer
of the Internet model. At the transport layer, the
protocol handles all handshaking and transmission details
and presents an abstraction of the network connection to
the application.
"Tcp state diagram fixed new" by Scil100. Licensed under CC BY-SA 3.0 via Wikimedia Commons
> Tcp socket connection_
HARDWARE
SOFTWARE
GUI
TESTING
17
18. The Transmission Control Protocol provides a
communication service at an intermediate level between an
application program and the Internet Protocol. It
provides host-to-host connectivity at the Transport Layer
of the Internet model. At the transport layer, the
protocol handles all handshaking and transmission details
and presents an abstraction of the network connection to
the application.
Sent bytestream
image from http://www.slideshare.net/aswinkartick/mk-ppt-chapter-5
302700 x 3 bytes
> Tcp socket connection_
HARDWARE
SOFTWARE
GUI
TESTING
18
19. Y′CbCr, is a family of color spaces used as a part of the
color image pipeline in video and digital photography
systems. Y′ is the luma component and Cb and Cr are the
blue-difference and red-difference chroma components.
Y′CbCr is not an absolute color space. Rather, it is a
way of encoding RGB information.
Colour space for processing
"CCD" by LionDoc - Own work. Licensed under Public Domain via Wikimedia Commons
> Image processing_
HARDWARE
SOFTWARE
GUI
TESTING
19
20. GUIs provide point-and-click control of software
applications, eliminating the need to type commands in
order to run the application.
> Graphical user interface_
HARDWARE
SOFTWARE
GUI
TESTING
20
21. GUIs provide point-and-click control of software
applications, eliminating the need to type commands in
order to run the application.
Feature highlights
User-friendly interface
Explanatory tooltips & dialogs
Communication error handling ability
Standalone executable application (no need for running
MATLAB instance)
> Graphical user interface_
HARDWARE
SOFTWARE
GUI
TESTING
21
1 2
5
8
6 7
3
4
22. GUIs provide point-and-click control of software
applications, eliminating the need to type commands in
order to run the application.
GUI v.0.2.0 sections
CAPTURED IMAGE PROCESSED IMAGE
INFORMATIVE CONSOLE DSK CONTROL (CCS LINK)
CAPTURE BUTTON SENSOR ADJUSTMENTS
IMAGE PROCESSING BUTTONS SENSOR RESET
> Graphical user interface_
HARDWARE
SOFTWARE
GUI
TESTING
22
23. Regarding the captured image bytestream, the GUI handles
the image by splitting the colour components accordingly
in three 640x480 matrices. In case of a grayscale image,
the procedure simplified in a 640x480 matrix fill.
Colour image construction
> Image composition_
HARDWARE
SOFTWARE
GUI
TESTING
23
480 px
640 px
480 px
640 px
24. System was tested in laboratory under various lighting
conditions. Captured frames satisfied several concepts
(places, low-light room, bright displays etc).
System setup
PC network adapter was set appropriately
DSP board was connected to PC via CAT 5 Ethernet cable
> System testing_
HARDWARE
SOFTWARE
GUI
TESTING
24
25. System was tested in laboratory under various lighting
conditions. Captured frames satisfied several concepts
(places, low-light room, bright displays etc).
Image processing samples
• RGB2Grayscale
• Edge detection
> System testing_
HARDWARE
SOFTWARE
GUI
TESTING
25
26. System was tested in laboratory under various lighting
conditions. Captured frames satisfied several concepts
(places, low-light room, bright displays etc).
Image processing samples
• White balance
• Histogram inversion
> System testing_
HARDWARE
SOFTWARE
GUI
TESTING
26
27. System was tested in laboratory under various lighting
conditions. Captured frames satisfied several concepts
(places, low-light room, bright displays etc).
Image processing samples
• Sharp image
• Blue channel adjustment
> System testing_
HARDWARE
SOFTWARE
GUI
TESTING
27