This paper introduces efficient test logic partitioning to not only optimize and reduce the overall test power during silicon validation but also reduce power in functional mode by shutting off test logic. Approach used in optimizing test power has been successful in reducing overall functional mode leakage power by 50% without any additional area overhead or test time increase. Results shared are based on WIMAX full chip SoC design.

1. Power Optimization with Efficient Test
Logic Partitioning for Full Chip Design
Vyagrhee Nainala
Pankaj Singh
Jayateertha Karekar
Vibhor Mishra
Texas Instruments India (P) Ltd

2. Content
Glossary
Objective
Outline
Introduction
Solution Offered for Test Power Reduction
—SoC Test Architecture
—Power Savings Scenarios
—Separating Scan Mode
—Final results
—DFT Flow
Key Care About for Power Optimization
Conclusion and Summary
Acknowledgement
References

3. Power Optimization with Efficient Test Logic Partitioning for Full Chip Design
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Glossary
 DFT : Design for Test
 EDT : Embedded Deterministic Test
 MDP : Memory Data Path
 JTAG : Joint Test Action Group
 EFUSE : Electronic Fuse
 PBIST : Programmable BIST
 ALW : Always On
 PD : Power Domain
 PSCON : Power State Controller

4. Power Optimization with Efficient Test Logic Partitioning for Full Chip Design
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Objective
 This paper introduces efficient test logic partitioning to
not only optimize and reduce the overall test power
during silicon validation but also reduce power in
functional mode by shutting off test logic. Approach used
in optimizing test power has been successful in reducing
overall functional mode leakage power by 50% without
any additional area overhead or test time increase.
Results shared are based on WIMAX full chip SoC design.

5. Power Optimization with Efficient Test Logic Partitioning for Full Chip Design
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Outline
 This paper start with introduction section which
describes critical reliability issues with higher power
consumption in test mode and highlights the need for
test power reduction.
 The next section describes the test architecture
implementation for DFT (Design For Test) modes and
presents alternate test architecture scenarios for power
savings in functional mode. The alternate test
architecture implementation is based on tradeoff between
physical design implementation challenges and overall
test power reduction. This section also describes
selective enable of power domain/subchip to reduce
power consumption during silicon validation.
 The last section describes Key Care about for test power
optimization using this approach and concludes this
paper with overall benefits of the proposed methodology.

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Introduction
 Power dissipation in test mode is becoming an important
concern as design size increases. Switching activity in test
mode can be 3x to 5x more than power in functional mode.
— This can cause reliability issues due to EM or noise-induced
test failures due to IR drop issues.
— Excessive peak power in test mode over multiple cycles can
also elevate the temperature of the chip, causing instant
damage.
 Test logic overhead can be as large as 500K to 600K at
SOC level. Typically designer effort is spent in reducing
power in Always-On logic. However most of the times the
test logic is higher than Always-On functional logic and
consumes most of the device power.
— Leakage power due to test logic can be as large as ~70% if
proper power management techniques are not deployed
 BIST logic & MDP (Memory Data Path) are main contributor to the
test logic area and power consumption.
 EDT (Embedded Deterministic Test ) and Efuse (Electronic Fuse)
controller are next contributor to overall area and power
increase.

7. Power Optimization with Efficient Test Logic Partitioning for Full Chip Design
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Introduction
 While several algorithm has been proposed for reducing
power dissipation in test mode, very little effort is spent
in optimizing test architecture partitioning in SoC design
to reduce overall power. This was the main motivation to
start this work; this paper presents architecture level
optimization to reduce power in functional mode by
switching off/disabling the test logic.
 The test logic implementation is done at netlist level
without any schedule impact or additional increase in
gate count, test time. Equivalence check ensures
functionality is maintained after test logic insertion.

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SoC Architecture without Test Logic
PD2 (Digital
Subchip)
PD1 (Digital
Subchip)
PD3 (IP)
SOC
Analog IP
Memory
PD: Power domain

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SoC Architecture with Test Logic
MODULE1MODULE2
MODULE3(IP)
SOC
Analog IP
Test pin muxing
JTAG
TEST WRAPPER
EDT
EDT
EDT
PBIST &MDP
EFUSE
MISC

10. Power Optimization with Efficient Test Logic Partitioning for Full Chip Design
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Power saving Scenario#1
PSCON
sequencer
Test
control
Test control
from JTAG
PSCON
sequencer
Test
control
Test control
from JTAG
EFUSE .
Fuse chain
PD1
PDn
PBIST
MDP
MDP
EDT
EDT
JTAG & MUX Pros: Less physical design issues such as
congestion , timing closure.
Cons: More power consumption in
functional mode
Sleep signal
Sleep signal

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Power saving Scenario #2
PD1
PDn
PSCON
sequencer
Test
control
Test control
from JTAG
Test controller .
PSCON
sequencer
Test
control
Test control
from JTAG
EFUSE .
Fuse chain
JTAG & MUX
MDP
EDT
Pros: Lower leakage power. Disable test
controller in functional mode.
Cons: Signal routing issues (Congestion, timing
closure) due to thousands of additional signal
from test controller-PD
Sleep signal
Sleep signal

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Separating Scan mode to Reduce Test Power during Validation
Wrapper to test the
boundary
SO2
• Dynamic power can be reduced during Stuck-At and TFT by separating the test modes to different scan modes
• The test time impact due to increase in scan modes is minimal(<1%) as compared to overall test time.
• Testing of interface between power domains is done with wrapper cells.
Note:
SI1 : Scan Input 1. SO1: Scan output1
SI2: Scan Input2. SO2: Scan Output2
Power is reduced during
silicon validation since scan
flops of individual power
domain do not toggle at the
same time.
PD1
(SCANMODE1)
PSCON
SCAN
combiner
8
8
8
8
SO1
SI2SI1
SI
SO
JTAG
To/From
PADS
PD1
(SCANMODE2)

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Results: SoC Leakage Power Savings
 As depicted in above table ~220uA leakage power was saved.
This is more than 50% of Always-on functional power (390uA).
 The overall power can be further saved as high as 70% of total
leakage power by moving the MDP Bist and EDT scan logic to
the test controller module.
 Except JTAG (Joint Test Action Group) and Always-ON logic
complete test logic can be shutdown
Module Leakage(uA) Area Comment
PBIST 180 285K Option to Power down by PSCON
MDP 40 73K
This can be power down by making it part of test controller; leakage power depends
on size of the design and number of memories
EDT 20 42K
This can be power down by making it part of test controller; leakage power depends
on size of the design and number of FFs
EFUSE 60 94K Option to shut down after autoload sequence using PSCON
JTAG & pin
mux 40 51K This can not be power down. And Should always be ON
ALW(logic) 350 138K This can not be power down. And Should always be ON
Other Test 1) Wrapextest and scan test are muxed and not enabled at the same time
2) Test Mode to select individual power domain in scan mode
Note*: These numbers are based on WIMAX design. Actual numbers can vary based on the design size
Complete shutdown.
Option to shutdown

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DFT Flow: Automated Test logic Insertion
MDP, Efuse hookup &
power signals hookup
Input Netlist
Clk leaker integration
&
CLK & Reset MUX
Scan insertion &
wrapper insertion
EDT generation
& Integration
Equivalence
Check
DFT Verification
and Physical Design
Flow
Scan
Check
• TheTest logic insertion flow is fully automated .
• Equivalence check at each stage ensures functionality of the
design after DFT implementation

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Key Care about: Power Optimization
 Test logic should be cleverly partitioned to get the
maximum power savings
— Place the EDT for scan and MDP for BIST (~50 or more
memories) inside individual power domains for large design
which is channel dominated at top level. This approach will
minimize congestion issues due to multiple long net routing
from test controller to power domains at the top level.
 Clock tree for the memories should be planned in
advance with external PBist (Programmable BIST )
controller to minimize timing closure issues
— Use functional clock tree for memories to avoid use of
unnecessary multiplexers thereby reducing insertion delay

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 Test Power up sequence should be planned before
finalizing the Test controller power domain. Care should
be taken to ensure proper power up sequence for test
controller logic :
— Test controller should be powered up for scan test, memory
test
— Efuse controller should be powered up for auto load to
complete during memory Final test.
Key Care about: Power Optimization

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Conclusion
 The test logic partitioning presented in this paper has
been successful in reducing the overall leakage power
and providing the following benefits:
— Reduces the test power overhead in functional mode
— Enables multi-site testing of SoC’s by utilizing low cost
tester with less power testing capability
— Enables accurate IDDQ testing by providing option to put
device in complete power shutdown mode.
 The DFT methodology presented in this paper is
completely automated. Test logic can be
inserted/integrated in netlist with minimal effort.
Equivalence check ensures design validity after test logic
insertion.

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References
 Tackling test challenges for low-power design; Chris
Hawkins, Jason Doege and George Kuo. EE Times
ID=173403100
 Low-power IC test can be trying; Chris Hawkins,
Jason Doege and George Kuo. EE Times
ID=174900268
 Industrial Experience with Adoption of EDT for Low-
Cost Test without Concessions; Frank Poehl, Matthias
Beck, Ralf Arnold, Peter Muhmenthaler, Nagesh
Tamarapalli, Mark Kassab, Nilanjan Mukherjee,
Janusz Rajski. ITC International Test Conference

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