In the featuring VLSI era, compact electronic devices are popular. The reliability and durability of such compact devices relies on low power utilization. The purpose of this project was to implement a low power adiabatic Static Random Access Memory (SRAM), with the following objectives - To reduce the power waste by means of stepwise charging using tank capacitors which is an adiabatic way of generating power
clock. This method is capable of recuperating the electrical energy back to the source. Further to examine the Static Noise Margin (SNM) – a parameter which gives detailed information about the cell stability – in
contrast with conventional 6T, 7T and 8T topologies of SRAM under 180 nm technology. Finally, SNM variations with respect to process parameters are also discussed. All the implementations and analysis were made using CADENCE tool and MATLAB tool.
IMPLEMENTATION OF LOW POWER ADIABATIC SRAMVLSICS Design
In the featuring VLSI era, compact electronic devices are popular. The reliability and durability of such compact devices relies on low power utilization. The purpose of this project was to implement a low power adiabatic Static Random Access Memory (SRAM), with the following objectives - To reduce the power waste by means of stepwise charging using tank capacitors which is an adiabatic way of generating power clock. This method is capable of recuperating the electrical energy back to the source. Further to examine the Static Noise Margin (SNM) – a parameter which gives detailed information about the cell stability – in contrast with conventional 6T, 7T and 8T topologies of SRAM under 180 nm technology. Finally, SNM variations with respect to process parameters are also discussed. All the implementations and analysis were made using CADENCE tool and MATLAB tool.
A Novel Low Power Energy Efficient SRAM Cell With Reduced Power Consumption u...iosrjce
In modern high performance integrated circuits, maximum of the total active mode energy is
consumed due to leakage current. SRAM cell array is main source of leakage current since majority of
transistor are utilized for on-chip memory in today high performance microprocessor and system on chip
designs. Therefore the design of low leakage SRAM is required. Reducing power dissipation, supply voltage,
leakage currents, area of chip are the most important parameters in today`s VLSI designs. But scaling of these
parameters will lead to drastic increase in sub threshold leakage currents and power dissipation because of that
performance of the design is degraded. So to overcome these issues it is better to concentrate on reduction of
active leakage currents and dynamic power dissipation by using power reduction techniques. In this paper 9T
SRAM (data retention p-gated) cell for low voltage and energy constrain application is analyzed with respect to
power dissipation, area and delay. The analyzed design of 9T SRAM cell with MTCMOS technique has been
proposed. Designed circuits are simulated in Microwind 3.1 VLSI CAD Tool in 90 and 65nm CMOS technology.
DESIGN OF LOW WRITE-POWER CONSUMPTION SRAM CELL BASED ON CNTFET AT 32nm TECHN...VLSICS Design
The SRAM which functions as the cache for system-on-chip is vital in the electronic industry. Carbon Nanotube Field Effect Transistor (CNFET) is used for high performance, high stability and low-power circuit designs as an alternative material to silicon in recent years. Therefore Design of SRAM Cell based on CNTFET is important for Low-power cache memory. In cells, the bit-lines are the most power consuming components because of larger power dissipation in driving long bit-line with large capacitance. The cache write consumes considerable large power due to full voltage swing on the bit-line. This Paper proposes a novel 7T SRAM cell based on CNTFET that only depends on one of bit lines for Write operation and reduce the write-power consumption. The read cycle also improved because of careful transistor
sizing. HSPICE simulations of this circuit using Stanford CNFET model shows that 37.2% write power saving, read cycle improvement of 38.6%.
SIMULTANEOUS OPTIMIZATION OF STANDBY AND ACTIVE ENERGY FOR SUB-THRESHOLD CIRC...VLSICS Design
Increased downscaling of CMOS circuits with respect to feature size and threshold voltage has a result of dramatically increasing in leakage current. So, leakage power reduction is an important design issue for active and standby modes as long as the technology scaling increased. In this paper, a simultaneous active and standby energy optimization methodology is proposed for 22 nm sub-threshold CMOS circuits. In the first phase, we investigate the dual threshold voltage design for active energy per cycle minimization. A
slack based genetic algorithm is proposed to find the optimal reverse body bias assignment to set of noncritical
paths gates to ensure low active energy per cycle with the maximum allowable frequency at the optimal supply voltage. The second phase, determine the optimal reverse body bias that can be applied to all gates for standby power optimization at the optimal supply voltage determined from the first phase.
Therefore, there exist two sets of gates and two reverse body bias values for each set. The reverse body bias is switched between these two values in response to the mode of operation. Experimental results are obtained for some ISCAS-85 benchmark circuits such as 74L85, 74283, ALU74181, and 16 bit RCA. The optimized circuits show significant energy saving ranged (from 14.5% to 42.28%) and standby power
saving ranged (from 62.8% to 67%)
“Power and Temperature Analysis of 12T CMOS SRAM Designed With Short Channel ...iosrjce
This paper focuses mainly on dynamic power dissipations at different temperature for both read and
write operations of 12T SRAM. In the proposed 12T structure virtual vdd concept is employed because of this
leakage current will reduce. Hence reduction in leakage current causes reduction in dynamic power. Power
dissipation of the proposed SRAM cell have been determined and compared to those of some other existing
memory cells. Proposed cell is a short channel BSIM4 model. It is observed that power dissipation of 12T
SRAM for read operation at 40̊
̊
is 44.7nw and for write operation it is 38.79nw. The proposed SRAM cell
dissipates less power. Simulation has been done in Tanner-13 EDA tool for 50nm.
IOSR Journal of Electronics and Communication Engineering(IOSR-JECE) is an open access international journal that provides rapid publication (within a month) of articles in all areas of electronics and communication engineering and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications in electronics and communication engineering. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
VOLTAGE STACKING FOR SIMPLIFYING POWER MANAGEMENT IN ASYNCHRONOUS CIRCUITSVLSICS Design
Multiple power domains on a single integrated circuit (IC) are becoming more common due to the increasing complexity of systems on chips (SoCs) as process nodes continue to get smaller. Supplying the correct voltage to each domain requires the use of multiple voltage converters that occupy substantial space either on-chip or off-chip and introduce additional power loss in the conversions. In this paper, an asynchronous paradigm called Multi-Threshold NULL Convention Logic (MTNCL) is used to create a “stacked” architecture that reduces the number of converters needed and thereby mitigating the aforementioned problems. In this architecture, the MTNCL circuits are stacked between a multiple of VDD and GND, where simple control mechanisms alleviate the induced dynamic range fluctuation problem. The GLOBALFOUNDRIES 32nm Silicon-on-Insulator (SOI) CMOS process is used to evaluate and analyze the theoretical effects of parasitic extracted physical implementations in stacking different circuits running different workloads. These results show that the “stacked” architecture introduce negligible overhead compared to the operation of the individual circuits while substantially alleviating the need for voltage converters, which in turn reduces the overall power consumption of the system.
IMPLEMENTATION OF LOW POWER ADIABATIC SRAMVLSICS Design
In the featuring VLSI era, compact electronic devices are popular. The reliability and durability of such compact devices relies on low power utilization. The purpose of this project was to implement a low power adiabatic Static Random Access Memory (SRAM), with the following objectives - To reduce the power waste by means of stepwise charging using tank capacitors which is an adiabatic way of generating power clock. This method is capable of recuperating the electrical energy back to the source. Further to examine the Static Noise Margin (SNM) – a parameter which gives detailed information about the cell stability – in contrast with conventional 6T, 7T and 8T topologies of SRAM under 180 nm technology. Finally, SNM variations with respect to process parameters are also discussed. All the implementations and analysis were made using CADENCE tool and MATLAB tool.
A Novel Low Power Energy Efficient SRAM Cell With Reduced Power Consumption u...iosrjce
In modern high performance integrated circuits, maximum of the total active mode energy is
consumed due to leakage current. SRAM cell array is main source of leakage current since majority of
transistor are utilized for on-chip memory in today high performance microprocessor and system on chip
designs. Therefore the design of low leakage SRAM is required. Reducing power dissipation, supply voltage,
leakage currents, area of chip are the most important parameters in today`s VLSI designs. But scaling of these
parameters will lead to drastic increase in sub threshold leakage currents and power dissipation because of that
performance of the design is degraded. So to overcome these issues it is better to concentrate on reduction of
active leakage currents and dynamic power dissipation by using power reduction techniques. In this paper 9T
SRAM (data retention p-gated) cell for low voltage and energy constrain application is analyzed with respect to
power dissipation, area and delay. The analyzed design of 9T SRAM cell with MTCMOS technique has been
proposed. Designed circuits are simulated in Microwind 3.1 VLSI CAD Tool in 90 and 65nm CMOS technology.
DESIGN OF LOW WRITE-POWER CONSUMPTION SRAM CELL BASED ON CNTFET AT 32nm TECHN...VLSICS Design
The SRAM which functions as the cache for system-on-chip is vital in the electronic industry. Carbon Nanotube Field Effect Transistor (CNFET) is used for high performance, high stability and low-power circuit designs as an alternative material to silicon in recent years. Therefore Design of SRAM Cell based on CNTFET is important for Low-power cache memory. In cells, the bit-lines are the most power consuming components because of larger power dissipation in driving long bit-line with large capacitance. The cache write consumes considerable large power due to full voltage swing on the bit-line. This Paper proposes a novel 7T SRAM cell based on CNTFET that only depends on one of bit lines for Write operation and reduce the write-power consumption. The read cycle also improved because of careful transistor
sizing. HSPICE simulations of this circuit using Stanford CNFET model shows that 37.2% write power saving, read cycle improvement of 38.6%.
SIMULTANEOUS OPTIMIZATION OF STANDBY AND ACTIVE ENERGY FOR SUB-THRESHOLD CIRC...VLSICS Design
Increased downscaling of CMOS circuits with respect to feature size and threshold voltage has a result of dramatically increasing in leakage current. So, leakage power reduction is an important design issue for active and standby modes as long as the technology scaling increased. In this paper, a simultaneous active and standby energy optimization methodology is proposed for 22 nm sub-threshold CMOS circuits. In the first phase, we investigate the dual threshold voltage design for active energy per cycle minimization. A
slack based genetic algorithm is proposed to find the optimal reverse body bias assignment to set of noncritical
paths gates to ensure low active energy per cycle with the maximum allowable frequency at the optimal supply voltage. The second phase, determine the optimal reverse body bias that can be applied to all gates for standby power optimization at the optimal supply voltage determined from the first phase.
Therefore, there exist two sets of gates and two reverse body bias values for each set. The reverse body bias is switched between these two values in response to the mode of operation. Experimental results are obtained for some ISCAS-85 benchmark circuits such as 74L85, 74283, ALU74181, and 16 bit RCA. The optimized circuits show significant energy saving ranged (from 14.5% to 42.28%) and standby power
saving ranged (from 62.8% to 67%)
“Power and Temperature Analysis of 12T CMOS SRAM Designed With Short Channel ...iosrjce
This paper focuses mainly on dynamic power dissipations at different temperature for both read and
write operations of 12T SRAM. In the proposed 12T structure virtual vdd concept is employed because of this
leakage current will reduce. Hence reduction in leakage current causes reduction in dynamic power. Power
dissipation of the proposed SRAM cell have been determined and compared to those of some other existing
memory cells. Proposed cell is a short channel BSIM4 model. It is observed that power dissipation of 12T
SRAM for read operation at 40̊
̊
is 44.7nw and for write operation it is 38.79nw. The proposed SRAM cell
dissipates less power. Simulation has been done in Tanner-13 EDA tool for 50nm.
IOSR Journal of Electronics and Communication Engineering(IOSR-JECE) is an open access international journal that provides rapid publication (within a month) of articles in all areas of electronics and communication engineering and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications in electronics and communication engineering. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
VOLTAGE STACKING FOR SIMPLIFYING POWER MANAGEMENT IN ASYNCHRONOUS CIRCUITSVLSICS Design
Multiple power domains on a single integrated circuit (IC) are becoming more common due to the increasing complexity of systems on chips (SoCs) as process nodes continue to get smaller. Supplying the correct voltage to each domain requires the use of multiple voltage converters that occupy substantial space either on-chip or off-chip and introduce additional power loss in the conversions. In this paper, an asynchronous paradigm called Multi-Threshold NULL Convention Logic (MTNCL) is used to create a “stacked” architecture that reduces the number of converters needed and thereby mitigating the aforementioned problems. In this architecture, the MTNCL circuits are stacked between a multiple of VDD and GND, where simple control mechanisms alleviate the induced dynamic range fluctuation problem. The GLOBALFOUNDRIES 32nm Silicon-on-Insulator (SOI) CMOS process is used to evaluate and analyze the theoretical effects of parasitic extracted physical implementations in stacking different circuits running different workloads. These results show that the “stacked” architecture introduce negligible overhead compared to the operation of the individual circuits while substantially alleviating the need for voltage converters, which in turn reduces the overall power consumption of the system.
POWER COMPARISON OF CMOS AND ADIABATIC FULL ADDER CIRCUITSVLSICS Design
Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. Apart from the basic addition adders also used in performing useful operations such as subtraction, multiplication, division, address calculation, etc. In most of these systemsthe adder lies in the critical path that determines the overall performance of the system. In this paper conventional complementary metal oxide emiconductor (CMOS) and adiabatic adder circuits are analyzed in terms of power and transistor count using 0.18UM technology.
DESIGN & ANALYSIS OF A CHARGE RE-CYCLE BASED NOVEL LPHS ADIABATIC LOGIC CIRCU...VLSICS Design
This paper focuses on principles of adiabatic logic, its classification and comparison of various adiabatic logic designs. An attempt has been made in this paper to modify 2PASCL (Two Phase Adiabatic Static CMOS Logic) adiabatic logic circuit to minimize delay of the different 2PASCL circuit designs. This modifications in the circuits leads to improvement of Power Delay Product (PDP) which is one of the figure of merit to optimize the circuit with factors like power dissipation and delay of the circuit. This paper investigates the design approaches of low power adiabatic gates in terms of energy dissipation and uses of Simple PN diode instead of MOS diode which reduces the effect of Capacitances at high transition and power clock frequency. A computer simulation using SPECTRE from Cadence is carried out on different adiabatic circuits, such as Inverter, NAND, NOR, XOR and 2:1 MUX.
DESIGN AND MODELLING OF DIFFERENT SRAM’S BASED ON CNTFET 32NM TECHNOLOGYVLSICS Design
Carbon nanotube field-effect transistor (CNTFET) refers to a field-effect transistor that utilizes a single carbon nanotube or an array of carbon nanotubes as the channel material instead of bulk silicon in the traditional MOSFET structure. Since it was first demonstrated in 1998, there have been tremendous developments in CNTFETs, which promise for an alternative material to replace silicon in future electronics. Carbon nanotubes are promising materials for the nano-scale electron devices such as nanotube FETs for ultra-high density integrated circuits and quantum-effect devices for novel intelligent circuits, which are expected to bring a breakthrough in the present silicon technology. A Static Random Access Memory (SRAM) is designed to plug two needs: i) The SRAM provides as cache memory, communicating between central processing unit and Dynamic Random Access Memory (DRAM). ii) The SRAM technology act as driving force for low power application since SRAM is portable compared to DRAM, and SRAM doesn’t require any refresh current. On the basis of acquired knowledge, we present
different SRAM's designed for the conventional CNTFET. HSPICE simulations of this circuit using Stanford CNTFET model shows a great improvement in power saving.
Design and Analysis of Multi Vt and Variable Vt based Pipelined Adder for Lo...VLSICS Design
Majority of Digital Signal Processing (DSP) applications require arithmetic blocks such as multipliers and adders for hardware realization of complex algorithms. Power consumption of arithmetic blocks need to be minimized by use of low power techniques. In this paper, an experimental setup is developed to identify the sources of power dissipation and remedies that can be adopted to minimize power dissipation in arithmetic blocks. Use of low power techniques such as Multi Vt, variable Vt, pipelining, geometry scaling and use of appropriate load capacitance have been used to reduce power dissipation. A 4-bit pipelined adder is designed and the power dissipation is reduced to 4.17µW from 9.6µW. The designed pipelined adder can be used for DSP applications.
.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
The paper presents a low Power consumption plays a vital role in the present day VLSI technology. Power consumption of an electronic device can be reduced by adopt changed design styles. Multipliers play a most important role in high concert systems. This project focus on a novel energy efficient technique called adiabatic logic which is based on energy renewal principle and power is compared by designing a multiplier. CMOS technology plays a main role in designing low power consuming devices, compared to different logic family CMOS has less power dissipation. Adiabatic logic method is assumed to be an attractive solution for low power electronic applications. By using Adiabatic techniques energy dissipation in PMOS network can be minimized and selection of energy stored at load capacitance can be recycled instead of dissipated as heat. Tanner EDA tools are used for simulation.
Comparative Performance Analysis of XORXNOR Function Based High-Speed CMOS Fu...VLSICS Design
This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A low power and high performance 9T full adder cell using a design style called “XOR (3T)” is discussed. The designed circuit commands a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as it lowers power consumption by using XOR (3T) logic circuits. Gate Diffusion Input (GDI) technique of low-power digital combinatorial circuit design is also described. This technique helps in reducing the power consumption and the area of digital circuits while maintaining low complexity of logic design. This paper analyses, evaluates and compares the performance of various adder circuits. Several simulations conducted using different voltage supplies, load capacitors and temperature variation demonstrate the superiority of the XOR (3T) based full adder designs in term of delay, power and power delay product (PDP) compared to the other full adder circuits. Simulation results illustrate the superiority of the designed adder circuits against the conventional CMOS, TG and Hybrid full adder circuits in terms of power, delay and power delay product (PDP).
Implementation of High Reliable 6T SRAM Cell Designiosrjce
Memory can be formed with the integration of large number of basic storing element called cells.
SRAM cell is one of the basic storing unit of volatile semiconductor memory that stores binary logic '1' or '0' bit.
Modified read and write circuits were proposed in this paper to address incorrect read and write operations in
conventional 6T SRAM cell design available in open literature. Design of a new highly reliable 6T SRAM cell
design is proposed with reliable read, write operations and negative bit line voltage (NBLV). Simulations are
carried out using MENTOR GRAPHICS
250nm Technology Based Low Power SRAM Memoryiosrjce
High integration density, low power and fastperformance are all critical parameters in designing of
memory blocks. Static Random Access Memories (SRAMs)’s focusing on optimizing dynamic power concept of
virtual source transistors is used for removing direct connection between VDD and GND.
Also stacking effect can be reduced by switching off the stacktransistors when the memory is ideal and the
leakage current using SVL techniques This paper discusses the evolution of 9t SRAM circuits in terms of low
power consumption, The whole circuit verification is done on the Tanner tool, Schematic of the
SRAM cell is designed on the S-Edit and net list simulation done by using T-spice and waveforms are analyzed
through the W-edit
Energy optimization of 6T SRAM cell using low-voltage and high-performance in...IJECEIAES
The performance of the cell deteriorates, when static random access memory (SRAM) cell is operated below 1V supply voltage with continuous scale down of the complementary metal oxide semiconductor (CMOS) technology. The conventional 6T, 8T-SRAM cells suffer writeability and read static noise margins (SNM) at low-voltages leads to degradation of cell stability. To improve the cell stability and reduce the dynamic power dissipation at low- voltages of the SRAM cell, we proposed four SRAM cells based on inverter structures with less energy consumption using voltage divider bias current sink/source inverter and NOR/NAND gate using a pseudo-nMOS inverter. The design and implementation of SRAM cell using proposed inverter structures are compared with standard 6T, 8T and ST-11T SRAM cells for different supply voltages at 22-nm CMOS technology exhibit better performance of the cell. The read/write static noise margin of the cell significantly increases due to voltage divider bias network built with larger cell-ratio during read path. The load capacitance of the cell is reduced with minimized switching transitions of the devices during high-to-low and low- to-high of the pull-up and pull-down networks from VDD to ground leads to on an average 54% of dynamic power consumption. When compared with the existing ones, the read/write power of the proposed cells is reduced to 30%. The static power gets reduced by 24% due to stacking of transistors takes place in the proposed SRAM cells as compare to existing ones. The layout of the proposed cells is drawn at a 45-nm technology, and occupies an area of 1.5 times greater and 1.8 times greater as compared with 6T-SRAM cell.
Design of Low Write-Power Consumption SRAM Cell Based on CNTFET at 32nm Techn...VLSICS Design
The SRAM which functions as the cache for system-on-chip is vital in the electronic industry. Carbon Nanotube Field Effect Transistor (CNFET) is used for high performance, high stability and low-power circuit designs as an alternative material to silicon in recent years. Therefore Design of SRAM Cell based on CNTFET is important for Low-power cache memory. In cells, the bit-lines are the most power consuming components because of larger power dissipation in driving long bit-line with large capacitance. The cache write consumes considerable large power due to full voltage swing on the bit-line. This Paper proposes a novel 7T SRAM cell based on CNTFET that only depends on one of bit lines for Write operation and reduce the write-power consumption. The read cycle also improved because of careful transistor sizing. HSPICE simulations of this circuit using Stanford CNFET model shows that 37.2% write power saving, read cycle improvement of 38.6%.
CELL STABILITY ANALYSIS OF CONVENTIONAL 6T DYNAMIC 8T SRAM CELL IN 45NM TECHN...VLSICS Design
A SRAM cell must meet requirements for operation in submicron/nano ranges. The scaling of CMOS technology has significant impact on SRAM cell -- random fluctuation of electrical characteristics and substantial leakage current. In this paper we present dynamic column based power supply 8T SRAM cell and comparing the proposed SRAM cell with respect to conventional SRAM 6T in various aspects. To verify read stability and write ability analysis we use N-curve metric. Simulation results affirmed that proposed 8T SRAM cell achieved improved read stability, read current, and leakage current in 45nm Technology comparing with conventional 6T SRAM using cadence virtuoso tool.
SIMULTANEOUS OPTIMIZATION OF STANDBY AND ACTIVE ENERGY FOR SUB-THRESHOLD CIRC...VLSICS Design
Increased downscaling of CMOS circuits with respect to feature size and threshold voltage has a result of
dramatically increasing in leakage current. So, leakage power reduction is an important design issue for
active and standby modes as long as the technology scaling increased. In this paper, a simultaneous active
and standby energy optimization methodology is proposed for 22 nm sub-threshold CMOS circuits. In the
first phase, we investigate the dual threshold voltage design for active energy per cycle minimization. A
slack based genetic algorithm is proposed to find the optimal reverse body bias assignment to set of noncritical paths gates to ensure low active energy per cycle with the maximum allowable frequency at the
optimal supply voltage. The second phase, determine the optimal reverse body bias that can be applied to
all gates for standby power optimization at the optimal supply voltage determined from the first phase.
Therefore, there exist two sets of gates and two reverse body bias values for each set. The reverse body bias
is switched between these two values in response to the mode of operation. Experimental results are
obtained for some ISCAS-85 benchmark circuits such as 74L85, 74283, ALU74181, and 16 bit RCA. The
optimized circuits show significant energy saving ranged (from 14.5% to 42.28%) and standby power
saving ranged (from 62.8% to 67%).
POWER COMPARISON OF CMOS AND ADIABATIC FULL ADDER CIRCUITSVLSICS Design
Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. Apart from the basic addition adders also used in performing useful operations such as subtraction, multiplication, division, address calculation, etc. In most of these systemsthe adder lies in the critical path that determines the overall performance of the system. In this paper conventional complementary metal oxide emiconductor (CMOS) and adiabatic adder circuits are analyzed in terms of power and transistor count using 0.18UM technology.
DESIGN & ANALYSIS OF A CHARGE RE-CYCLE BASED NOVEL LPHS ADIABATIC LOGIC CIRCU...VLSICS Design
This paper focuses on principles of adiabatic logic, its classification and comparison of various adiabatic logic designs. An attempt has been made in this paper to modify 2PASCL (Two Phase Adiabatic Static CMOS Logic) adiabatic logic circuit to minimize delay of the different 2PASCL circuit designs. This modifications in the circuits leads to improvement of Power Delay Product (PDP) which is one of the figure of merit to optimize the circuit with factors like power dissipation and delay of the circuit. This paper investigates the design approaches of low power adiabatic gates in terms of energy dissipation and uses of Simple PN diode instead of MOS diode which reduces the effect of Capacitances at high transition and power clock frequency. A computer simulation using SPECTRE from Cadence is carried out on different adiabatic circuits, such as Inverter, NAND, NOR, XOR and 2:1 MUX.
DESIGN AND MODELLING OF DIFFERENT SRAM’S BASED ON CNTFET 32NM TECHNOLOGYVLSICS Design
Carbon nanotube field-effect transistor (CNTFET) refers to a field-effect transistor that utilizes a single carbon nanotube or an array of carbon nanotubes as the channel material instead of bulk silicon in the traditional MOSFET structure. Since it was first demonstrated in 1998, there have been tremendous developments in CNTFETs, which promise for an alternative material to replace silicon in future electronics. Carbon nanotubes are promising materials for the nano-scale electron devices such as nanotube FETs for ultra-high density integrated circuits and quantum-effect devices for novel intelligent circuits, which are expected to bring a breakthrough in the present silicon technology. A Static Random Access Memory (SRAM) is designed to plug two needs: i) The SRAM provides as cache memory, communicating between central processing unit and Dynamic Random Access Memory (DRAM). ii) The SRAM technology act as driving force for low power application since SRAM is portable compared to DRAM, and SRAM doesn’t require any refresh current. On the basis of acquired knowledge, we present
different SRAM's designed for the conventional CNTFET. HSPICE simulations of this circuit using Stanford CNTFET model shows a great improvement in power saving.
Design and Analysis of Multi Vt and Variable Vt based Pipelined Adder for Lo...VLSICS Design
Majority of Digital Signal Processing (DSP) applications require arithmetic blocks such as multipliers and adders for hardware realization of complex algorithms. Power consumption of arithmetic blocks need to be minimized by use of low power techniques. In this paper, an experimental setup is developed to identify the sources of power dissipation and remedies that can be adopted to minimize power dissipation in arithmetic blocks. Use of low power techniques such as Multi Vt, variable Vt, pipelining, geometry scaling and use of appropriate load capacitance have been used to reduce power dissipation. A 4-bit pipelined adder is designed and the power dissipation is reduced to 4.17µW from 9.6µW. The designed pipelined adder can be used for DSP applications.
.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
The paper presents a low Power consumption plays a vital role in the present day VLSI technology. Power consumption of an electronic device can be reduced by adopt changed design styles. Multipliers play a most important role in high concert systems. This project focus on a novel energy efficient technique called adiabatic logic which is based on energy renewal principle and power is compared by designing a multiplier. CMOS technology plays a main role in designing low power consuming devices, compared to different logic family CMOS has less power dissipation. Adiabatic logic method is assumed to be an attractive solution for low power electronic applications. By using Adiabatic techniques energy dissipation in PMOS network can be minimized and selection of energy stored at load capacitance can be recycled instead of dissipated as heat. Tanner EDA tools are used for simulation.
Comparative Performance Analysis of XORXNOR Function Based High-Speed CMOS Fu...VLSICS Design
This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A low power and high performance 9T full adder cell using a design style called “XOR (3T)” is discussed. The designed circuit commands a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as it lowers power consumption by using XOR (3T) logic circuits. Gate Diffusion Input (GDI) technique of low-power digital combinatorial circuit design is also described. This technique helps in reducing the power consumption and the area of digital circuits while maintaining low complexity of logic design. This paper analyses, evaluates and compares the performance of various adder circuits. Several simulations conducted using different voltage supplies, load capacitors and temperature variation demonstrate the superiority of the XOR (3T) based full adder designs in term of delay, power and power delay product (PDP) compared to the other full adder circuits. Simulation results illustrate the superiority of the designed adder circuits against the conventional CMOS, TG and Hybrid full adder circuits in terms of power, delay and power delay product (PDP).
Implementation of High Reliable 6T SRAM Cell Designiosrjce
Memory can be formed with the integration of large number of basic storing element called cells.
SRAM cell is one of the basic storing unit of volatile semiconductor memory that stores binary logic '1' or '0' bit.
Modified read and write circuits were proposed in this paper to address incorrect read and write operations in
conventional 6T SRAM cell design available in open literature. Design of a new highly reliable 6T SRAM cell
design is proposed with reliable read, write operations and negative bit line voltage (NBLV). Simulations are
carried out using MENTOR GRAPHICS
250nm Technology Based Low Power SRAM Memoryiosrjce
High integration density, low power and fastperformance are all critical parameters in designing of
memory blocks. Static Random Access Memories (SRAMs)’s focusing on optimizing dynamic power concept of
virtual source transistors is used for removing direct connection between VDD and GND.
Also stacking effect can be reduced by switching off the stacktransistors when the memory is ideal and the
leakage current using SVL techniques This paper discusses the evolution of 9t SRAM circuits in terms of low
power consumption, The whole circuit verification is done on the Tanner tool, Schematic of the
SRAM cell is designed on the S-Edit and net list simulation done by using T-spice and waveforms are analyzed
through the W-edit
Energy optimization of 6T SRAM cell using low-voltage and high-performance in...IJECEIAES
The performance of the cell deteriorates, when static random access memory (SRAM) cell is operated below 1V supply voltage with continuous scale down of the complementary metal oxide semiconductor (CMOS) technology. The conventional 6T, 8T-SRAM cells suffer writeability and read static noise margins (SNM) at low-voltages leads to degradation of cell stability. To improve the cell stability and reduce the dynamic power dissipation at low- voltages of the SRAM cell, we proposed four SRAM cells based on inverter structures with less energy consumption using voltage divider bias current sink/source inverter and NOR/NAND gate using a pseudo-nMOS inverter. The design and implementation of SRAM cell using proposed inverter structures are compared with standard 6T, 8T and ST-11T SRAM cells for different supply voltages at 22-nm CMOS technology exhibit better performance of the cell. The read/write static noise margin of the cell significantly increases due to voltage divider bias network built with larger cell-ratio during read path. The load capacitance of the cell is reduced with minimized switching transitions of the devices during high-to-low and low- to-high of the pull-up and pull-down networks from VDD to ground leads to on an average 54% of dynamic power consumption. When compared with the existing ones, the read/write power of the proposed cells is reduced to 30%. The static power gets reduced by 24% due to stacking of transistors takes place in the proposed SRAM cells as compare to existing ones. The layout of the proposed cells is drawn at a 45-nm technology, and occupies an area of 1.5 times greater and 1.8 times greater as compared with 6T-SRAM cell.
Design of Low Write-Power Consumption SRAM Cell Based on CNTFET at 32nm Techn...VLSICS Design
The SRAM which functions as the cache for system-on-chip is vital in the electronic industry. Carbon Nanotube Field Effect Transistor (CNFET) is used for high performance, high stability and low-power circuit designs as an alternative material to silicon in recent years. Therefore Design of SRAM Cell based on CNTFET is important for Low-power cache memory. In cells, the bit-lines are the most power consuming components because of larger power dissipation in driving long bit-line with large capacitance. The cache write consumes considerable large power due to full voltage swing on the bit-line. This Paper proposes a novel 7T SRAM cell based on CNTFET that only depends on one of bit lines for Write operation and reduce the write-power consumption. The read cycle also improved because of careful transistor sizing. HSPICE simulations of this circuit using Stanford CNFET model shows that 37.2% write power saving, read cycle improvement of 38.6%.
CELL STABILITY ANALYSIS OF CONVENTIONAL 6T DYNAMIC 8T SRAM CELL IN 45NM TECHN...VLSICS Design
A SRAM cell must meet requirements for operation in submicron/nano ranges. The scaling of CMOS technology has significant impact on SRAM cell -- random fluctuation of electrical characteristics and substantial leakage current. In this paper we present dynamic column based power supply 8T SRAM cell and comparing the proposed SRAM cell with respect to conventional SRAM 6T in various aspects. To verify read stability and write ability analysis we use N-curve metric. Simulation results affirmed that proposed 8T SRAM cell achieved improved read stability, read current, and leakage current in 45nm Technology comparing with conventional 6T SRAM using cadence virtuoso tool.
SIMULTANEOUS OPTIMIZATION OF STANDBY AND ACTIVE ENERGY FOR SUB-THRESHOLD CIRC...VLSICS Design
Increased downscaling of CMOS circuits with respect to feature size and threshold voltage has a result of
dramatically increasing in leakage current. So, leakage power reduction is an important design issue for
active and standby modes as long as the technology scaling increased. In this paper, a simultaneous active
and standby energy optimization methodology is proposed for 22 nm sub-threshold CMOS circuits. In the
first phase, we investigate the dual threshold voltage design for active energy per cycle minimization. A
slack based genetic algorithm is proposed to find the optimal reverse body bias assignment to set of noncritical paths gates to ensure low active energy per cycle with the maximum allowable frequency at the
optimal supply voltage. The second phase, determine the optimal reverse body bias that can be applied to
all gates for standby power optimization at the optimal supply voltage determined from the first phase.
Therefore, there exist two sets of gates and two reverse body bias values for each set. The reverse body bias
is switched between these two values in response to the mode of operation. Experimental results are
obtained for some ISCAS-85 benchmark circuits such as 74L85, 74283, ALU74181, and 16 bit RCA. The
optimized circuits show significant energy saving ranged (from 14.5% to 42.28%) and standby power
saving ranged (from 62.8% to 67%).
SIMULTANEOUS OPTIMIZATION OF STANDBY AND ACTIVE ENERGY FOR SUB-THRESHOLD CIRC...VLSICS Design
Increased downscaling of CMOS circuits with respect to feature size and threshold voltage has a result of
dramatically increasing in leakage current. So, leakage power reduction is an important design issue for
active and standby modes as long as the technology scaling increased. In this paper, a simultaneous active
and standby energy optimization methodology is proposed for 22 nm sub-threshold CMOS circuits. In the
first phase, we investigate the dual threshold voltage design for active energy per cycle minimization. A
slack based genetic algorithm is proposed to find the optimal reverse body bias assignment to set of noncritical
paths gates to ensure low active energy per cycle with the maximum allowable frequency at the
optimal supply voltage. The second phase, determine the optimal reverse body bias that can be applied to
all gates for standby power optimization at the optimal supply voltage determined from the first phase.
Therefore, there exist two sets of gates and two reverse body bias values for each set. The reverse body bias
is switched between these two values in response to the mode of operation. Experimental results are
obtained for some ISCAS-85 benchmark circuits such as 74L85, 74283, ALU74181, and 16 bit RCA. The
optimized circuits show significant energy saving ranged (from 14.5% to 42.28%) and standby power
saving ranged (from 62.8% to 67%).
SIMULTANEOUS OPTIMIZATION OF STANDBY AND ACTIVE ENERGY FOR SUB-THRESHOLD CIRC...VLSICS Design
Increased downscaling of CMOS circuits with respect to feature size and threshold voltage has a result of dramatically increasing in leakage current. So, leakage power eduction is an important design issue for active and standby modes as long as the technology scaling increased. In this paper, a simultaneous active and standbyrgy optimization methodology is proposed for 22 nm sub-threshold CMOS circuits. In thefirst phase, we investigate the dual threshold voltage design for active energy per cycle minimization. A slack based genetic algorithm is proposed to find the optimal reverse body bias assignment to set of noncritical paths gates to ensure low active energy per cycle with the maximum allowable frequency at the optimal supply voltage. The second phase, determine the optimal reverse body bias that can be applied to
all gates for standby power optimization at the optimal supply voltage determined from the first phase. Therefore, there exist two sets of gates and two reverse body bias values for each set. The reverse body bias is switched between these two values in response to the mode of operation. Experimental results are obtained for some ISCAS-85 benchmark circuits such as 74L85, 74283, ALU74181, and 16 bit RCA. The optimized circuits show significant energy saving ranged (from 14.5% to 42.28%) and standby power saving ranged (from 62.8% to 67%).
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Average and Static Power Analysis of a 6T and 7T SRAM Bit-Cell at 180nm, 90nm...idescitation
A lot of consideration has been given to problems arising due to power dissipation.
Different ideas have been proposed by many researchers from the device level to the
architectural level and above. However, there is no universal way to avoid tradeoffs between
the power, delay and area. This is why; the designers are required to choose appropriate
techniques that satisfy application and product needs. Another important component of
power which contributes to power dissipation is Dynamic Power. This power is increasing
due to prolonged use of the electronic equipments. This is due to the fact that now-a-days
people are working on electronic systems from morning till night; it may be a mobile phone
or a laptop or any other equipment. This paper deals with the estimation of two components
of power i.e. static power (when device is in the standby mode) and the average power
(average amount of energy consumed with respect to time) of a 6T and 7T SRAM (Static
Random Access Memory) bit-cell at 180nm, 90nm, and 45nm CMOS Technology. This is
done in order to estimate the power required for a high speed operation of 6T and 7T
SRAM bit-cell.
PERFORMANCE EVALUATION OF DIFFERENT SRAM CELL STRUCTURES AT DIFFERENT TECHNOL...VLSICS Design
In recent years the demand for low power devices has been increases tremendously. To solve the power dissipation problem, many researchers have proposed different ideas from the device level to the architectural level and above. However, there is no universal way to avoid tradeoffs between power, delay and area, thus designers are required to choose appropriate techniques that satisfy application and product needs. The demand for static random-access memory (SRAM) is increasing with large use of SRAM in System On-Chip and high-performance VLSI circuits. This paper represents the simulation of different SRAM cells and their comparative analysis on different parameters such as Power Supply Voltage, area efficiency etc to enhance the performance. All the simulations have been carried out on BSIM 3V3 90nm, 45nm and 32 technology at Tanner EDA tool.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
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Implementation of Area Effective Carry Select AddersKumar Goud
Abstract: In the design of Integrated circuit area occupancy plays a vital role because of increasing the necessity of portable systems. Carry Select Adder (CSLA) is a fast adder used in data processing processors for performing fast arithmetic functions. From the structure of the CSLA, the scope is reducing the area of CSLA based on the efficient gate-level modification. In this paper 16 bit, 32 bit, 64 bit and 128 bit Regular Linear CSLA, Modified Linear CSLA, Regular Square-root CSLA (SQRT CSLA) and Modified SQRT CSLA architectures have been developed and compared. However, the Regular CSLA is still area-consuming due to the dual Ripple-Carry Adder (RCA) structure. For reducing area, the CSLA can be implemented by using a single RCA and an add-one circuit instead of using dual RCA. Comparing the Regular Linear CSLA with Regular SQRT CSLA, the Regular SQRT CSLA has reduced area as well as comparing the Modified Linear CSLA with Modified SQRT CSLA; the Modified SQRT CSLA has reduced area. The results and analysis show that the Modified Linear CSLA and Modified SQRT CSLA provide better outcomes than the Regular Linear CSLA and Regular SQRT CSLA respectively. This project was aimed for implementing high performance optimized FPGA architecture. Modelsim 10.0c is used for simulating the CSLA and synthesized using Xilinx PlanAhead13.4. Then the implementation is done in Virtex5 FPGA Kit.
Keywords: Field Programmable Gate Array (FPGA), efficient, Carry Select Adder (CSLA), Square-root CSLA (SQRTCSLA).
Design and Simulation Low power SRAM Circuitsijsrd.com
SRAMs), focusing on optimizing delay and power. As the scaling trends in the speed and power of SRAMs with size and technology and find that the SRAM delay scales as the logarithm of its size as long as the interconnect delay is negligible. Non-scaling of threshold mismatches with process scaling, causes the signal swings in the bitlines and data lines also not to scale, leading to an increase in the relative delay of an SRAM, across technology generations. Appropriate methods for reduction of power consumption were studied such as capacitance reduction, very low operating voltages, DC and AC current reduction and suppression of leakage currents to name a few.. Many of reviewed techniques are applicable to other applications such as ASICs, DSPs, etc. Battery and solar-cell operation requires an operating voltage environment in low voltage area. These conditions demand new design approaches and more sophisticated concepts to retain high device reliability. The proposed techniques (USRS and LPRS) are topology based and hence easier to implement.
Similar to IMPLEMENTATION OF LOW POWER ADIABATIC SRAM (20)
Immunizing Image Classifiers Against Localized Adversary Attacksgerogepatton
This paper addresses the vulnerability of deep learning models, particularly convolutional neural networks
(CNN)s, to adversarial attacks and presents a proactive training technique designed to counter them. We
introduce a novel volumization algorithm, which transforms 2D images into 3D volumetric representations.
When combined with 3D convolution and deep curriculum learning optimization (CLO), itsignificantly improves
the immunity of models against localized universal attacks by up to 40%. We evaluate our proposed approach
using contemporary CNN architectures and the modified Canadian Institute for Advanced Research (CIFAR-10
and CIFAR-100) and ImageNet Large Scale Visual Recognition Challenge (ILSVRC12) datasets, showcasing
accuracy improvements over previous techniques. The results indicate that the combination of the volumetric
input and curriculum learning holds significant promise for mitigating adversarial attacks without necessitating
adversary training.
Welcome to WIPAC Monthly the magazine brought to you by the LinkedIn Group Water Industry Process Automation & Control.
In this month's edition, along with this month's industry news to celebrate the 13 years since the group was created we have articles including
A case study of the used of Advanced Process Control at the Wastewater Treatment works at Lleida in Spain
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Saudi Arabia stands as a titan in the global energy landscape, renowned for its abundant oil and gas resources. It's the largest exporter of petroleum and holds some of the world's most significant reserves. Let's delve into the top 10 oil and gas projects shaping Saudi Arabia's energy future in 2024.
Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdffxintegritypublishin
Advancements in technology unveil a myriad of electrical and electronic breakthroughs geared towards efficiently harnessing limited resources to meet human energy demands. The optimization of hybrid solar PV panels and pumped hydro energy supply systems plays a pivotal role in utilizing natural resources effectively. This initiative not only benefits humanity but also fosters environmental sustainability. The study investigated the design optimization of these hybrid systems, focusing on understanding solar radiation patterns, identifying geographical influences on solar radiation, formulating a mathematical model for system optimization, and determining the optimal configuration of PV panels and pumped hydro storage. Through a comparative analysis approach and eight weeks of data collection, the study addressed key research questions related to solar radiation patterns and optimal system design. The findings highlighted regions with heightened solar radiation levels, showcasing substantial potential for power generation and emphasizing the system's efficiency. Optimizing system design significantly boosted power generation, promoted renewable energy utilization, and enhanced energy storage capacity. The study underscored the benefits of optimizing hybrid solar PV panels and pumped hydro energy supply systems for sustainable energy usage. Optimizing the design of solar PV panels and pumped hydro energy supply systems as examined across diverse climatic conditions in a developing country, not only enhances power generation but also improves the integration of renewable energy sources and boosts energy storage capacities, particularly beneficial for less economically prosperous regions. Additionally, the study provides valuable insights for advancing energy research in economically viable areas. Recommendations included conducting site-specific assessments, utilizing advanced modeling tools, implementing regular maintenance protocols, and enhancing communication among system components.
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptxR&R Consult
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Here's a great example: At a large natural gas-fired power plant, where they use waste heat to generate steam and energy, they were puzzled that their boiler wasn't producing as much steam as expected.
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An inspection had shown that a significant amount of hot flue gas was bypassing the boiler tubes, where the heat was supposed to be transferred.
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It is always satisfying when we can help solve complex challenges like this. Do your systems also need a check-up or optimization? Give us a call!
Work done in cooperation with James Malloy and David Moelling from Tetra Engineering.
More examples of our work https://www.r-r-consult.dk/en/cases-en/
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About
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
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Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
Key Features
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface
• Compatible with MAFI CCR system
• Copatiable with IDM8000 CCR
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
Application
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.3, June 2018
DOI: 10.5121/vlsic.2018.9301 1
IMPLEMENTATION OF LOW POWER ADIABATIC
SRAM
Savitha S M1
, H P Rajani2
and Shivaling M Hunagund3
1
Department of Electronics and Communication, Visvesvaraya Technological University,
Belagavi, Karnataka
2
HOD of Department of Telecommunication
3
Asst Prof. of Department of Electronics and Communication
ABSTRACT
In the featuring VLSI era, compact electronic devices are popular. The reliability and durability of such
compact devices relies on low power utilization. The purpose of this project was to implement a low power
adiabatic Static Random Access Memory (SRAM), with the following objectives - To reduce the power
waste by means of stepwise charging using tank capacitors which is an adiabatic way of generating power
clock. This method is capable of recuperating the electrical energy back to the source. Further to examine
the Static Noise Margin (SNM) – a parameter which gives detailed information about the cell stability – in
contrast with conventional 6T, 7T and 8T topologies of SRAM under 180 nm technology. Finally, SNM
variations with respect to process parameters are also discussed. All the implementations and analysis
were made using CADENCE tool and MATLAB tool.
KEYWORDS
SRAM, Adiabatic, CMOS, Stepwise Charging, SNM and Process variations.
1. INTRODUCTION
In the contemporary times, in ubiquity of device minimization is in demand – one of the prime
mottos of low power VLSI. As per Moore’s law, in every 18 months the number of transistors
gets doubled in an Integrated Circuit (IC) [1]. Because of this, the small sized devices face
durability and reliability issues. Main reason for these kinds of issue, is the power dissipation.
Usually in a CMOS IC, half of the power consumed is dissipated in the form of heat. In order to
overcome this, heat sinks were introduced which increases the area of the device, failing to serve
the prime motto.
The main sources of power dissipation in a CMOS circuit are static power dissipation – due to
leakage currents during inactive states, dynamic power dissipation – due charging and
discharging of capacitances and short circuit power dissipation – due to slow rise and fall times.
The total power dissipation is the summation of all the three sources. The majority is due to
dynamic switching activity - to reduce this, various low power design techniques were used.
Many of them were based on clock signals and complement form, which are outdated for the
present day technologies. So, the researches came across a new class of logic called “Adiabatic
logic”. This logic is one of the finest low power design technique.
Usually in a circuit, during the charging and discharging of capacitor half the energy which is
given by 0.5CV2
is wasted, in other words all the energy drawn isn’t converted into useful work.
But in case of adiabatic logic the energy is recuperated back to the source without being
2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.3, June 2018
2
discharged to the ground. Adiabatic logic also uses the method of slow charging instead of fast
charging to reduce the power waste.
2 LITERATURE SURVEY
[1] This book provides a detailed information on MOS – transistors, static and dynamic operating
fundamentals, relevant topics on CMOS low power circuit design. It also provides information
about the design methodologies in VLSI and in-depth presentation of semiconductor memory [1].
It also offers BiCMOS digital circuit design. The book also covers topics such as chip I/O design,
Design for manufacturability and testability [1]. From this book we understood the basics of a
semiconductor memory and adiabatic circuits. [2] It gives an overview of SRAM circuit design
and testing. It offers a detailed understanding for the readers on topics of cell stability and its
testing techniques. This book helped me in understanding how to measure the cell stability and
the factors affecting the cell stability. [3] The document provided a detailed description of SRAM
which was used to design an 8 X 8 SRAM IC. SRAM IC was developed using the CDS IC446,
cadence IC design environment. The design was based on the AMI 0.6-micron process [3]. This
report assisted me in designing the peripheral circuits required for a single read and write
operation of AN SRAM cell. It also provided an idea to build an array of required size. [4]. It
furnishes a systematic and a complete view of SRAM bit cell circuits, architectures, and design
and analysis techniques [4]. This book is indeed a great help for VLSI design engineers to design
SRAM and cache architecture reasonably [4]. This book aided me in understanding the
theoretical background of all the peripherals of an SRAM and also came across the different
topologies of low power SRAMs and their classifications based on the robustness. [5] It aids the
readers with the benefits of adiabatic logic and generation of power clocks to reduce the energy
consumption. This book also deals with the basic fundamentals and the future trends. With the
help of this book the concept of adiabatic logic was much clearer. [6] It was mainly based on the
power clock generation using step charging concept. The authors stated that their work wasn’t
compared with any of their referral records. The concept was to recover the energy in an efficient
manner through step charging the concerned circuit. [7] The author proposed a new and stable
way to generate a power clock using asymmetric tank capacitors. Later the same concept was
applied to develop a low power SRAM. [8] In this paper a design procedure for driver to
minimize power [8]. [9] In this paper, the design and functionality of a novel ultra-low power
stable SRAM cell is discussed which addresses power minimization as well as stability against
large variation in temperature which is ideally suited for space applications. This paper explores a
novel circuit level approach to reduce power in the SRAM cell during active mode of operation as
well as standby mode by incorporating NMOS-PMOS pair in each pull down path. [10] In this
paper an analytical method to analyse the stepwise charging of adiabatic circuits was suggested
by the authors. From this paper a detailed study on stepwise charging is obtained.
3 SRAM CELL DESIGN AND OPERATION
3.1 SRAM BLOCK ASSEMBLY
The following is an example of a basic SRAM block. It consists of RxC array of SRAM cells,
where R is the number of rows and C is the number of bits. With the help of a row decoder, a
particular row of interest can be selected, this is possible by decoding the address to select one of
the word lines W1 to WN. Usually the SRAM arrangement is either bit aligned or word aligned.
If it is bit aligned then each address retrieves a single bit, else retrieves a word of s bits where s
includes 8, 16, 32 or 64. A single sense amplifier can be distributed to more than one column with
the assistance of a column decoder.
3. International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.3, June 2018
3
SRAM Block Architecture
3.2 6T SRAM
The conventional circuit of one bit SRAM cell consists of 6 transistors or MOSFETs, the
arrangement consists of two inverters which are connected back to back in a cross manner (i.e.,
the output of 1st
inverter is connected to the input to the 2nd
and vice versa). It is same as a flip
flop - a b is table element. In a SRAM cell not only the data bit but its compliment is also stored.
The data bit is stored and retrieved from the bit cell with the help of word line (WL) and bit lines
(BL and BLB). The transistors (P1, P2), (N1, N2) and (N3, N4) are load, driver and access
transistors respectively. The word line is connected to the gate of the access transistor and the bit
lines carry the bit voltage that is to be stored in the cell.
Conventional 6TSRAM cell.
A. READ OPERATION
1. Precharge the bitlines up to 0.5Vdd using a precharge circuitry.
2. For the read operation to begin the word line goes high.
3. Based on the data stored at node Q charging and discharging of the capacitances
happen. If Q=0 then the charge is discharged else it is charged.
4. The sense amplifier senses the data bit by converting the differential signal to
logic level.
5. Word line is made low.
4. International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.3, June 2018
4
6T SRAM during read operation.
During read operation with Q = Vdd, the corresponding schematic diagram is as shown in the
figure. When the voltage at node QB reaches the threshold voltage of the NMOS- N1, the voltage
at Q starts to decrease and the renewal action of the coupled inverter will force the bit stored to
overturn.
B. WRITE OPERATION
1. Initially the word line is made low.
2. Precharge the bitlines up to Vdd /2 using precharge circuitry.
3. For the write operation the bit lines are connected from the Vdd
4. Word line is made high.
5. The data to be written is placed on the bitlines (BL and BLB)
6. Once the Q and QB overturns its state, word line is made low.
6T SRAM during write operation.
3.3 PERIPHERAL CIRCUITS
For the read and write operation of SRAM peripheral circuits such as precharge circuit, sense
amplifier, mux for BLB and mux for BL are necessary.
5. International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.3, June 2018
5
A. PRECHARGE CIRCUIT
It consists of 2 PMOSFETs, the sources of the MOSFETs are connected to the supply voltage -
for the project a voltage=2.5V was preferred. The gates of the transistors are connected to the
precharge control stimuli. The drains are connected to the bitlines (BL and BLB) which as shown
in the figure.
The purpose of using this circuit is to maintain the uniformity of the bitlines before the read and
write operation. The bitlines are pulled to Vdd.
Precharge circuit
B. SENSE AMPLIFIER
It is the most important circuit during the read phase, it is used to sense the bit voltage by
converting the differential signal on BL and BLB to a digital signal. A current mirror differential
sense amplifier [2] was used for the project. The configuration consists of 2 PMOSFETs and 3
NMOSFETs which are in contact accordingly, as seen in the figure.
Current mirror differential sense amplifier
C. MUX FOR BITLINES
It is also an important peripheral circuit, which is engaged in the write phase. The following
figures represent the mux circuits for BL and BLB respectively. The data is not written into the
cell unless and until the W_E (Write Enable) signal is made high [3]. The right mux is connected
6. International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.3, June 2018
6
to BLB and left mux is connected to BL, it can be connected the other way around also. The main
difference between the left mux and right mux is the inverter which is used to invert the data. The
data and inverted data are sent to the bitlines BL and BLB.
The following figures shows the detailed connection of all the transistors forming the
multiplexers.
Mux for bit line BL
Mux for the bit line BLB.
3.4 SINGLE READ AND WRITE SRAM CELL
Merging all the above peripheral circuits with SRAM, single read and write cell is configured.
The following figure shows the configuration, the stimuli given to the circuit are as follows 1-
precharge, 2-data (bit 0 or 1), 3-write_enable (it gives the authority to write the data into the cell),
7. International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.3, June 2018
7
4-sense (it validates the bit which is stored in the cell) and 5-word_line (resolves at which address
the bit is registered) [3].
Single read and write SRAM cell.
4 VARIOUS CONFIGURATIONS OF SRAM
There are two more configurations that are discussed in this project, they are 7T and 8T SRAM.
Concentrating on the fundamental factors of the low power VLSI design, these configurations
were depicted to reduce the power consumption, improve the cell stability, efficiency and the
performance.
4.1 7T SRAM
The figure below shows the configuration of the 7T SRAM, it was designed to reduce the power
consumption and to have a better read accessed SNM. It is similar to the 6T structure with an
extra NMOS whose gate is connected to the word line. The read and write operations are similar
as that of 6T SRAM.
7T SRAM
8. International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.3, June 2018
8
4.2 8T SRAM
The structure slightly varies from 6T and 7T, because it uses control signals such as RWL (Read
Word Line) and RD (Read signal). It is same as that of 6T SRAM cell with two extra transistors
connected to the control signal RD which is used only and mainly during the read operation along
with RWL=1. During write operation BL and BLB along with WWL =1 is used.
8T SRAM
5 ADIABATIC LOGIC
Adiabatic is a Greek word which signifies that it is impassable to heat, in other words no trade of
heat between a system and the neighbouring environment. The fundamentals of adiabatic logic
are as follows
1. When there is no voltage between the nodes, the switches are ON.
2. The switches are OFF, when there no current run across the nodes.
3. Use an active element that is able to recuperate the energy in the form of charge.
All the above fundamentals are attained by a time varying current source instead of a voltage
source. Customarily, the designers underplay with the events, the node capacitances or the
voltage swings to reduce the power waste.
Adiabatic switching ciruits require non-constant, non-standard power supply with time-varying
voltage. This power supply is known as “Pulsed power supplies” or “power clock”. These power
supplies use circuit components capable of restoring the energ. Inverting the current supply
causes the energy to flow from the load capacitance back into the power supply. So, the power
supplies must be designed to retrieve the energy fed back to it.
5.1 REALIZATION OF POWER CLOCK
The following circuit is capable of creating a power clock by charging the load capacitor in a
stepwise manner using tank capacitors, the steps may vary from 2 to n-1, the switches 1 to N are
closed in an incresing order.The charge at the load capacitor varies from 0 to Vdd insteps of 0 to
Vdd/n, Vdd /n to 2Vdd /n and so on. The overhead limits the practical number of steps to 10, but
larger the number of steps greater is the reduction in power waste.
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Stepwise Charging using tank capacitors
5.2 REALIZATION OF ADIABATIC GATES
Adiabatic logic can be realized for any conventional CMOS logic just by replacing each pMOS
and nMOS devices in the pull-up and pull-down networks respectively with interdependent
transmission gates (T-gates).
As all the stimuli must be available in complementary form, both the networks in the adiabatic
logic circuit are used to charge-up as well as charge-down the output capacitances. We can use
expanded pull-up and pull-down networks to drive true and inverse output respectively.
Replace DC source Vdd by a pulse power supply with varying voltage to allow adiabatic
operation.The pulsed power supply or the power clock is capable of recovering the energy backto
source reducing the power waste.
Conventional and Adiabatic Logic
6 STATIC NOISE MARGIN
Static Noise Margin (SNM) is a stability metric of an SRAM cell interpreted by the Voltage
Transfer Characteristics (VTC) of the back to back connected inverters of the SRAM. The
measurements can be made for read accessed, write accessed and stable/hold SRAMs. On the
whole the Noise Margin is an acceptable signal by the device still maintaining the correctness of
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the operation. If it is a dc or static signal, then it lasts long affecting the correctness. It can be
controlled by latching the signal. It is generally used to find a weak SRAM cell by adding a noise
voltage source which is as shown in the figure below.
A. READ ACCESSED SNM (RSNM)
Usually the RSNM presents the worst case SNM of the SRAM cell. RSNM is given by side
length of the largest square inscribed inside the lobes of the butterfly curve, which is formed by
the VTCs of the inverter of the SRAM. This approach was depicted by Hill in the year 1968[2].
This method is for ideal SRAMs, but in real the squares inscribed aren’t equal, so the side length
of a smaller square is considered. The nature of graph is as shown below
Nature of graph of RSNM
PROCEDURE TO FIND THE RSNM
Connect a noise voltage X=0 at the output of one of the inverters. Both the bitlines are precharged
to Vdd/2 and the word line is enabled. Plot the VTC of both the inverters to form a butterfly plot.
Now fit a largest square into the eye lobes of the butterfly plot. Higher the value of RSNM better
the read stability of the SRAM cell.
B. Write Accessed SNM (WSNM)
WSNM depicts the write stability of the SRAM cell. It is given by side length of the largest
square inscribed between the VTC of the inverters of SRAM cell. The nature of graph is as shown
below
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Nature of graph of WSNM
PROCEDURE TO FIND WSNM
The two inverters of the SRAM are broken apart to find the WSNM, the bitlines BL and BLB
consists of the bit and its complement (say 0 and 1 or 1 and 0) respectively. Once the word line is
enabled, plot the VTC of the both inverters. Now fit a largest square in the region between the
characteristic curves.
C. Hold SNM
It depicts the stability of the cell in standby mode or idle (i.e. when it is holding a value). The
nature of the graph of hold SNM is same as that of read accessed SNM. It is a perfect butterfly
plot.
PROCEDURE TO FIND HOLD SNM
The procedure is same as that of RSNM, except for the word line to be disabled.
Nature of graph of Hold SNM.
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6.1 SRAM SNM AND PROCESS PARAMETER VARIATIONS
To get an intense intuition of the reactivity of SNM due to process variables - such as
temperature, supply voltage, Cell Ratio (CR) and Pull-up Ratio (PR) - simulations are performed
by varying the process variables.
Cell Ratio is the ratio of W/L of driver transistor to the W/L of the access transistor. It is mainly
concerned during the read operation. CR is directly proportional to SNM.
Pull-up Ratio is the ratio of W/L of load to W/L of access transistors. It is of concern during the
write operation. SNM increases as it increases.
The dependence of SNM on process variables is clearly seen in the results and discussion chapter
of the report.
7 RESULTS AND DISCUSSION
The following graphs depict the average power consumed during read write operation by CMOS
and Adiabatic SRAM topologies, under 180nm technology with voltages 1.8 V and 2.5 Volts.
Power consumption when Vdd=1.8 V
Power consumption when Vdd=2.5V
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7.1 INFLUENCE OF PROCESS PARAMETERS ON SNM OF CMOS SRAM.
With different process variations such as temperature, supply voltage, CR and PR the SNM
calculations were made in all the modes.
A. 6T SRAM
Variation of Pull-up Ratio keeping the Cell ratio constant i.e. equal to 2 is as shown in the figure.
The WSNM varies accordingly with the PR from 1 to 2.5 with equal steps of 0.25 but the RSNM
does not vary.
Contrast of RSNM and WSNM of 6T SRAM with CR=2
Now keeping the PR=1 and varying the CR from 1 to 2.5 in steps of 0.25 at a time we observe
that, RSNM varies accordingly with CR and WSNM remains almost constant.
Contrast of RSNM and WSNM of 6T SRAM with PR=1
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SNM values of 6T SRAM in all the modes
The variation of RSNM with respect to temperature and power supply is observed now, variation
in temperature ranges from -140 to 140 degree Celsius with Vdd = 1 V and supply voltage from
1.1 to 2.5 in 5 steps at room temperature equal to 27 degree Celsius.
From the above graph we see that the RSNM decreases as the temperature increases. Hence the
RSNM is more stable at less temperature. More the SNM more is the stability. From the table we
observe that the RSNM, WSNM and Hold SNM values of 6T SRAM decreases as the voltage and
temperature increases.
B. 7T SRAM
Variation of RSNM and WSNM according the PR and CR values is seen in the subsequent
graphs. The behaviour is same as that of 6T SRAM.
Contrast of RSNM and WSNM of 7T SRAM with CR=2
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Contrast of RSNM and WSNM of 7T SRAM with PR=1
The WSNM varies when CR is constant and remains the same for constant PR.
The variation of SNM with respective to temperature and supply voltage is given by the table 2
SNM values of 7T SRAM in all the modes
C. 8T SRAM
The SNM results of 8T SRAM are discussed below.
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Variation of RSNM and WSNM of 8T SRAM with CR=2
Variation of RSNM and WSNM of 8T SRAM with PR=1
The behaviour of SNM in all the modes with respect to the process parameters such as supply
voltage and temperature.
SNM values of 8T SRAM in all the modes.
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CONCLUSION
A low power adiabatic SRAM has been implemented using the stepwise charging process with
the help of tank capacitors. From the results and discussion, we conclude that the stepwise
charging method is appropriate for 8T cell, because the power consumption was reduced by 22.72
and 26.27 percent for Vdd=1.8V and Vdd=2.5 V respectively.
From the detailed analysis of RSNM, WSNM and Hold SNM of 6T, 7T and 8T SRAM cells we
conclude that the stability of 6T SRAM and 8T SRAM cell is better than the 7T SRAM cell.
Hence 8T cell is more appropriate for low power applications with good SNM at different process
variations. Thus from all the implementations and analysis, the project concludes that the 8T
SRAM cell with step charging method is the low power adiabatic SRAM.
ACKNOWLEDGEMENTS
The satisfaction and euphoria that accompany the successful completion of any task would
be incomplete without the people who made it possible. I take this opportunity to express my
gratitude to the people who have been instrumental in the successful completion of the
work. With profound sense of gratitude, I acknowledge the opportunity to thank my internal
guides Dr H.P. Rajani and Prof. Shivaling M Hunagund, Dept. of Electronics &
Communication Engineering, for his kind support that he has provided throughout this effort.
It gives me an immense pleasure in thanking my P.G. Coordinator Prof. Nataraj A. Vijapur,
Dept. of Electronics & Communication Engineering, for extending all kind of guidance.
I express my heart full gratitude to Prof. S.B. Kulkarni, Head of Electronics & Communication
Engineering Dept., for providing the necessary facilities and advice to make this training a
success. I am thankful to Dr. Basavaraj G. Katageri, Principal K.L.E Dr M. S. Sheshgiri
College of Engineering and Technology, Belagavi who had been a source of inspiration and for
his timely guidance in the conduct of my project. I acknowledge gratefully this support,
encouragement and patience of all those who have been involved with this work directly or
indirectly.
REFERENCES
[1] Sung – Mo (Steve) Kang and Yusuf Leblebigi, CMOS DIGITAL INTEGRATED CIRCUITS
ANALYSIS AND DESIGN, 3rd Edition. Tata McGraw-Hill Education, New York, 2003.
[2] Andrei Pavlov and Manoj Sachdev, CMOS SRAM CIRCUIT DESIGN AND PARAMETRIC TEST
IN NANO-SCALED TECHNOLOGIES PROCESS – AWARE SRAM DESIGN AND TEST,
Springer Publications, 2008.
[3] Irina Vazir, Prabhjot S. Balaggan, Sumandeep Kaur and Cailan Shen, SRAM IP FOR DSP/SOC
PROJECTS.
[4] Jawar Singh, Saraju P.Mohanty and Dhiraj K. Pradhan, ROBUST SRAM DESIGNS AND
ANALYSIS, Springer Publications, 2013.
[5] Philip Teichmann, ADIABATIC LOGIC FUTURE TREND AND SYSTEM LEVEL
PERSPECTIVE, Springer Series in Advanced Microelectronics, 2012.
[6] Himadri Singh Raghav, Vivian A.Bartlett and Izzet Kale, INVESTIGATION OF STEPWISE
CHARGING CIRCUITS FOR POWER-CLOCK GENERATION IN ADIABATIC LOGIC, 12th
Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) IEEE, 2016.
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[7] Shunji Nataka, THE STABILITY OF ADIABATIC REVERSIBLE LOGIC USING ASYMMETRIC
TANK CIRCUITS AND ITS APPLICATION TO SRAM, IEICE Electronics Express, Vol.2, No.20,
512-518, 2005.
[8] L. “J.” Svensson and J.G. Koller, DRIVING A CAPACITIVE LOAD WITHOUT DISSIPATING
fCV2, IEEE Symposium on Low Power Electronics, 1994.
[9] Rajani H. P., Hansraj Guhilot and S.Y. Kulkanri, NOVEL STABLE SRAM FOR ULTRA LOW
POWER DEEP SUBMICRON CACHE MEMORIES, IEEE International Conference on Recent
Advances in Intelligent Computational Systems, RAICS 2011.
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FAST LOAD-CHARGE-PRESERVING SWITCHING PROCEDURE FOR THE STEPWISE
ADIABATIC CIRCUITS, IEEE Transactions on Circuits and Systems, 2016.
AUTHORS
Savitha S.M has obtained B.E Degree in Electronics and Communication from
Basaveshwar Engineering College Bagalkot. She is pursuing her postgraduate degree
in M.Tech in VLSI Design and Embedded systems at K.L.E.Society’s Dr M S
Sheshgiri College of Engineering and Technology, Belagavi. Research interests are
Low power VLSI design.
Dr Rajani H.P has received B.E Degree in Electronics and Communication from
Karnataka University, Karnataka. She has obtained her M.Tech degree from N.I.T.K
(K.R.E.C), Surathkal. She is currently heading the Department of Telecommunication
Engineering at K.L.E.Society’s Dr M S Sheshgiri College of engineering and
Technology. She has several publications in International Conferences and Journals to
her credit. Her research interests include design of low power CMOS circuits and
Memories, Performance Improvement in CMOS circuits, Computer Organization,
Embedded Systems etc. She has served as invited member for Board of Studies (BOS),
Member of Board of Examiners (BOE) and as visiting faculty at Visvesvaraya Technological University
(VTU).
Shivaling M Hunagund has received B.E Degree in Electronics and Communication
from University BDT College of Engineering, Davangere. He has obtained his M.Tech
degree in Digital Electronics from B.V.B College of Engineering and Technology,
Hubli. He is a Former Assistant Professor in the Department of Electronics and
Communication Engineering pursuing at K.L.E.Society’s Dr M S Sheshgiri College of
Engineering and Technology.