International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
This paper presents combinations of level shifted pulse-width modulation algorithm with conventional discontinuous pulse-width modulation methods for cascaded multilevel inverters. In the proposed DPWM a zero sequence signal is injected in sinusoidal reference signal to generate various modulators with easier implementation. The analysis four various control strategies namely Common Carrier (CC), Inverted Carrier (IC), Phase Shifted (PS) and Inverted Phase Shift (IPS) for cascaded multilevel inverter fed induction motor drive has been illustrated. To validate the proposed work experimental tests has been carried out using dSPACE controller. Experimental study proves that using proposed algorithms reduction in common-mode voltage with fewer harmonics along with reduced switching loss for a cascaded multilevel inverter fed motor drive has been achieved.
Harmonic Minimization In Multilevel Inverters By Using PSOIDES Editor
Harmonic Elimination in a multilevel inverters is
an optimization problem which is solved by applying particle
swarm optimization (PSO) technique. The derived equation
for the computation of total harmonic distortion (THD) of the
output voltage of the multilevel inverter is used as the objective
function in PSO algorithm. The objective function used is to
reduce the THD of the multilevel inverter and obtain the
corresponding switching angles with the elimination of
possible lower order harmonics. In this paper a pseudo code
based algorithm is proposed to deal with inequality constraints
which will helps in accelerating the optimization process. The
proposed method is applied for seven level cascade inverter to
eliminate the 5th and 7th order harmonics to reduce the total
harmonic distortion .This proposed PSO algorithm is effective
in reducing the total harmonic distortion corresponding the
range of modulation index. The simulation results shows that
the proposed PSO method is indeed capable of obtaining
higher quality of solutions to eliminate 5th and 7th order
harmonics and to reduce the total harmonic distortion of 7-
level cascade inverter
Torque Ripple Minimization of a BLDC Motor Drive by Using Electronic Commutat...AI Publications
Brushless DC motors are having a major problem with harmonics in torque. The variations in speed and production of noise should be minimized by using proper topologies. BLDC motors have been gaining attention from different Industrial and domestic appliance manufacturers, because of their high efficiency, high power density and easy maintenance and low cost. This paper presents a three phase BLDC motor with low cost drive to be driven without DC link capacitor. The proposed technique uses an electronic commutation and operates the machine exclusive of the intermediate DC link capacitor. The designing of Brushless DC motor drive system along with control system for torque ripple minimization, speed controller and current controllers are presented using MATLAB / SIMULINK and results are evaluated.
International Journal of Engineering Research and DevelopmentIJERD Editor
Electrical, Electronics and Computer Engineering,
Information Engineering and Technology,
Mechanical, Industrial and Manufacturing Engineering,
Automation and Mechatronics Engineering,
Material and Chemical Engineering,
Civil and Architecture Engineering,
Biotechnology and Bio Engineering,
Environmental Engineering,
Petroleum and Mining Engineering,
Marine and Agriculture engineering,
Aerospace Engineering.
Investigation of TTMC-SVPWM Strategies for Diode Clamped and Cascaded H-bridg...ijeei-iaes
This paper presents a concept of two types multilevel inverters such as diode clamped and cascaded H-bridge for harmonic reduction on high power applications. Normally, multilevel inverters can be used to reduce the harmonic problems in electrical distribution systems. This paer focused on the performance and analysis of a three phase seven level inverter including diode clamped and cascaded H-bridge based on new tripizodal triangular space vector PWM technique approaches. TTMC based modified Space vector Pulse width modulation technique so called tripizodal triangular Space vector Pulse width modulation (TTMC-SVPWM) technique. In this paper the reference sine wave generated as in case of conventional off set injected SVPWM technique. It is observed that the TTMC-Space vector pulse width modulation ensures excellent, close to optimized pulse distribution results and THD is compared to seven level, diode clamped and cascaded multi level inverters. Theoretical investigations were confirmed by the digital simulations using MATLAB/SIMULINK software.
This paper presents combinations of level shifted pulse-width modulation algorithm with conventional discontinuous pulse-width modulation methods for cascaded multilevel inverters. In the proposed DPWM a zero sequence signal is injected in sinusoidal reference signal to generate various modulators with easier implementation. The analysis four various control strategies namely Common Carrier (CC), Inverted Carrier (IC), Phase Shifted (PS) and Inverted Phase Shift (IPS) for cascaded multilevel inverter fed induction motor drive has been illustrated. To validate the proposed work experimental tests has been carried out using dSPACE controller. Experimental study proves that using proposed algorithms reduction in common-mode voltage with fewer harmonics along with reduced switching loss for a cascaded multilevel inverter fed motor drive has been achieved.
Harmonic Minimization In Multilevel Inverters By Using PSOIDES Editor
Harmonic Elimination in a multilevel inverters is
an optimization problem which is solved by applying particle
swarm optimization (PSO) technique. The derived equation
for the computation of total harmonic distortion (THD) of the
output voltage of the multilevel inverter is used as the objective
function in PSO algorithm. The objective function used is to
reduce the THD of the multilevel inverter and obtain the
corresponding switching angles with the elimination of
possible lower order harmonics. In this paper a pseudo code
based algorithm is proposed to deal with inequality constraints
which will helps in accelerating the optimization process. The
proposed method is applied for seven level cascade inverter to
eliminate the 5th and 7th order harmonics to reduce the total
harmonic distortion .This proposed PSO algorithm is effective
in reducing the total harmonic distortion corresponding the
range of modulation index. The simulation results shows that
the proposed PSO method is indeed capable of obtaining
higher quality of solutions to eliminate 5th and 7th order
harmonics and to reduce the total harmonic distortion of 7-
level cascade inverter
Torque Ripple Minimization of a BLDC Motor Drive by Using Electronic Commutat...AI Publications
Brushless DC motors are having a major problem with harmonics in torque. The variations in speed and production of noise should be minimized by using proper topologies. BLDC motors have been gaining attention from different Industrial and domestic appliance manufacturers, because of their high efficiency, high power density and easy maintenance and low cost. This paper presents a three phase BLDC motor with low cost drive to be driven without DC link capacitor. The proposed technique uses an electronic commutation and operates the machine exclusive of the intermediate DC link capacitor. The designing of Brushless DC motor drive system along with control system for torque ripple minimization, speed controller and current controllers are presented using MATLAB / SIMULINK and results are evaluated.
International Journal of Engineering Research and DevelopmentIJERD Editor
Electrical, Electronics and Computer Engineering,
Information Engineering and Technology,
Mechanical, Industrial and Manufacturing Engineering,
Automation and Mechatronics Engineering,
Material and Chemical Engineering,
Civil and Architecture Engineering,
Biotechnology and Bio Engineering,
Environmental Engineering,
Petroleum and Mining Engineering,
Marine and Agriculture engineering,
Aerospace Engineering.
Investigation of TTMC-SVPWM Strategies for Diode Clamped and Cascaded H-bridg...ijeei-iaes
This paper presents a concept of two types multilevel inverters such as diode clamped and cascaded H-bridge for harmonic reduction on high power applications. Normally, multilevel inverters can be used to reduce the harmonic problems in electrical distribution systems. This paer focused on the performance and analysis of a three phase seven level inverter including diode clamped and cascaded H-bridge based on new tripizodal triangular space vector PWM technique approaches. TTMC based modified Space vector Pulse width modulation technique so called tripizodal triangular Space vector Pulse width modulation (TTMC-SVPWM) technique. In this paper the reference sine wave generated as in case of conventional off set injected SVPWM technique. It is observed that the TTMC-Space vector pulse width modulation ensures excellent, close to optimized pulse distribution results and THD is compared to seven level, diode clamped and cascaded multi level inverters. Theoretical investigations were confirmed by the digital simulations using MATLAB/SIMULINK software.
Analysis and Implementation of Unipolar PWM Strategies for Three Phase Cascad...IJAAS Team
This paper presents unipolar pulse width modulation technique with sinusoidal sampling pulse width modulation are analyzed for three-phase five-level, seven-level, nine-level and eleven-level cascaded multi-level inverter. The unipolar PWM method offers a good opportunity for the realization of the Three-phase inverter control, it is better to use the unipolar PWM method with single carrier wave compared to two reference waves. In such case the motor harmonic losses will be considerably lower.The necessary calculations for generation of unipolar pulse width modulation strategies have presented in detail. The unipolar SPWM voltage switching scheme is selected in this paper because this method offers the advantages of effectively doubling the switching frequency of the inverter voltage. The cascaded multi level inverter fed induction motor is simulated and compared the total harmonic distroction for all level (five-level, seven-level, nine-level and elevel-level)of the inverter. Theoretical investigations were confirmed by the digital simulations using MATLAB/SIMULINK software.
This paper presents new modified space vector pulse width modulation techniques (Phase disposition-Space vector pulse width modulation, Alternative Phase Opposition disposition- Space vector pulse width modulation and Phase Opposition disposition-Space vector pulse width modulation) are analyzed for three-phase cascaded multi-level inverter fed induction motor from the point of view of the Phase voltages, line voltage, stator current,speed,torque and Total harmonic distortion.in the proposed modified technique the reference signals are generated by adding offset voltage to the reference phase voltages.This modified SVPWM technique does not involve region indentification,sector identification for switching vector determination as are required in the conventional multi level SVPWM technique,it is also reduces the computation time compared to the conventional space vector PWM technique.The necessary calculations for generation of new modified SVPWM for the modulation strategies have presented in detail. It is observed that the modified SVPWM modulation ensures excellent, close to optimized pulse distribution results and THD is compared to for five-level, seven-level, nine-level and eleven-level Cascaded H-Bride Multi-level Inverter fed to Induction motor. Theoretical investigations were confirmed by the digital simulations using MATLAB/SIMULINK software.
Ieee Power Electronics Ieee Project Titles, 2009 2010 Ncct Final Year Projectsncct
Final Year Projects, IEEE Projects, Final Year Projects in Chennai, Final Year IEEE Projects, final year projects, college projects, student projects, java projects, asp.net projects, software projects, software ieee projects, ieee 2009 projects, 2009 ieee projects, embedded projects, final year software projects, final year embedded projects, ieee embedded projects, matlab projects, microcontroller projects, vlsi projects, dsp projects, free projects, project review, project report, project presentation, free source code, free project report, Final Year Projects, IEEE Projects, Final Year Projects in Chennai, Final Year IEEE Projects, final year projects, college projects, student projects, java projects, asp.net projects, software projects, software ieee projects, ieee 2009 projects, 2009 ieee projects, embedded projects, final year software projects, final year embedded projects, ieee embedded projects, matlab projects
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
A Three-to-Five-Phase Matrix Converter BasedFive- Phase Induction Motor Drive...idescitation
This paper presents a five-phase induction motor drive
system fed from a three-to-five-phase matrix converter. This
is a new concept of generating variable voltage and variable
frequency five-phase output using a special matrix converter.
This matrix converter is proposed recently which transform
the available three-phase supply to five-phase supply. Simple
carrier-based PWM scheme with enhanced approach is
employed to control the output of the matrix converter.
Enhanced approach is utilized so as to increase the output
voltage magnitude of the three-to-five-phase matrix converter.
The motor is controlled in constant v/f mode. Simulation study
is carried out for excitation, acceleration, loadingand reversing
transients. High quality dynamics are observed.
Voltage profile enhancement in distribution network using static synchronous ...IJECEIAES
STATCOM is one of FACTS devices that used as regulator for transmission and distribution systems which works for reactive power compensation. STATCOM utilisation in distribution system mostly for enhancing the profile of voltage, where used for adjusting the disturbance voltage by injecting into the system a controllable voltage. This paper present a Fuzzy controller based on STATCOM to enhance the voltage profile in distribution network. The controller of STATCOM has simulated for different types of abnormal load conditions of balance and unbalance load. The results of simulation show ability of proposed design to enhance the load voltage which was 96% of the nominal value.
In present days of electrical industries, adjustable speed controlled induction
motor drives are very common due to its versatile features. For the speed control of induction
motor, variable frequency sources are the heart of such drives. To attain variable frequency
and variable voltage supply a power electronics device; single phase matrix converter is
proposed.
In this paper, the single phase matrix converter is modeled in MATLAB Simulink
environment; controlled with sinusoidal pulse width modulation technique, control scheme is
implemented in a Xilinx system generator environment and interfaced with power circuit in
MATLAB Simulink. Analyses this SPMC with different type of loads in both frequency step
up and step down modes. Based on simulation results, this converter is suitable for variable
frequency power supplies, varying load conditions and variable speed electrical drives.
FPGA control is best suitable for controlling a circuit like SPMC, consists of more
controlled elements to attain fast operation.
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
The papers for publication in The International Journal of Engineering& Science are selected through rigorous peer reviews to ensure originality, timeliness, relevance, and readability.
Direct Torque Control of Induction Motor Drive Fed from a Photovoltaic Multil...IJERA Editor
This paper presents Direct Torque Control (DTC) using Space Vector Modulation (SVM) for an induction motor drive fed from a photovoltaic multilevel inverter (PV-MLI). The system consists of two main parts PV DC power supply (PVDC) and MLI. The PVDC is used to generate DC isolated sources with certain ratios suitable for the adopted MLI. Beside the hardware system, the control system which uses the torque and speed estimation to control the load angle and to obtain the appropriate flux vector trajectory from which the voltage vector is directly derived based on direct torque control methods. The voltage vector is then generated by a hybrid multilevel inverter by employing space vector modulation (SVM). The inverter high quality output voltage which leads to a high quality IM performances. Besides, the MLI switching losses is very low due to most of the power cell switches are operating at nearly fundamental frequency. Some selected simulation results are presented for system validation.
In analyzing the problems in South Sulawesi transmission system, simulations of PSCAD / EMTDC [5-6] and PWS (Power World Simulator) [7] software were used to simulate changes in electrical current and voltage during a disturbance.
-Single phase to Ground,
-Line to Fault Line,
-Double Line to Ground
-Three phase Short Circuit
The traction inverter is a crucial power device in the electric vehicle’s powertrain, and its failure is intolerable as it would considerably compromise the system’s safety. For more reliable driving, installing a traction inverter that is sufficiently resistant to electrical failure is inherent. Due to its compact size and the small number of switches incorporated in three-phase four-switch inverter, this modular topology was used to compensate for the open switch’s failure. However, it is known to have manifold weaknesses mainly distinguished in the low-frequency region. This paper introduces a new fault-tolerant indirect control that handles the IGBT’s failure constituting the traction inverter. The fault compensator is designed first based on the Proportional Integral regulator combined with the notch filter to mitigate the current imbalance and restore the DC voltage equilibrium.Furthermore, to conceive a comprehensive fault-tolerant control, there must therefore contain an accurate fault detector. In this regard, an uncomplicated fault diagnosis method based on the current spectral analysis has been performed. The effectiveness of the submitted controller was validated by simulation using Matlab.
Power System Simulation Laboratory Manual Santhosh Kumar
Date:-(13-07-2016)
Hii friends
I Have Attached Our Power System Simulation Laboratory Manual Here for your Reference
Kindly download the Manual and Start Writing the Observation Note By Mr.G.Shivaraj-AP/EEE
Please follow it friends✌
With Happy,
Šαηтн๑zzζzz
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Analysis and Implementation of Unipolar PWM Strategies for Three Phase Cascad...IJAAS Team
This paper presents unipolar pulse width modulation technique with sinusoidal sampling pulse width modulation are analyzed for three-phase five-level, seven-level, nine-level and eleven-level cascaded multi-level inverter. The unipolar PWM method offers a good opportunity for the realization of the Three-phase inverter control, it is better to use the unipolar PWM method with single carrier wave compared to two reference waves. In such case the motor harmonic losses will be considerably lower.The necessary calculations for generation of unipolar pulse width modulation strategies have presented in detail. The unipolar SPWM voltage switching scheme is selected in this paper because this method offers the advantages of effectively doubling the switching frequency of the inverter voltage. The cascaded multi level inverter fed induction motor is simulated and compared the total harmonic distroction for all level (five-level, seven-level, nine-level and elevel-level)of the inverter. Theoretical investigations were confirmed by the digital simulations using MATLAB/SIMULINK software.
This paper presents new modified space vector pulse width modulation techniques (Phase disposition-Space vector pulse width modulation, Alternative Phase Opposition disposition- Space vector pulse width modulation and Phase Opposition disposition-Space vector pulse width modulation) are analyzed for three-phase cascaded multi-level inverter fed induction motor from the point of view of the Phase voltages, line voltage, stator current,speed,torque and Total harmonic distortion.in the proposed modified technique the reference signals are generated by adding offset voltage to the reference phase voltages.This modified SVPWM technique does not involve region indentification,sector identification for switching vector determination as are required in the conventional multi level SVPWM technique,it is also reduces the computation time compared to the conventional space vector PWM technique.The necessary calculations for generation of new modified SVPWM for the modulation strategies have presented in detail. It is observed that the modified SVPWM modulation ensures excellent, close to optimized pulse distribution results and THD is compared to for five-level, seven-level, nine-level and eleven-level Cascaded H-Bride Multi-level Inverter fed to Induction motor. Theoretical investigations were confirmed by the digital simulations using MATLAB/SIMULINK software.
Ieee Power Electronics Ieee Project Titles, 2009 2010 Ncct Final Year Projectsncct
Final Year Projects, IEEE Projects, Final Year Projects in Chennai, Final Year IEEE Projects, final year projects, college projects, student projects, java projects, asp.net projects, software projects, software ieee projects, ieee 2009 projects, 2009 ieee projects, embedded projects, final year software projects, final year embedded projects, ieee embedded projects, matlab projects, microcontroller projects, vlsi projects, dsp projects, free projects, project review, project report, project presentation, free source code, free project report, Final Year Projects, IEEE Projects, Final Year Projects in Chennai, Final Year IEEE Projects, final year projects, college projects, student projects, java projects, asp.net projects, software projects, software ieee projects, ieee 2009 projects, 2009 ieee projects, embedded projects, final year software projects, final year embedded projects, ieee embedded projects, matlab projects
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
A Three-to-Five-Phase Matrix Converter BasedFive- Phase Induction Motor Drive...idescitation
This paper presents a five-phase induction motor drive
system fed from a three-to-five-phase matrix converter. This
is a new concept of generating variable voltage and variable
frequency five-phase output using a special matrix converter.
This matrix converter is proposed recently which transform
the available three-phase supply to five-phase supply. Simple
carrier-based PWM scheme with enhanced approach is
employed to control the output of the matrix converter.
Enhanced approach is utilized so as to increase the output
voltage magnitude of the three-to-five-phase matrix converter.
The motor is controlled in constant v/f mode. Simulation study
is carried out for excitation, acceleration, loadingand reversing
transients. High quality dynamics are observed.
Voltage profile enhancement in distribution network using static synchronous ...IJECEIAES
STATCOM is one of FACTS devices that used as regulator for transmission and distribution systems which works for reactive power compensation. STATCOM utilisation in distribution system mostly for enhancing the profile of voltage, where used for adjusting the disturbance voltage by injecting into the system a controllable voltage. This paper present a Fuzzy controller based on STATCOM to enhance the voltage profile in distribution network. The controller of STATCOM has simulated for different types of abnormal load conditions of balance and unbalance load. The results of simulation show ability of proposed design to enhance the load voltage which was 96% of the nominal value.
In present days of electrical industries, adjustable speed controlled induction
motor drives are very common due to its versatile features. For the speed control of induction
motor, variable frequency sources are the heart of such drives. To attain variable frequency
and variable voltage supply a power electronics device; single phase matrix converter is
proposed.
In this paper, the single phase matrix converter is modeled in MATLAB Simulink
environment; controlled with sinusoidal pulse width modulation technique, control scheme is
implemented in a Xilinx system generator environment and interfaced with power circuit in
MATLAB Simulink. Analyses this SPMC with different type of loads in both frequency step
up and step down modes. Based on simulation results, this converter is suitable for variable
frequency power supplies, varying load conditions and variable speed electrical drives.
FPGA control is best suitable for controlling a circuit like SPMC, consists of more
controlled elements to attain fast operation.
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
The papers for publication in The International Journal of Engineering& Science are selected through rigorous peer reviews to ensure originality, timeliness, relevance, and readability.
Direct Torque Control of Induction Motor Drive Fed from a Photovoltaic Multil...IJERA Editor
This paper presents Direct Torque Control (DTC) using Space Vector Modulation (SVM) for an induction motor drive fed from a photovoltaic multilevel inverter (PV-MLI). The system consists of two main parts PV DC power supply (PVDC) and MLI. The PVDC is used to generate DC isolated sources with certain ratios suitable for the adopted MLI. Beside the hardware system, the control system which uses the torque and speed estimation to control the load angle and to obtain the appropriate flux vector trajectory from which the voltage vector is directly derived based on direct torque control methods. The voltage vector is then generated by a hybrid multilevel inverter by employing space vector modulation (SVM). The inverter high quality output voltage which leads to a high quality IM performances. Besides, the MLI switching losses is very low due to most of the power cell switches are operating at nearly fundamental frequency. Some selected simulation results are presented for system validation.
In analyzing the problems in South Sulawesi transmission system, simulations of PSCAD / EMTDC [5-6] and PWS (Power World Simulator) [7] software were used to simulate changes in electrical current and voltage during a disturbance.
-Single phase to Ground,
-Line to Fault Line,
-Double Line to Ground
-Three phase Short Circuit
The traction inverter is a crucial power device in the electric vehicle’s powertrain, and its failure is intolerable as it would considerably compromise the system’s safety. For more reliable driving, installing a traction inverter that is sufficiently resistant to electrical failure is inherent. Due to its compact size and the small number of switches incorporated in three-phase four-switch inverter, this modular topology was used to compensate for the open switch’s failure. However, it is known to have manifold weaknesses mainly distinguished in the low-frequency region. This paper introduces a new fault-tolerant indirect control that handles the IGBT’s failure constituting the traction inverter. The fault compensator is designed first based on the Proportional Integral regulator combined with the notch filter to mitigate the current imbalance and restore the DC voltage equilibrium.Furthermore, to conceive a comprehensive fault-tolerant control, there must therefore contain an accurate fault detector. In this regard, an uncomplicated fault diagnosis method based on the current spectral analysis has been performed. The effectiveness of the submitted controller was validated by simulation using Matlab.
Power System Simulation Laboratory Manual Santhosh Kumar
Date:-(13-07-2016)
Hii friends
I Have Attached Our Power System Simulation Laboratory Manual Here for your Reference
Kindly download the Manual and Start Writing the Observation Note By Mr.G.Shivaraj-AP/EEE
Please follow it friends✌
With Happy,
Šαηтн๑zzζzz
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
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International Journal of Computational Engineering Research(IJCER)ijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
Design & Simulation Of 3-Phase, 15-Level Inverter with Reverse Voltage TopologyIJERA Editor
Multilevel inverters have been widely accepted for high-power high-voltage applications. Their performance is highly superior to that of conventional Seven-level inverters due to reduced harmonic distortion, lower electromagnetic interference, and higher dc link voltages. In this paper, a new topology with a reversing-voltage component is proposed to improve the multilevel performance. This topology requires fewer components compared to existing inverters (particularly in higher levels) and requires fewer carrier signals and gate drives. Therefore, thecomplexity is greatly reduced particularly for higher output voltage levels. The Proposed 15-level inverter is modelled and simulated in Matlab 2012a using Simulink and Sim Power Systems set tool boxes
Simulation of 3-phase matrix converter using space vector modulationIJECEIAES
This paper illustrates the simulation of 3-phase matrix converter using Space Vector Modulation (SVM). Variable AC output voltage engendered using matrix converter with bidirectional power switches controlled by appropriate switching pulse. The conventional PWM converter engenders switching common mode voltage across the load system terminals, which cause to common mode current and its leads to bearing failure in load drive. These problems can be rectified using SVM and which minimize the effect on the harmonic fluctuation in AC output voltage and stress on the power switch is reduced using bidirectional switch for proposed 3-phase matrix converter. The simulation results have been presented to validate the proposed system using matlab / simulink.
The power electronics device which converts DC power to AC power at required output voltage and frequency level is known as inverter. Multilevel inverter is to synthesize a near sinusoidal voltage from several levels of dc voltages. In order to maintain the different voltage levels at appropriate intervals, the conduction time intervals of MOSFETS have been maintained by controlling the pulse width of gating pulses. In this paper single phase to three phase power conversion using PWM technique. The simulation is carried out in MATLAB/Simulink environment which demonstrate the feasibility of proposed scheme.
COMPREHENSIVE ANALYSIS AND SIMULATION OF MULTILEVEL POWER CONVERTERS TO CURTA...ecij
Present day industrial applications require higher power apparatus for power conversion. At medium voltage grid, to connect only one power semiconductor switch directly is a not practically successful concept. To overcome this multilevel power converter structure has been introduced and studied as an alternative in high power and medium voltage applications. Renewable energy sources like photovoltaic, wind, fuel cells can be conveniently interfaced to a multilevel converter system for high power applications. In this study it is discussed in detail for different levels of the multilevel converters using pulse width
modulation technique (PWM) the harmonics contents decreases gradually. The simulated results are presented and compared thereafter. Total harmonic distortion decreases as the number of levels increased are tabulated accordingly. All the simulation results are carried out under MATLAB/Simulink environment.
COMPREHENSIVE ANALYSIS AND SIMULATION OF MULTILEVEL POWER CONVERTERS TO CURTA...ecij
Present day industrial applications require higher power apparatus for power conversion. At medium
voltage grid, to connect only one power semiconductor switch directly is a not practically successful
concept. To overcome this multilevel power converter structure has been introduced and studied as an
alternative in high power and medium voltage applications. Renewable energy sources like photovoltaic,
wind, fuel cells can be conveniently interfaced to a multilevel converter system for high power applications.
In this study it is discussed in detail for different levels of the multilevel converters using pulse width
modulation technique (PWM) the harmonics contents decreases gradually. The simulated results are
presented and compared thereafter. Total harmonic distortion decreases as the number of levels increased
are tabulated accordingly. All the simulation results are carried out under MATLAB/Simulink environment.
Multilevel inverters (MLI) are becoming more popular over the years for medium and high power applications because of its significant merits over two level inverters. This paper presents an implementation of multicarrier based sinusoidal pulse width modulation technique for three phase seven level diode clamped multilevel inverter. This topology is operated under phase opposition disposition pulse width modulation technique. The performance of three phase seven level diode clamped inverter is analyzed for induction motor (IM) load. Simulation is performed using MATLAB/SIMULINK. Experimental results are presented to validate the effectiveness of the operation of the diode clamped multilevel inverter using field programmable gate array.
Harmonics Reduction of Multilevel Inverter Drive Using Sine Carrier Pulse Wid...IJERA Editor
The main objective of this paper is to control the speed of an induction motor by using seven level diode clamped multilevel inverter and improve the high quality sinusoidal output voltage with reduced harmonics. The presented scheme for diode clamped multilevel inverter is sine carrier Pulse Width Modulation control. An open loop speed control can be achieved by using V/ƒ method. This method can be implemented by changing the supply voltage and frequency applied to the three phase induction motor at constant ratio. The presented system is an effective replacement for the conventional method which has high switching losses, its result ends in a poor drive performance. The simulation result portrays the effective control in the motor speed and an enhanced drive performance through reduction in total harmonic distortion (THD). The effectiveness of the system is verified through simulation using PSIM6.1 Simulink package
Comparative performance of modular with cascaded H-bridge three level invertersIJECEIAES
The conventional two-level inverter becomes no longer has the ability to cope with the high-power requirement, so this paper discusses two very common topologies of multilevel inverter like modular multilevel converter (MMC) and cascaded H-bridge (CHB) multilevel inverter for induction motor drive applications. This work attempts to investigate the comparison between MMC and CHB. The comparison is done in aspects of the configuration, concept of operation, advantages and disadvantages, the comparison is also considering output voltage (line to line) waveform, total harmonic distortion (THD) of the output line voltage waveform and the current drawn by both inverters. The performance of the inverters under carrier-based pulse width modulation (PWM) technique and mainly in-phase disposition (IPD), level shifted pulse width modulation is viewed. The paper discusses the comparison between the two multilevel inverters (MLIs) with motor drive applications especially induction motor. The operation of the motor is studied under certain value of load torque. The simulation results for the induction motor with the two inverters (modular multilevel and Cascaded H-bride) for three numbers of levels using MATLAB/Simulink are provided). The obtained results are encouraging and promising especially in the improvement of the THD% results.
Report On diode clamp three level inverterVinay Singh
three level diode clamp inverter. that converts any type of DC ( rectified, PV cell, battery etc.) to AC supply. we made by mosfet and ardiuno . in this ppt we present the Simulink model of a three-level inverter and the hardware reort of the inverter.
also discuss about other level inverter and there THD analysis, simulink model and detail. compression between another inverter.
Power Quality Improvement Using Cascaded H-Bridge Multilevel Inverter Based D...IJERA Editor
Cascaded multilevel configuration of the inverter has the advantage of its simplicity and modularity over the
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conditioning to improve power quality in the distribution network. The DSTATCOM helps to improve the
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Load (NLDRL). The compensation process is based on concept of p-q theory. A CHB Inverter is considered for
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PWM (PSPWM) techniques are adopted to investigate the performance of CHB Inverter. The results are
obtained through Matlab/Simulink software package.
Analysis of 7-Level Cascaded & MLDCLI with Sinusoidal PWM & Modified Referenc...IJMTST Journal
Multilevel inverter offers several advantages compare to the conventional three phase bridge inverter in terms of lower dv/dt stresses, lower electromagnetic compatibility and better THD features. The primary use of DC to AC conversion & speed control of machines also voltage controller and reduce the harmonics in the levels of inverter by using cascade multilevel inverter. This paper presents a comparison of cascaded and multilevel dc link inverter (MLDCLI) Using only a DC power source and capacitors. A MLDCLI can be constructed by the series connection half and full bridge cells each having its own DC source .A multilevel voltage source inverter can be formed by connecting an MLDCL with a single bridge inverter. The MLDCL provides a DC voltage with the shape of a staircase with or without pulse width modulation (PWM) to the bridge inverter, which in turn alternates the polarity to produce an AC voltage. compared with the cascaded multilevel inverter, The MLDCLI can significantly reduce the switch count as the number of voltage levels increases beyond five for a given number of voltage levels , m , the required number of active switches is 2(m -1) for the existing multilevel inverter but is m+3 for the MLDCL inverters.
This paper presents the performance of a seven level cascaded multilevel inverter &MLDCLI Based on a sinusoidalPWM and modified Reference PWM control techniques. Performance analysis is made based on the results of simulation study conducted on the operation of the cascaded & MLDCLI using MATLAB/SIMULINK. The performance parameters chosen in the work include the waveform pattern harmonic spectrum, fundamental value & total harmonic distortion (THD) of the three phase cascaded H-Bridge MLI & MLDCLI.
Comparative Study of Fuzzy Logic Based Speed Control of Multilevel Inverter f...IJPEDS-IAES
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FIDO Alliance Osaka Seminar: Passkeys and the Road Ahead.pdf
Ai34212218
1. Jayant M. Parkhi, R.K.Dhatrak / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 4, Jul-Aug 2013, pp.212-218
212 | P a g e
Reduction Of Common Mode Voltage In Ac Drives Using
Multilevel Inverter
Jayant M. Parkhi1
, R.K.Dhatrak2
1,2
(Department of Electronics and Power Engg, R.C.E.R.T., Chandrapur
Abstract
In this paper, an approach to reduce
common-mode voltage (CMV) at the output of
multilevel inverters using a phase opposition
disposed (POD) sinusoidal pulse width
modulation (SPWM) technique is proposed. The
SPWM technique does not require computations
therefore, this technique is easy to implement on-
line in digital controllers. A good tradeoff
between the quality of the output voltage and the
magnitude of the CMV is achieved in this paper.
This paper realizes the implementation of a POD-
SPWM technique to reduce CMV using a five-
level diode clamped inverter for a three phase
induction motor. Experimental and simulation
results demonstrate the feasibility of the proposed
technique.
I. INTRODUCTION
Energy saving has never been more
important than it is today. In industrialized countries,
about 70% of all of the generated electric energy is
used by electrical motors. In addition, more than
60% of all the electric energy converted into
mechanical energy is consumed by pump and fan
drives with induction motors. This fact points out the
importance of energy savings in these types of
drives. High power pumps and fans need medium-
voltage (MV) Drives. At this rating, MV machine
designs offer significant cost savings and
improvements in the thermal performance of their
power components. The switching devices are
connected in series to raise the blocking capacity in
conventional two-level MV inverters. The
simultaneous switching of series connected fast
devices generates voltage with a high dv=dt at the
output terminal of the inverter. The combination of a
short rise time of the inverter output voltage and a
long cable are potentially hazardous for the motor
insulation and the cable itself. The phenomenon,
which is worsened with a shorter rise time, appears
on motors as a leakage current. In motor drive
applications, this may lead to electromagnetic
interference noise that causes a nuisance trip of the
inverter drive, problems with the protection scheme
of the supply transformer and interference with other
electronic equipment in the vicinity [1]. In addition,
a conventional two-level inverter based drive faces
problems with the CMV. The CMV is responsible
for the shaft voltage and the premature
failure of the bearings [2]. It is very important to
reduce CMV itself or to limit this voltage to within
certain bounds. Some approaches have been
presented to cope with the CMV issue include four
leg inverters, passive filters, passive elements with
active circuitry and dual bridge inverters [3]–[6].
A multilevel inverter can reduce as well as eliminate
the CMV. Multilevel inverters have a high number
of switching states so that the output voltage is
stepped in smaller increments. This allows
mitigation of the harmonics at low switching
frequencies thereby reducing switching losses.
Further, the leakage current is reduced because of
the lower dv=dt. The H-bridge multilevel inverter
presented in literature has been implemented
successfully in industrial applications for high power
drives. However, the drawback is that these inverters
need a large number of dc sources or isolation
transformers on the ac side. The diode
clamped multilevel structure is more suitable for
high and medium voltage drives which are directly
connected to the utility power system (direct to drive
topology). This topology requires only one ac power
supply (with a front end active converter and an
inverter at the drive end) therefore; it is very
attractive for industrial adjustable speed drives
(ASD). The CMV reduction technique is well
discussed in many papers using a higher level
cascaded H Bridge multilevel inverter and a three-
level diode (neutral) clamped inverter.
The application of a five-level diode
clamped inverter to reduce common mode voltage
using POD-PWM has not been reported in literature.
Fig. 1. Five-level diode clamped inverter and
induction motor.
2. Jayant M. Parkhi, R.K.Dhatrak / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 4, Jul-Aug 2013, pp.212-218
213 | P a g e
Fig. 2. Three-phase VSI inverter and induction
motor.
Recently, several methods to implement
SVM for multilevel converters have been presented.
These techniques have been successfully used to
reduce as well as cancel the CMV. In [7], a five-
level inverter is used to eliminate CMV but the
levels of the phase voltages of the star connected
load are reduced from five to three and the
magnitude of the line voltage transition increases.
The same source also reported that the trade
off between the magnitude of the CMV and the
switching states gives rise to lower order harmonics
in the phase voltage. In this paper CMV reduction is
proposed using the POD SPWM technique. A five
level diode clamped multilevel inverter is fabricated
for a three-phase, 3 hp, 400 V induction motor (Fig.
1). Sinusoidal PD-SPWM and PODSPWM
techniques are implemented using a Texas
Instruments DSP TMS320F2812. For a switching
frequency of 1050 Hz and a modulating index, ma
=0:9; simulation and experimental results are
provided to validate the implement of the five-level
diode clamped inverter.
II. COMMON-MODE VOLTAGE
CMV is defined as the voltage at the star
point of the load and the system ground. The
magnitude of the CMV depends on grounding
system. In this paper, CMV is defined with respect
to the dc midpoint (Vcom in Fig. 2) because this
definition of CMV consists of the well defined edges
that are responsible for common mode current.
Since the VSI cannot provide purely sinusoidal
voltages and has discrete output voltages synthesized
from the fixed dc bus voltage Vdc, the CMV is
always different from zero and
Fig. 3. Reference voltages carrier waveforms and
CMV when SPWM applied to two-level inverter.
Fig. 4. Output of inverters. (a) Voltage waveform
and (b) THD.
may take the values of _Vdc=6 or _Vdc=2,
depending on the inverter switch states selected.
During the switch state changes,
the CMV changes by _Vdc=3, regardless of the
changing states. The CMV transitions are shown in
Fig. 3. The change in CMV from -Vdc=2 to -Vdc=6
constitutes step of Vdc=3. When the level changes
from -Vdc=6 to Vdc=6, the change is
again Vdc=3.
III. FIVE-LEVEL DIODE CLAMPED
INVERTER
The multilevel inverters have become a
research hotspot in high-voltage and high-power
applications because of their many merits. With the
trade off between complexity of implementation and
improved performance, multilevel inverters are
usually chosen to be between three-level to nine-
level [8]. The PWM output voltages of two-, three-,
four- and five level inverter are shown in Fig. 4 (a).
Fig. 4 (b) shows the THD in the output voltages of
these inverters with the SPWM technique for a
modulating index of 0.1 to 1.0. The THD in the
output voltage of a multilevel inverter decreases as
the levels (N) of the output voltage increase.
Medium and high power drives designed
for conventional two-level topologies use six
switching devices in each pole as shown in Fig. 5(a)
[9]. This configuration can be converted into a four-
level inverter by simply adding clamping diodes as
shown in Fig. 5(b) which reduces voltage
equalization circuit as well as the dv=dt of inverter
3. Jayant M. Parkhi, R.K.Dhatrak / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 4, Jul-Aug 2013, pp.212-218
214 | P a g e
output voltage. The output voltage of a four-level
inverter is shown in Fig. 4 (a). From Eq. (1), the
CMV is one third of the summation of the
instantaneous voltages in a three phase system. From
Eq. (1), the CMV is one third of the summation of
the instantaneous voltages in a three phase system. A
N-level inverter produces a N-level output voltage
and a three phase system has N3 voltage
combinations. A two-level inverter has eight voltage
combinations without zero common mode voltage
[7]. A four level inverter has 64 combinations of
three-phase voltage without zero common mode
voltage. A five-level inverter has 125 combinations
of three-phase voltage. Out of these 125
combinations, only 19 combinations can generate
zero CMV. In a four-level three phase inverter, the
summation of the instantaneous voltages has a
definite value other than zero. Therefore a four-level
inverter is unable to eliminate the CMV because
zero CMV exists only in multilevel inverters with an
odd number of levels. If the circuit is modified to a
three-level diode clamped, eight switching devices
(two additional) are required in each pole of the
inverter (Fig. 5 (c)). Three-level inverters can be
fabricated using four devices but in medium voltage
drives to achieve the required output voltages of 3.4
kV and 4.16 kV, which means a dc-link voltage
above 6.0 kV, the use of three-level technology with
existing device ratings is not sufficient, therefore,
internal series connection is necessary [10]. A five-
level inverter can also be configured using eight
switching devices in each pole as shown in Fig. 5(d).
This configuration gives the advantages of a low
dv=dt, a low harmonics magnitude and a high
quality output at a low switching frequency.
The drawback of the additional requirement of a
clamping diodes can be justified by eliminating the
equalization circuit, the lower magnitude of the
harmonics at a low switching frequency, less THD at
a low switching frequency, low switching losses, a
low dv=dt, a reduced or zero CMV and a smaller
size sine filter, dv=dt filter and/or CMV filter. This
topology is also suitable for retrofitting. In this
paper, a five-level diode clamped multilevel inverter
is explored to reduce CMV.
IV. PROPOSED SYSTEM
APOD TYPE
Discrete,
Ts = 5e-005 s.
powergui
In1
+V
D1
D2
D3
PA
part3
In1
+V
D1
D2
D3
PA
part2
In1
+V
D1
D2
D3
PA
part1
pulses
controller
A
B
C
A
B
C
Three-Phase
Parallel RLC Branch
Scope1
Scope
In1
PA
D1
D2
D3
-V
Part1-3
In1
PA
D1
D2
D3
-V
Part1-2
In1
PA
D1
D2
D3
-V
Part1-1
G33
G3
G22
G2
G1
G11
G3
G33
G22
G2
G11
G1
DC3
DC2
DC1
DC
D331
D33
D321
D32
D311
D31
D231
D23
D221
D22
D211
D21
D131
D13
D121
D12
D111
D11
v
+
-
C2
v
+
-
C1
<signal1>
<signal2>
<signal3>
<signal4>
<signal5><signal5>
<signal6>
Fig 5.a. Five level diode clamped inverter with
resistive load
The diode clamped inverter also known as
neutral clamped inverter. The diode clamped
inverter delivers the staircase output voltage using
several levels of DC voltages developed by DC
capacitors. If m is the number of level, then the
number of capacitors required on the DC bus are
(m-1), the number of power electronic switches per
phase are 2(m- 1) and the number of diodes per
phase are 2(m-2). This design formula is most
common for all the diode clamped multilevel
inverters. The DC bus voltage is split into three
levels using two capacitors C1 and C2, for five
levels using four capacitors C1, C2, C3 and C4 are
shown in Fig . 1 and Fig .2. The voltage across each
capacitor is Vdc/4 and the voltage stress across each
switch is limited to one capacitor voltage through
clamping diodes. The switching sequences of three
phase 3-level and 5-level diode clamped multilevel
inverter are shown in table. I and II. As the number
of levels increase the harmonic distortion decreases
and efficiency of the inverter increases because of
the reduced switching losses. The number of levels
in multilevel inverters is limited because of the
large number of clamping diodes required. The
reverse recovery of these diodes is especially with
multicarrier PWM techniques in a high voltage
application is a major design challenge.
Multicarrier PWM techniques involves the
natural sampling of single modulating reference
waveform typically being sinusoidal, through several
carrier signals typically being triangular waveforms
This modulation method is the logical extension of
sine-triangle PWM for multilevel inverters, in which
(m-1) carriers are needed for m-level inverter. They
are arranged in vertical shifts in continuous bands
defined by the levels of the inverter. Each carrier has
the same frequency and amplitude. A single voltage
reference is compared to the carrier arrangement and
the generated pulses are associated to each switching
devices.
4. Jayant M. Parkhi, R.K.Dhatrak / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 4, Jul-Aug 2013, pp.212-218
215 | P a g e
5.1. Phase Disposition (PD)
This technique involves a number of
carriers (m-l) which are all in phase accordingly.
In 5 -level inverter all the four carrier waves are
in phase with each other and compared with
reference signal. According to that, the gate
pulses are generated and are associated to each
switching devices. The phase disposition PWM
technique is illustrated in Fig. 5.1
5.2. Phase Opposition Disposition (POD)
This technique employs a number of
carriers (m-1) which are all in phase above and
below the zero reference. In 5-level converters all
the four carrier waves are phase shifted by 180
degrees between the ones above and below zero
reference. The reference signal is compared with
all four carrier waves there by gate pulses are
generated and are associated to each switching
devices. The phase opposition disposition PWM
technique is illustrated in Fig.5.2.
5.3. Alternative Phase opposition Disposition
(APOD)
This technique requires number of
carriers (m-1) which are all phase displaced from
each other by 180 degrees alternatively. The
alternative phase opposition disposition PWM
technique is illustrated in Fig. 5.3
Fig.5.3. Alternative phase opposition disposition.
V. CMV REDUCTION BY POD-
SPWM
In this section the POD SPWM technique is
discussed to reduce common mode voltage. The
multilevel carrier based PWM for a N-level inverter
uses a set of N-1 adjacent level triangular carrier
waves with the same peak-to-peak amplitude and
frequency. Each carrier wave has a distinct dc bias
level such that the disposition of all of the
waveforms together fit the vertical span of the
modulating signal and none of them overlaps each
other. As shown in Fig. 9, four carriers are used for a
five-level inverter. The modulating/reference
waveform is compared with the carrier waveforms
and the switching patterns are generated using (2).
The minimum step size of the CMV is Vdc/(3(N-1))
with the SPWM technique.
In PD-SPWM, the CMV is reduced in the
step of Vdc/12 at the crossing of each reference
wave with the rising edge of the carrier signal as
shown in Fig. 9. The CMV changes in three steps
(maximum) and has four (maximum) distinct CMV
levels in a half period of Ts during the rising edge of
the carrier waveform. Similarly, the CMV is
increased in the step
Fig. 8. Three dimensional phasor representation of
fundamental and harmonics voltage in three-phase
system. (a) PD-SPWM. (b) POD-SPWM.
Fig.5.1. Phase disposition PWM technique
Fig.5.2. Phase opposition disposition PWM
technique
5. Jayant M. Parkhi, R.K.Dhatrak / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 4, Jul-Aug 2013, pp.212-218
216 | P a g e
Fig. 9. Reference phase voltages, carrier waveforms
and CMV when PD-SPWM is applied switching to
five-level inverter.
Fig. 10. Reference phase voltages, carrier
waveforms and CMV when POD-SPWM is applied
to five-level inverter.
of Vdc/12 while crossing the reference wave with
the falling edge of the carrier signal. The maximum
CMV can be -Vdc/6 at the positive peak of the
carrier wave and +Vdc/6 at the negative peak. In a
five-level inverter, the maximum CMV with the PD-
SPWM technique is observed to be _Vdc/6. It is
possible to limit the magnitude of the CMV to
_Vdc/12 with POD-SPWM.
In POD-SPWM, in the first half of the
carrier wave, the carrier waves have a positive slope
(rising edge) above the reference axis where as
below the reference axis the carrier waves have a
negative slope (falling edge). Similarly, in the
second half of the carrier wave, the carrier waves
have a falling edge above the reference axis and a
rising edge below the reference axis. In a three-
phase system, there are three reference signals;
therefore, three crossings with the carrier signals are
expected in every half cycle of the carrier wave.
In each half cycle of the carrier wave, there are
either two crossings above the reference axis and
one crossing below the reference axis or one
crossing above the reference axis and two crossings
below the reference axis. The CMV is reduced in the
step of Vdc/12 at the crossing of each reference
wave with the rising edge of the carrier signal above
the reference axis as shown in Fig. 10 and it is
reduced in the step of Vdc/12 at the crossing of each
reference wave with the falling edge of the carrier
signal below the reference axis. In PD-SPWM, the
CMV increases in same direction (positive or
negative) at the crossing of the reference wave with
the carrier signal in each half cycle of a carrier
period. Whereas, in PODSPWM, the CMV has two
transitions in one direction and one transition in the
other. The CMV varies within the band of (_2Vdc/6)
_ (Vdc/6) in POD-SPWM as shown in Fig. 10.
The POD-SPWM technique is implemented
for a five-level inverter.
Fig. 11. CMV with two-level inverter: (a)
Simulation results. (b) Experimental results. Scale:
200V/div, 5ms/div.
Fig. 12. CMV with five-level inverter: simulation
result (a) PD-SPWM technique (b) APOD-SPWM
technique (c) POD-SPWM technique. Scale:
200V/div, 5ms/div.
VI. SIMULATION AND
XPERIMENTAL RESULTS
Simulation results using MATLAB are
provided in this section to verify the concepts and
experimental results are provided to confirm the
value of the proposed algorithms. A three phase
6. Jayant M. Parkhi, R.K.Dhatrak / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 4, Jul-Aug 2013, pp.212-218
217 | P a g e
five-level diode clamped multilevel inverter is
fabricated in the laboratory for a three-phase, 400V,
50Hz, 3 hp, star/delta induction motor. The output
voltage of each rectifier is 162.5 V. This inverter is
controlled by the SPWM technique for ma = 0.9, mf
= 21 at 50 Hz using asymmetrical sampling. A DSP
TMS320F2812 is used as a controller and it has a 32
bit fix point, 150 MHz processor which performs
150 MIPs. A LeCroyWaveRunner 6030 digital
storage oscilloscope (DSO) is used for
measurements and analysis. Initially the five-level
inverter is operated as a two-level inverter by
switching all of the upper switches simultaneously to
get a +Vdc/2 voltage at the output terminal and all of
the lower four switches are turned on simultaneously
to get –Vdc/2
TABLE I
COMPARISION OF THD IN POLE VOLTAGE,
LINE VOLTAGE AND CMV
at the output. Multilevel inverters have an inherent
ability to reduce common mode voltage. Fig. 11
shows the CMV developed within an induction
motor when connected to a five level diode clamped
inverter. The inverter is controlled by the PD-SPWM
technique with a carrier frequency of 1050 Hz and a
modulating index of 0.9. In comparison, the
experimental results with a two-level inverter, from
Fig. 12, show a significant reduction in the
magnitude of CMV and have good agreement with
the simulation results. The maximum magnitude of
the CMV is found to be within the band of _Vdc/6
as presented in Fig. 12 (a) using the PD-SPWM
technique. It changes with a step of Vdc/12. The PD-
SPWM technique cannot further reduce the CMV
because its switching states are not controllable. The
magnitude of the CMV (maximum) is reduced to
_Vdc/12 using the APOD-SPWM (Fig. 12.(b)) and
POD-SPWM (Fig.12.(c)) techniques. It changes with
a step of Vdc/12. However, the THD in the line
voltage is higher with the APOD-SPWM technique.
Comparisons of the THD in the pole voltage and the
line voltage, and the CMV are given in Table I.
Fig. 13 shows the experimental result with the PD-
SPWM and POD-SPWM techniques. This is
implemented in software without adding any
hardware. With the PD-SPWM technique, the CMV
changes a maximum of six times with a maximum of
seven segments and four discrete levels with two
zero voltage levels during a carrier period. The
POD-SPWM technique reduces the nonzero CMV
levels and increases the zero CMV levels in a carrier
period.
VII. CONCLUSION
A conventional two-level inverter generates
CMV which is responsible for a leakage current and
the premature failure of motor bearings. A multilevel
inverter has the inherent ability to reduce CMV.
Simulation and experimental results prove that the
PD-SPWM technique reduces the magnitude of
CMV to Vdc/6 and that it has a minimum THD in
the line voltage and current. The POD-SPWM
technique further reduces the magnitude of CMV to
Vdc/12 at the cost of an increase in the THD in the
line voltage and current. A multilevel inverter
reduces the dv/dt in its output voltage and therefore
the leakage current is also reduced.
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Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 4, Jul-Aug 2013, pp.212-218
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