Sofics

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Design of ESD protection for high-speed interfaces
 
Local I/O ESD protection for 28Gbps to 112Gbps SerDes interfaces in advanced CMOS and FinFET technology
 
Optimization of On-chip ESD protection with ultra-low parasitic capacitance through Calibre PEX
 
Developing robust, 5V tolerant analog I/O libraries for CMOS processes & FinFET technologies to 16nm
 
Optimizing I/O’s and ESD protection to reduce power consumption in SOI applications
 
IoT workshop - Is 1kV Also Enough for IoT ESD Protection – Do Current Test Methods and Models Apply?
 
Introduction to TakeCharge on-chip ESD solutions from Sofics
 
SCR based On-chip ESD protection for LNA