The document describes a proposed 9T SRAM cell design with the following key features:
1. It uses a combination of a standard inverter and a single-ended Schmitt trigger inverter to provide high read stability.
2. Transmission gates are used instead of single-pass gates to reduce unnecessary switching during hold mode.
3. A negative assist technique alters the trip voltage of the Schmitt trigger inverter to improve write-1 ability.
4. Multi-threshold CMOS techniques are adopted to reduce leakage power in the proposed 9T SRAM cell.
Simulation results show the proposed cell has better performance than previous 7T, 10T, 11T, ST 9T
A Novel Low Power Energy Efficient SRAM Cell With Reduced Power Consumption u...iosrjce
In modern high performance integrated circuits, maximum of the total active mode energy is
consumed due to leakage current. SRAM cell array is main source of leakage current since majority of
transistor are utilized for on-chip memory in today high performance microprocessor and system on chip
designs. Therefore the design of low leakage SRAM is required. Reducing power dissipation, supply voltage,
leakage currents, area of chip are the most important parameters in today`s VLSI designs. But scaling of these
parameters will lead to drastic increase in sub threshold leakage currents and power dissipation because of that
performance of the design is degraded. So to overcome these issues it is better to concentrate on reduction of
active leakage currents and dynamic power dissipation by using power reduction techniques. In this paper 9T
SRAM (data retention p-gated) cell for low voltage and energy constrain application is analyzed with respect to
power dissipation, area and delay. The analyzed design of 9T SRAM cell with MTCMOS technique has been
proposed. Designed circuits are simulated in Microwind 3.1 VLSI CAD Tool in 90 and 65nm CMOS technology.
This paper presents a spin-transfer torque- magnetic
tunnel junction (STT-MTJ) based non-volatile 9-transistor
(9T) SRAM cell. The cell achieves low power dissipation due
to its series connected MTJ elements and read buffer which
offer stacking effect. The paper studies the impact of PVT
(process, voltage, and temperature) variations on the design
metric of the SRAM cell such as write delay and compares the
results with non-volatile 8T SRAM cell (NV8T). The proposed
design consumes lower leakage power and exhibits narrower
spread in write delay compared with NV8T.
Energy optimization of 6T SRAM cell using low-voltage and high-performance in...IJECEIAES
The performance of the cell deteriorates, when static random access memory (SRAM) cell is operated below 1V supply voltage with continuous scale down of the complementary metal oxide semiconductor (CMOS) technology. The conventional 6T, 8T-SRAM cells suffer writeability and read static noise margins (SNM) at low-voltages leads to degradation of cell stability. To improve the cell stability and reduce the dynamic power dissipation at low- voltages of the SRAM cell, we proposed four SRAM cells based on inverter structures with less energy consumption using voltage divider bias current sink/source inverter and NOR/NAND gate using a pseudo-nMOS inverter. The design and implementation of SRAM cell using proposed inverter structures are compared with standard 6T, 8T and ST-11T SRAM cells for different supply voltages at 22-nm CMOS technology exhibit better performance of the cell. The read/write static noise margin of the cell significantly increases due to voltage divider bias network built with larger cell-ratio during read path. The load capacitance of the cell is reduced with minimized switching transitions of the devices during high-to-low and low- to-high of the pull-up and pull-down networks from VDD to ground leads to on an average 54% of dynamic power consumption. When compared with the existing ones, the read/write power of the proposed cells is reduced to 30%. The static power gets reduced by 24% due to stacking of transistors takes place in the proposed SRAM cells as compare to existing ones. The layout of the proposed cells is drawn at a 45-nm technology, and occupies an area of 1.5 times greater and 1.8 times greater as compared with 6T-SRAM cell.
Analysis of CMOS and MTCMOS Circuits Using 250 Nano Meter Technology csandit
The low-power consumption with less delay time has become an important issue in the recent
trends of VLSI. In these days, the low power systems with high speed are highly preferable
everywhere. Designers need to understand how low-power techniques affect performance
attributes, and have to choose a set of techniques that are consistent with these attributes .The
main objective of this paper is to describe, how to achieve low power consumption with
approximately same delay time in a single circuit. In this paper, we make circuits with CMOS
and MTCMOS techniques and check out its power and delay characteristics. The circuits
designed using MTCMOS technique gives least power consumption.
All the pre-layout simulations have been performed at 250nm technology on tanner EDA tool.
Design & Implementation of Subthreshold Memory Cell design based on the prima...IOSRJVSP
As there is a demand for portable electronic systems or devices, there is an incremental growth in the technology in the past few decades and also technology is cumulative at a random rate, devices are consuming large amount of power due to this the life of the battery is draining fast. so there must be a alternative devices or circuits which can reduce the power by efficiently maintaining the area and performance, therefore life of battery can be increased. As SRAM is the heart of block in all the electronic design, where the power consumption is maximum there by analyzing, estimating & modifying or changing the logic, will be able to reduce the power and performance can be greatly achieved. This proposal describes under the principle of ultra-low power logic approach which operates under subthreshold voltage operating which leads to lower power and also efficient in functionality along with secondary constraints.
STUDY OF SPIN TRANSFER TORQUE (STT) AND SPIN ORBIT TORQUE (SOT) MAGNETIC TUNN...elelijjournal
Magnetic Random Access Memory (MRAM) is a promising candidate to be the universal non-volatile (NV) storage device. The Magnetic Tunnel Junction (MTJ) is the cornerstone of the NV-MRAM technology. 2- terminal MTJ based on Spin Transfer Torque (STT) switching is considered as a hot topic for academic and industrial researchers. Moreover, the 3-terminal Spin Orbit Torque (SOT) MTJ has recently been considered as a hopeful device which provides an increased reliability thanks to independent write and read paths. Since both MTJ devices (STT and SOT) seem to revolutionize the data storage market, it is necessary to explore their compatibility with very advanced CMOS processes in terms of transistor sizing and performance. Assuming a good maturity of the magnetic processes that would enable to fabricate small junctions, simulation results show that the existing advanced sub-micronic CMOS processes can drive the required writing current with reasonable size of transistors confirming the high density feature of MRAMs. At 28 nm node, the minimum transistor size can be used by the STT device. The SOT device shows remarkable energy efficiency with 6× improvement compared with the STT technology. Results are very encouraging for future complex hybrid magnetic/CMOS integrated circuits (ICs).
The International Journal of Engineering and Science (The IJES)theijes
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
A Novel Low Power Energy Efficient SRAM Cell With Reduced Power Consumption u...iosrjce
In modern high performance integrated circuits, maximum of the total active mode energy is
consumed due to leakage current. SRAM cell array is main source of leakage current since majority of
transistor are utilized for on-chip memory in today high performance microprocessor and system on chip
designs. Therefore the design of low leakage SRAM is required. Reducing power dissipation, supply voltage,
leakage currents, area of chip are the most important parameters in today`s VLSI designs. But scaling of these
parameters will lead to drastic increase in sub threshold leakage currents and power dissipation because of that
performance of the design is degraded. So to overcome these issues it is better to concentrate on reduction of
active leakage currents and dynamic power dissipation by using power reduction techniques. In this paper 9T
SRAM (data retention p-gated) cell for low voltage and energy constrain application is analyzed with respect to
power dissipation, area and delay. The analyzed design of 9T SRAM cell with MTCMOS technique has been
proposed. Designed circuits are simulated in Microwind 3.1 VLSI CAD Tool in 90 and 65nm CMOS technology.
This paper presents a spin-transfer torque- magnetic
tunnel junction (STT-MTJ) based non-volatile 9-transistor
(9T) SRAM cell. The cell achieves low power dissipation due
to its series connected MTJ elements and read buffer which
offer stacking effect. The paper studies the impact of PVT
(process, voltage, and temperature) variations on the design
metric of the SRAM cell such as write delay and compares the
results with non-volatile 8T SRAM cell (NV8T). The proposed
design consumes lower leakage power and exhibits narrower
spread in write delay compared with NV8T.
Energy optimization of 6T SRAM cell using low-voltage and high-performance in...IJECEIAES
The performance of the cell deteriorates, when static random access memory (SRAM) cell is operated below 1V supply voltage with continuous scale down of the complementary metal oxide semiconductor (CMOS) technology. The conventional 6T, 8T-SRAM cells suffer writeability and read static noise margins (SNM) at low-voltages leads to degradation of cell stability. To improve the cell stability and reduce the dynamic power dissipation at low- voltages of the SRAM cell, we proposed four SRAM cells based on inverter structures with less energy consumption using voltage divider bias current sink/source inverter and NOR/NAND gate using a pseudo-nMOS inverter. The design and implementation of SRAM cell using proposed inverter structures are compared with standard 6T, 8T and ST-11T SRAM cells for different supply voltages at 22-nm CMOS technology exhibit better performance of the cell. The read/write static noise margin of the cell significantly increases due to voltage divider bias network built with larger cell-ratio during read path. The load capacitance of the cell is reduced with minimized switching transitions of the devices during high-to-low and low- to-high of the pull-up and pull-down networks from VDD to ground leads to on an average 54% of dynamic power consumption. When compared with the existing ones, the read/write power of the proposed cells is reduced to 30%. The static power gets reduced by 24% due to stacking of transistors takes place in the proposed SRAM cells as compare to existing ones. The layout of the proposed cells is drawn at a 45-nm technology, and occupies an area of 1.5 times greater and 1.8 times greater as compared with 6T-SRAM cell.
Analysis of CMOS and MTCMOS Circuits Using 250 Nano Meter Technology csandit
The low-power consumption with less delay time has become an important issue in the recent
trends of VLSI. In these days, the low power systems with high speed are highly preferable
everywhere. Designers need to understand how low-power techniques affect performance
attributes, and have to choose a set of techniques that are consistent with these attributes .The
main objective of this paper is to describe, how to achieve low power consumption with
approximately same delay time in a single circuit. In this paper, we make circuits with CMOS
and MTCMOS techniques and check out its power and delay characteristics. The circuits
designed using MTCMOS technique gives least power consumption.
All the pre-layout simulations have been performed at 250nm technology on tanner EDA tool.
Design & Implementation of Subthreshold Memory Cell design based on the prima...IOSRJVSP
As there is a demand for portable electronic systems or devices, there is an incremental growth in the technology in the past few decades and also technology is cumulative at a random rate, devices are consuming large amount of power due to this the life of the battery is draining fast. so there must be a alternative devices or circuits which can reduce the power by efficiently maintaining the area and performance, therefore life of battery can be increased. As SRAM is the heart of block in all the electronic design, where the power consumption is maximum there by analyzing, estimating & modifying or changing the logic, will be able to reduce the power and performance can be greatly achieved. This proposal describes under the principle of ultra-low power logic approach which operates under subthreshold voltage operating which leads to lower power and also efficient in functionality along with secondary constraints.
STUDY OF SPIN TRANSFER TORQUE (STT) AND SPIN ORBIT TORQUE (SOT) MAGNETIC TUNN...elelijjournal
Magnetic Random Access Memory (MRAM) is a promising candidate to be the universal non-volatile (NV) storage device. The Magnetic Tunnel Junction (MTJ) is the cornerstone of the NV-MRAM technology. 2- terminal MTJ based on Spin Transfer Torque (STT) switching is considered as a hot topic for academic and industrial researchers. Moreover, the 3-terminal Spin Orbit Torque (SOT) MTJ has recently been considered as a hopeful device which provides an increased reliability thanks to independent write and read paths. Since both MTJ devices (STT and SOT) seem to revolutionize the data storage market, it is necessary to explore their compatibility with very advanced CMOS processes in terms of transistor sizing and performance. Assuming a good maturity of the magnetic processes that would enable to fabricate small junctions, simulation results show that the existing advanced sub-micronic CMOS processes can drive the required writing current with reasonable size of transistors confirming the high density feature of MRAMs. At 28 nm node, the minimum transistor size can be used by the STT device. The SOT device shows remarkable energy efficiency with 6× improvement compared with the STT technology. Results are very encouraging for future complex hybrid magnetic/CMOS integrated circuits (ICs).
The International Journal of Engineering and Science (The IJES)theijes
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Design of STT-RAM cell in 45nm hybrid CMOS/MTJ processEditor IJCATR
This paper evaluates the performance of Spin-Torque Transfer Random Access Memory (STT-RAM) basic memory cell
configurations in 45nm hybrid CMOS/MTJ process. Switching speed and current drawn by the cells have been calculated and
compared. Cell design has been done using cadence tools. The results obtained show good agreement with theoretical results.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
A Simulation Based Analysis of Lowering Dynamic Power in a CMOS Inverteridescitation
With the increase in demand of high fidelity
portable devices, there is more and more emphasis laying
down on the development of low power and high performance
systems. In the next generation processors, the low power
design has to be incorporated into fundamental computation
units, such as adder. CMOS circuit design plays a crucial role
in designing of these computation units (like adder and
multiplier) so if there is any optimal way to reduce the power
dissipation in CMOS circuits then it will directly lower down
the power dissipation of other circuits and logic gates as well.
In this paper we have studied and analyzed different
techniques to reduce the dynamic power of CMOS circuit
with the help of performing simulation on some significant
factors (i.e device characteristics) of respective circuitry
designs by using Cadence-Virtuoso tool.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Design and Simulation Low power SRAM Circuitsijsrd.com
SRAMs), focusing on optimizing delay and power. As the scaling trends in the speed and power of SRAMs with size and technology and find that the SRAM delay scales as the logarithm of its size as long as the interconnect delay is negligible. Non-scaling of threshold mismatches with process scaling, causes the signal swings in the bitlines and data lines also not to scale, leading to an increase in the relative delay of an SRAM, across technology generations. Appropriate methods for reduction of power consumption were studied such as capacitance reduction, very low operating voltages, DC and AC current reduction and suppression of leakage currents to name a few.. Many of reviewed techniques are applicable to other applications such as ASICs, DSPs, etc. Battery and solar-cell operation requires an operating voltage environment in low voltage area. These conditions demand new design approaches and more sophisticated concepts to retain high device reliability. The proposed techniques (USRS and LPRS) are topology based and hence easier to implement.
SPIN TORQUE TRANSFER MRAM AS A UNIVERSAL MEMORYIJERA Editor
The current multi-core era has resulted in the integration of increasing numbers of cores into the
microprocessors used to power computers and cell phones. Spin-Transfer Torque RAM (STT-RAM) is an
emerging non-volatile memory technology with the potential to be used as universal memory. STT MRAM with
read and write current is discusses here . In addition to that application of STT MRAM as a cache design is also
discussed.
Investigation of TTMC-SVPWM Strategies for Diode Clamped and Cascaded H-bridg...ijeei-iaes
This paper presents a concept of two types multilevel inverters such as diode clamped and cascaded H-bridge for harmonic reduction on high power applications. Normally, multilevel inverters can be used to reduce the harmonic problems in electrical distribution systems. This paer focused on the performance and analysis of a three phase seven level inverter including diode clamped and cascaded H-bridge based on new tripizodal triangular space vector PWM technique approaches. TTMC based modified Space vector Pulse width modulation technique so called tripizodal triangular Space vector Pulse width modulation (TTMC-SVPWM) technique. In this paper the reference sine wave generated as in case of conventional off set injected SVPWM technique. It is observed that the TTMC-Space vector pulse width modulation ensures excellent, close to optimized pulse distribution results and THD is compared to seven level, diode clamped and cascaded multi level inverters. Theoretical investigations were confirmed by the digital simulations using MATLAB/SIMULINK software.
In the project#1, IBM 130nm process is used to design and manual layout a 128 word SRAM, with word size 10bits. Cadence's Virtuoso is applied for layout editing, DRC and LVS running and circuit simulation.
FPGA IMPLEMENTATION OF LOW POWER SRAM BASED PROCESSOR IN 8T USING HETTSEditor IJMTER
In MOSFETs lower limit sub threshold swing (60mv/decade) restricts the low power
operation. Low voltage operation is enabled by low Vth while maintaining performance. Hence steep
sub threshold slopes provide power-efficient operation without any loss of performance. To obtain
sub threshold swings of less than 30mV/decade with large ON current, Si/SiGe heterojunction
tunneling transistor uses gate controlled modulation. To overcome the impact of HETT
characteristics on SRAM, seven transistors HETT based SRAM design is introduced. Compared to
CMOS this new 8T HETT SRAM achieves reduction in leakage power.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
ANALYSIS OF CMOS AND MTCMOS CIRCUITS USING 250 NANO METER TECHNOLOGYcscpconf
The low-power consumption with less delay time has become an important issue in the recent
trends of VLSI. In these days, the low power systems with high speed are highly preferable
everywhere. Designers need to understand how low-power techniques affect performance
attributes, and have to choose a set of techniques that are consistent with these attributes .The
main objective of this paper is to describe, how to achieve low power consumption with
approximately same delay time in a single circuit. In this paper, we make circuits with CMOS
and MTCMOS techniques and check out its power and delay characteristics. The circuits
designed using MTCMOS technique gives least power consumption.
All the pre-layout simulations have been performed at 250nm technology on tanner EDA tool.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Design of STT-RAM cell in 45nm hybrid CMOS/MTJ processEditor IJCATR
This paper evaluates the performance of Spin-Torque Transfer Random Access Memory (STT-RAM) basic memory cell
configurations in 45nm hybrid CMOS/MTJ process. Switching speed and current drawn by the cells have been calculated and
compared. Cell design has been done using cadence tools. The results obtained show good agreement with theoretical results.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
A Simulation Based Analysis of Lowering Dynamic Power in a CMOS Inverteridescitation
With the increase in demand of high fidelity
portable devices, there is more and more emphasis laying
down on the development of low power and high performance
systems. In the next generation processors, the low power
design has to be incorporated into fundamental computation
units, such as adder. CMOS circuit design plays a crucial role
in designing of these computation units (like adder and
multiplier) so if there is any optimal way to reduce the power
dissipation in CMOS circuits then it will directly lower down
the power dissipation of other circuits and logic gates as well.
In this paper we have studied and analyzed different
techniques to reduce the dynamic power of CMOS circuit
with the help of performing simulation on some significant
factors (i.e device characteristics) of respective circuitry
designs by using Cadence-Virtuoso tool.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Design and Simulation Low power SRAM Circuitsijsrd.com
SRAMs), focusing on optimizing delay and power. As the scaling trends in the speed and power of SRAMs with size and technology and find that the SRAM delay scales as the logarithm of its size as long as the interconnect delay is negligible. Non-scaling of threshold mismatches with process scaling, causes the signal swings in the bitlines and data lines also not to scale, leading to an increase in the relative delay of an SRAM, across technology generations. Appropriate methods for reduction of power consumption were studied such as capacitance reduction, very low operating voltages, DC and AC current reduction and suppression of leakage currents to name a few.. Many of reviewed techniques are applicable to other applications such as ASICs, DSPs, etc. Battery and solar-cell operation requires an operating voltage environment in low voltage area. These conditions demand new design approaches and more sophisticated concepts to retain high device reliability. The proposed techniques (USRS and LPRS) are topology based and hence easier to implement.
SPIN TORQUE TRANSFER MRAM AS A UNIVERSAL MEMORYIJERA Editor
The current multi-core era has resulted in the integration of increasing numbers of cores into the
microprocessors used to power computers and cell phones. Spin-Transfer Torque RAM (STT-RAM) is an
emerging non-volatile memory technology with the potential to be used as universal memory. STT MRAM with
read and write current is discusses here . In addition to that application of STT MRAM as a cache design is also
discussed.
Investigation of TTMC-SVPWM Strategies for Diode Clamped and Cascaded H-bridg...ijeei-iaes
This paper presents a concept of two types multilevel inverters such as diode clamped and cascaded H-bridge for harmonic reduction on high power applications. Normally, multilevel inverters can be used to reduce the harmonic problems in electrical distribution systems. This paer focused on the performance and analysis of a three phase seven level inverter including diode clamped and cascaded H-bridge based on new tripizodal triangular space vector PWM technique approaches. TTMC based modified Space vector Pulse width modulation technique so called tripizodal triangular Space vector Pulse width modulation (TTMC-SVPWM) technique. In this paper the reference sine wave generated as in case of conventional off set injected SVPWM technique. It is observed that the TTMC-Space vector pulse width modulation ensures excellent, close to optimized pulse distribution results and THD is compared to seven level, diode clamped and cascaded multi level inverters. Theoretical investigations were confirmed by the digital simulations using MATLAB/SIMULINK software.
In the project#1, IBM 130nm process is used to design and manual layout a 128 word SRAM, with word size 10bits. Cadence's Virtuoso is applied for layout editing, DRC and LVS running and circuit simulation.
FPGA IMPLEMENTATION OF LOW POWER SRAM BASED PROCESSOR IN 8T USING HETTSEditor IJMTER
In MOSFETs lower limit sub threshold swing (60mv/decade) restricts the low power
operation. Low voltage operation is enabled by low Vth while maintaining performance. Hence steep
sub threshold slopes provide power-efficient operation without any loss of performance. To obtain
sub threshold swings of less than 30mV/decade with large ON current, Si/SiGe heterojunction
tunneling transistor uses gate controlled modulation. To overcome the impact of HETT
characteristics on SRAM, seven transistors HETT based SRAM design is introduced. Compared to
CMOS this new 8T HETT SRAM achieves reduction in leakage power.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
ANALYSIS OF CMOS AND MTCMOS CIRCUITS USING 250 NANO METER TECHNOLOGYcscpconf
The low-power consumption with less delay time has become an important issue in the recent
trends of VLSI. In these days, the low power systems with high speed are highly preferable
everywhere. Designers need to understand how low-power techniques affect performance
attributes, and have to choose a set of techniques that are consistent with these attributes .The
main objective of this paper is to describe, how to achieve low power consumption with
approximately same delay time in a single circuit. In this paper, we make circuits with CMOS
and MTCMOS techniques and check out its power and delay characteristics. The circuits
designed using MTCMOS technique gives least power consumption.
All the pre-layout simulations have been performed at 250nm technology on tanner EDA tool.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Sub-Threshold Leakage Current Reduction Techniques In VLSI Circuits -A SurveyIJERA Editor
There is an increasing demand for portable devices powered up by battery, this led the manufacturers of
semiconductor technology to scale down the feature size which results in reduction in threshold voltage and
enables the complex functionality on a single chip. By scaling down the feature size the dynamic power
dissipation has no effect but the static power dissipation has become equal or more than that of Dynamic power
dissipation. So in recent CMOS technologies static power dissipation i.e. power dissipation due to leakage
current has become a challenging area for VLSI chip designers. In order to prolong the battery life and maintain
reliability of circuit, leakage current reduction is the primary goal. A basic overview of techniques used for
reduction of sub-threshold leakages is discussed in this paper. Based on the surveyed techniques, one would be
able to choose required and apt leakage reduction technique.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Average and Static Power Analysis of a 6T and 7T SRAM Bit-Cell at 180nm, 90nm...idescitation
A lot of consideration has been given to problems arising due to power dissipation.
Different ideas have been proposed by many researchers from the device level to the
architectural level and above. However, there is no universal way to avoid tradeoffs between
the power, delay and area. This is why; the designers are required to choose appropriate
techniques that satisfy application and product needs. Another important component of
power which contributes to power dissipation is Dynamic Power. This power is increasing
due to prolonged use of the electronic equipments. This is due to the fact that now-a-days
people are working on electronic systems from morning till night; it may be a mobile phone
or a laptop or any other equipment. This paper deals with the estimation of two components
of power i.e. static power (when device is in the standby mode) and the average power
(average amount of energy consumed with respect to time) of a 6T and 7T SRAM (Static
Random Access Memory) bit-cell at 180nm, 90nm, and 45nm CMOS Technology. This is
done in order to estimate the power required for a high speed operation of 6T and 7T
SRAM bit-cell.
Implementation of an Efficient SRAM for Ultra-Low Voltage Application Based o...IOSR Journals
Abstract: Operation of standard 6T static random access memory (SRAM) cells at sub or near threshold
voltages is unfeasible, predominantly due to degraded static noise margins (SNM) and poor robustness. We
analyze Schmitt-Trigger (ST)-based differential-sensing static random access memory (SRAM) bitcells for
ultralow-voltage operation. The ST-based SRAM bitcells address the fundamental conflicting design
requirement of the read versus write operation of a conventional 6T bitcell. The ST operation gives better readstability
as well as better write-ability compared to the standard 6T bitcell. In this paper we are going to
propose a new SRAM bitcell for the purpose of read stability and write ability by using 90nm technology , and
less power consumption, less area than the existing Schmitt trigger1 based SRAM. Design and simulations were done using DSCH and Microwind.
Index Terms: read stability, write ability, Schmitt trigger.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
DESIGN AND MODELLING OF DIFFERENT SRAM’S BASED ON CNTFET 32NM TECHNOLOGYVLSICS Design
Carbon nanotube field-effect transistor (CNTFET) refers to a field-effect transistor that utilizes a single carbon nanotube or an array of carbon nanotubes as the channel material instead of bulk silicon in the traditional MOSFET structure. Since it was first demonstrated in 1998, there have been tremendous developments in CNTFETs, which promise for an alternative material to replace silicon in future electronics. Carbon nanotubes are promising materials for the nano-scale electron devices such as nanotube FETs for ultra-high density integrated circuits and quantum-effect devices for novel intelligent circuits, which are expected to bring a breakthrough in the present silicon technology. A Static Random Access Memory (SRAM) is designed to plug two needs: i) The SRAM provides as cache memory, communicating between central processing unit and Dynamic Random Access Memory (DRAM). ii) The SRAM technology act as driving force for low power application since SRAM is portable compared to DRAM, and SRAM doesn’t require any refresh current. On the basis of acquired knowledge, we present
different SRAM's designed for the conventional CNTFET. HSPICE simulations of this circuit using Stanford CNTFET model shows a great improvement in power saving.
Vaccine management system project report documentation..pdfKamal Acharya
The Division of Vaccine and Immunization is facing increasing difficulty monitoring vaccines and other commodities distribution once they have been distributed from the national stores. With the introduction of new vaccines, more challenges have been anticipated with this additions posing serious threat to the already over strained vaccine supply chain system in Kenya.
Final project report on grocery store management system..pdfKamal Acharya
In today’s fast-changing business environment, it’s extremely important to be able to respond to client needs in the most effective and timely manner. If your customers wish to see your business online and have instant access to your products or services.
Online Grocery Store is an e-commerce website, which retails various grocery products. This project allows viewing various products available enables registered users to purchase desired products instantly using Paytm, UPI payment processor (Instant Pay) and also can place order by using Cash on Delivery (Pay Later) option. This project provides an easy access to Administrators and Managers to view orders placed using Pay Later and Instant Pay options.
In order to develop an e-commerce website, a number of Technologies must be studied and understood. These include multi-tiered architecture, server and client-side scripting techniques, implementation technologies, programming language (such as PHP, HTML, CSS, JavaScript) and MySQL relational databases. This is a project with the objective to develop a basic website where a consumer is provided with a shopping cart website and also to know about the technologies used to develop such a website.
This document will discuss each of the underlying technologies to create and implement an e- commerce website.
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptxR&R Consult
CFD analysis is incredibly effective at solving mysteries and improving the performance of complex systems!
Here's a great example: At a large natural gas-fired power plant, where they use waste heat to generate steam and energy, they were puzzled that their boiler wasn't producing as much steam as expected.
R&R and Tetra Engineering Group Inc. were asked to solve the issue with reduced steam production.
An inspection had shown that a significant amount of hot flue gas was bypassing the boiler tubes, where the heat was supposed to be transferred.
R&R Consult conducted a CFD analysis, which revealed that 6.3% of the flue gas was bypassing the boiler tubes without transferring heat. The analysis also showed that the flue gas was instead being directed along the sides of the boiler and between the modules that were supposed to capture the heat. This was the cause of the reduced performance.
Based on our results, Tetra Engineering installed covering plates to reduce the bypass flow. This improved the boiler's performance and increased electricity production.
It is always satisfying when we can help solve complex challenges like this. Do your systems also need a check-up or optimization? Give us a call!
Work done in cooperation with James Malloy and David Moelling from Tetra Engineering.
More examples of our work https://www.r-r-consult.dk/en/cases-en/
Courier management system project report.pdfKamal Acharya
It is now-a-days very important for the people to send or receive articles like imported furniture, electronic items, gifts, business goods and the like. People depend vastly on different transport systems which mostly use the manual way of receiving and delivering the articles. There is no way to track the articles till they are received and there is no way to let the customer know what happened in transit, once he booked some articles. In such a situation, we need a system which completely computerizes the cargo activities including time to time tracking of the articles sent. This need is fulfilled by Courier Management System software which is online software for the cargo management people that enables them to receive the goods from a source and send them to a required destination and track their status from time to time.
Automobile Management System Project Report.pdfKamal Acharya
The proposed project is developed to manage the automobile in the automobile dealer company. The main module in this project is login, automobile management, customer management, sales, complaints and reports. The first module is the login. The automobile showroom owner should login to the project for usage. The username and password are verified and if it is correct, next form opens. If the username and password are not correct, it shows the error message.
When a customer search for a automobile, if the automobile is available, they will be taken to a page that shows the details of the automobile including automobile name, automobile ID, quantity, price etc. “Automobile Management System” is useful for maintaining automobiles, customers effectively and hence helps for establishing good relation between customer and automobile organization. It contains various customized modules for effectively maintaining automobiles and stock information accurately and safely.
When the automobile is sold to the customer, stock will be reduced automatically. When a new purchase is made, stock will be increased automatically. While selecting automobiles for sale, the proposed software will automatically check for total number of available stock of that particular item, if the total stock of that particular item is less than 5, software will notify the user to purchase the particular item.
Also when the user tries to sale items which are not in stock, the system will prompt the user that the stock is not enough. Customers of this system can search for a automobile; can purchase a automobile easily by selecting fast. On the other hand the stock of automobiles can be maintained perfectly by the automobile shop manager overcoming the drawbacks of existing system.
Water scarcity is the lack of fresh water resources to meet the standard water demand. There are two type of water scarcity. One is physical. The other is economic water scarcity.
Cosmetic shop management system project report.pdfKamal Acharya
Buying new cosmetic products is difficult. It can even be scary for those who have sensitive skin and are prone to skin trouble. The information needed to alleviate this problem is on the back of each product, but it's thought to interpret those ingredient lists unless you have a background in chemistry.
Instead of buying and hoping for the best, we can use data science to help us predict which products may be good fits for us. It includes various function programs to do the above mentioned tasks.
Data file handling has been effectively used in the program.
The automated cosmetic shop management system should deal with the automation of general workflow and administration process of the shop. The main processes of the system focus on customer's request where the system is able to search the most appropriate products and deliver it to the customers. It should help the employees to quickly identify the list of cosmetic product that have reached the minimum quantity and also keep a track of expired date for each cosmetic product. It should help the employees to find the rack number in which the product is placed.It is also Faster and more efficient way.
Welcome to WIPAC Monthly the magazine brought to you by the LinkedIn Group Water Industry Process Automation & Control.
In this month's edition, along with this month's industry news to celebrate the 13 years since the group was created we have articles including
A case study of the used of Advanced Process Control at the Wastewater Treatment works at Lleida in Spain
A look back on an article on smart wastewater networks in order to see how the industry has measured up in the interim around the adoption of Digital Transformation in the Water Industry.
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About
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Technical Specifications
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
Key Features
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface
• Compatible with MAFI CCR system
• Copatiable with IDM8000 CCR
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
Application
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
1. This work is licensed under a Creative Commons Attribution 4.0 International License,
which permits unrestricted use, distribution, and reproduction in any medium, provided
the original work is properly cited.
ech
T Press
Science
Computers, Materials & Continua
DOI: 10.32604/cmc.2022.023934
Article
Design of Low Power Transmission Gate Based 9T SRAM Cell
S. Rooban1
, Moru Leela1
, Md. Zia Ur Rahman1,*, N. Subbulakshmi2
and R. Manimegalai3
1
Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram,
Guntur, Andhra Pradesh, 522502, India
2
Department of Electronics and Communication Engineering, Francis Xavier Engineering College, Tirunelveli,
Tamil Nadu, 627003, India
3
Department of Computer Science and Engineering, PSG Institute of Technology and Applied Research, Coimbatore,
Tamil Nadu, 641062, India
*Corresponding Author: Md. Zia Ur Rahman. Email: mdzr55@gmail.com
Received: 27 September 2021; Accepted: 30 December 2021
Abstract: Considerable research has considered the design of low-power and
high-speed devices. Designing integrated circuits with low-power consump-
tion is an important issue due to the rapid growth of high-speed devices.
Embedded static random-access memory (SRAM) units are necessary com-
ponents in fast mobile computing. Traditional SRAM cells are more energy-
consuming and with lower performances. The major constraints in SRAM
cells are their reliability and low power. The objectives of the proposed
method are to provide a high read stability, low energy consumption, and bet-
ter writing abilities. A transmission gate-based multi-threshold single-ended
Schmitt trigger (ST) 9T SRAM cell in a bit-interleaving structure without a
write-back scheme is proposed. Herein, an ST inverter with a single bit-line
design is used to attain the high read stability. A negative assist technique is
applied to alter the trip voltage of the single-ended ST inverter. The multi-
threshold complementary metal oxide semiconductor (MTCMOS) technique
is adopted to reduce the leakage power in the proposed single-ended TG-
ST 9T SRAM cell. The proposed system uses a combination of standard
and ST inverters, which results in a large read stability. Compared with the
previous ST 9T, ST 11T, 11T, 10T, and 7T SRAM cells, the proposed cell is
implemented in Cadence Virtuoso ADE with 45-nm CMOS technology and
consumes 35.80%, 42.09%, 31.60%, 12.54%, and 31.60% less energy for read
operations and 73.59%, 93.95%, 92.76%, 89.23%, and 85.78% less energy for
write operations, respectively.
Keywords: Bit-interleaving; low power; SRAM cell; schmitt trigger;
transmission gate
1 Introduction
As technology evolves each day, the important design constraints for transistor scaling are the
speed and integrated density, while leakages and reliability issues degrade the overall device perfor-
mances. Further scaling results in short-channel effects, and overcoming this effect has led to several
2. 1310 CMC, 2022, vol.72, no.1
leakage power reduction techniques in existing designs [1]. Electronic devices, like microprocessors and
microcontrollers, require high performances based on low power and high speeds. Such devices may
be packed compactly and handled easily but require a memory cell with a low power consumption
[2,3]. A memory cell is a fundamental block in computer memory, and most digital devices are made
using SRAM [4,5]. The high operating speed capability of SRAM makes it widely used over dynamic
random-access memory (DRAM), even though SRAM designs are comparatively more complex. The
SRAM memory cell is a flip-flop circuit and is typically implemented using metal oxide field-effect
transistors (MOSFETs). SRAM plays an important role in the System on Chip (SoC) as it is the
primary element in chip design. SRAM has a larger value of switched capacitance in the bit line (BL)
and word line (WL), which requires a higher energy cost. Thus, reducing the power consumption
on SRAM reduces the power consumption of SoC devices [6]. A MOSFET has three regions of
operations: i) sub-threshold, ii) near-threshold, and iii) super threshold. In the sub-threshold region,
the gate-to-source voltage is not as high as the edge voltage of a MOSFET, so this region is also called
the cut-off region where the effects of current on the gate voltage are exponential. Conduction in the
cut-off region is denoted as sub-threshold conduction, where there are more leakages even though the
power consumption is low [7,8]. In the super threshold region, the gate-to-source voltage is greater
than the MOSFET threshold voltage and is called the saturation region as there is no effect on the
current with a greater drain voltage [9].
In the near-threshold voltage (NTV) region, the voltage of the gate-source is greater than the
threshold voltage (Vth) of the MOSFET. Here, the current increases with the voltage at the drain
terminal, and the current leakage is low compared to sub-threshold operations [10,11]. This results
in greater improvements in reducing the power consumption compared to super threshold operations
[12–14]. However, soft errors are induced in the near-threshold operation region due to the effects of
alpha particles [15]. High-energy alpha particles interact with the memory cell and interrupt operations
or even cause damage [16]. SRAM designs can be categorized based on interconnections with the
inverter as i) cross-coupled standard inverter, ii) cross-coupled Schmitt-trigger (ST) inverter, and iii)
cross-coupled ST inverter with a standard inverter. First, various inverters that fall under the cross-
coupled standard inverter category are the conventional 6T [17], 8T [18], Pasandi’s 9T [19], Chang’s
9T [20], Joon’s 10T [21], and 7T [22]. In 10T SRAM, a single BL is used for both read/write to
reduce the power consumption [23], and in 11T, power gating transistors and a transmission gate are
implemented to reduce the power leakage [24]. The read disturbance from BL or bit line bar (BLB)
in the conventional 6T can flip the stored data. In 6T, the read and write stabilities are not achieved
simultaneously because these depend on the beta- and alpha-ratios, respectively. The 7T SRAM cell
is not affected by any RHSc issues and does not have any read disturbances that require low power.
The advantages of cross-coupled ST inverters in SRAM designs over the standard inverter SRAM
designs are i) the cross-coupled structure of the ST inverter with a standard inverter to improve the
read stability, and ii) the ST inverter write assist scheme with selective power gating to improve the write
capability. The ST 10T [25] and ST 11T [26] belong to the cross-coupled ST inverter group. In ST 11T,
the cross-coupled ST inverter is connected with the read buffer, and a single BL structure is used for
read operations, where the read buffer improves the hold and read stabilities. In the cross-coupled ST
inverter with a standard inverter category, the ST 9T [27] has a single BL structure and is designed with
WBSBS. Selective power gating is used to develop the write ability. The ST voltage of the 9T inverter
can be controlled through the write-assist scheme. The MTCMOS method offers a high performance
in low-power designs [28]. Transmission gates reduce the leakage power to a greater extent [29], and the
ST inverter [30] provides a robust security and high read stability while the performance characteristic
of the standard inverter decays for smaller supply voltages (Vdd). Based on several investigations,
3. CMC, 2022, vol.72, no.1 1311
the literature suggests that current designs have problems, such as read/write stability and a reduced
leakage power. To address these issues, the proposed method provides the following contributions.
• Compared to ST 10T, the proposed design has a large read stability as it uses a combination of
standard and ST inverters.
• In place of single-pass gates in the literature, a transmission gate is implemented to reduce
unnecessary switching during the hold mode.
• When a read disturbance reaches the storage node, the ST inverter is more resistant to read
interruptions compared to ideal inverters.
• The proposed method holds column-based assist techniques to reduce the energy consumption.
• The read static noise margin of the proposed cell is high compared to the 10T SRAM and 6T
SRAM cells.
The remainder of this work is organized as follows. Section 2 introduces the proposed TG-ST 9T
SRAM design and its operation. Section 3 analyzes the performance of the proposed design with the
N-curve metric. Section 4 compares the results with the ST 9T SRAM cell based on power and delay,
and Section 5 concludes this article.
2 Proposed TG-ST 9T SRAM
Several SRAM cell designs have been investigated to reduce the power, and significant constraints
have been considered in the memory portion of the chip as the best possible design pathway, as
described in the previous section. This section discusses the proposed SRAM cell design. The schematic
and timing diagrams of the proposed SRAM cell are given in Figs. 1a and 1b. This method adapts the
MTCMOS technique based on a single BL structure, which includes a high Vth with nominal Vth
devices to reduce leakage. The proposed cell has a cross-coupled standard inverter and a single-ended
modified ST inverter with both having high Vth. In place of a single-pass gate in the literature, a
transmission gate (TP and TN) is used with one enable (EN) transistor connected between the two
inverters, which reduces the unnecessary switching activities during hold mode. The TP, TN, and EN
all have a nominal Vth. The word lines (WL and WLB) are row-based signals and the WWL is a
column-based signal. The WL is connected to the TN and EN gates, the WLB is connected to the TP
gate, and the WWL is connected to the source of the feedback transistor (NF).
Figure 1: (a) Schematic and (b) Timing diagrams of the proposed SRAM cell
4. 1312 CMC, 2022, vol.72, no.1
2.1 Proposed Method: Read Operation
The read operation of the proposed cell is depicted in Fig. 2. The BL is pre-charged to VDD
during read operations, the WWL is set to “1,” and the inverter controls node Q. Activating the row-
dependent signals (WL and WLB) allows turning on the transmission gate. If Q has zero charge, the
BL discharges; otherwise, there is no change in the BL. Disturbances caused by the BL during read
operations are the most common cause of read failures. If the storage node is enabled through read
disturbances, then the voltage attains the inverter trip voltage. The proposed design addresses this
problem by combining a regular inverter and an ST inverter into a cross-coupled structure. Figs. 3a
and 3b represent the single-ended modified ST inverter and its DC characteristics, respectively. The
ST inverter has a greater trip voltage than the normal inverter when the input changes from logical
“0” to logical “1.” The voltage at node VX increases with the NF transistor, which reduces the strength
of PDR1 transistor. As a result, when a read disturbance reaches the storage node, the ST inverter is
more resistant to read interruptions compared with an ideal inverter.
Figure 2: Read operations in the proposed ST inverter scheme
Figure 3: (a) Schematic diagram of the ST inverter and (b) Its DC characteristics at VDD = 0.5 V
5. CMC, 2022, vol.72, no.1 1313
2.2 Write-0 Operation
Write operations are conditional on whether the information to be composed on the SRAM cell
is a “1” or “0.” Fig. 4a illustrates the write-0 operation. The column-based signal WWL remains “1”
in the write-0 operation, and the write driver sets BL to “0”, WL to “1,” and WLB to “0.” The Q node
is pushed to “0” through the turned-on transmission gate, and the ST inverter flips. The proposed
SRAM cell cuts off the VDD by disconnecting the pMOS transistor of the standard inverter, which
achieves write-0 capability during the write operations.
Figure 4: Proposed TG-ST 9T static RAM (a) Write-0 and (b) Write-1 operations
2.3 Write-1 Operation
The write-1 process is illustrated in Fig. 4b. During write-1 operations, the write driver pushes the
BL to “1,” the WL is ON, and the WLB is disabled. The proposed cell has a negative VWWL assist
technique to boost its write-1 ability. Once the negative voltage is provided to the WWL, the turned-on
feedback transistor NF drives the Vx node to a negative voltage. As the voltage at Vx decreases, the
power of PDR1 increases and lowers the ST inverter trip voltage. As a result, the write-1 operation
becomes more straightforward.
The amount of change in the trip voltage that corresponds to the increased PDR1 is shown in
Fig. 5. When the column-based WWL signal is held at 0 V, the ST inverter trip voltage decreases by
16.61%. As the feedback function is removed by turning off the feedback transistor NF, the trip voltage
is identical to that of a regular inverter. The trip voltage decrease to 64.85% using the negative assist
technique on the column-based signal from the WWL. Lowering the trip voltage allows the negative
assist technique to boost the write-1 ability.
6. 1314 CMC, 2022, vol.72, no.1
Figure 5: DC characteristics of the negative VWWL given at VDD = 0.5 V
3 Performance Analysis
The stability assessment and evaluation of the N-curve metric is implemented in the 7T, 10T, 11T,
ST 11T, ST 9T, and the proposed TG-ST 9T SRAM cells.
In the N-curve metric, the stability of the SRAM depends on the supply voltage. The SRAM cell
becomes unstable if the supply voltage is reduced. The N-curve is the preferred metric to measure
the stability of the SRAM. Drawing a butterfly/N-curve is a single plot with detailed information
on the stability of the SRAM and write operation. For CR = 10, the stability parameters such as the
static voltage noise margin (SVNM), static current noise margin (SINM), write trip current (WTI),
and write trip voltage (WTV) are observed to provide reasonably better values compared to CR = 9,
8, and 7 in the 45-nm CMOS technology, as summarized in Tab. 1. Fig. 6 shows the N-curve of the
proposed design, where the four N-curve parameters are utilized to characterize the device stability.
Comparisons of the parameters SVNM, SINM, WTI, and WTV for the conventional SRAM cells
(7T, 10T, 11T, ST 11T, ST 9T, and low leakage 10T) with the proposed method are given in Tab. 2.
Table 1: N-curve analysis of the proposed design at various cell ratios
Technology Parameters CR = 10 CR = 9 CR = 8 CR = 7
45-nm CMOS SVNM (mV) 233.27 223.46 213.31 207.95
SINM (uA) 1.73 1.49 1.25 1.01
WTI (uA) −0.729 −0.729 −0.728 −0.719
WTV (mV) 193.05 193.34 193.62 184.64
7. CMC, 2022, vol.72, no.1 1315
Figure 6: N-curve analysis of the proposed design at 0.5 V
Table 2: Comparison of N-curve results of various SRAM cell
SRAM cell 7T SRAM
[22]
10T SRAM
[23]
11T SRAM
[24]
ST 11T
SRAM
[26]
ST 9T
SRAM
[27]
Proposed
design
SVNM (mV) 150 90 246.494 172.873 229.25 233.27
SINM (uA) 0.159 0.1 0.302 0.084 0.205 1.7
WTI (uA) −0.736 −2.399 −0.351 −0.238 −0.169 −0.7
WTV (mV) 260 410 253.5 230 184.47 193.05
4 Simulation Results
The implementation results of the proposed TG ST-9T are compared with other SRAM cells
using 45-nm CMOS technology. Monte Carlo simulations are performed in HSPICE to evaluate the
SRAM cell design. Statistical analysis for the stability is achieved using the noise margin (NM), which
is another key factor in SRAM cells and is an important constraint in their construction.
4.1 Read Delay
The time taken for the response when the input signal is applied to the WL is denoted as the read
delay. Fig. 7 shows the read delay of the proposed design with various supply voltages of 0.40, 0.42,
0.44, 0.46, 0.48, and 0.50 V. A reduction in the delay between the ST 11T and ST 9T is the same as the
reduction between the ST 9T and the proposed design with 0.44 and 0.40 V. Thus, it is perceived and
verified that the design holds the minimum delay over the 7T SRAM.
8. 1316 CMC, 2022, vol.72, no.1
Figure 7: Read delay comparison at various supply voltages
4.2 Write Assist Technique
Various write assist techniques have been proposed and used in several memory cell designs.
Among the available write assist techniques, the suppressed cell VDD [31], raised cell VSS [32], boosted
VWL [33], negative VBL [34], and negative VWWL assist techniques are commonly used in 7T, ST
11T, ST 9T, 11T, and 10T SRAM cells.
4.3 Half-Selected Cell Stability and Write Ability
All selected columns must be controlled in column-based assist techniques, which leads to an
increased energy consumption, whereas only one row is selected and controlled in row-based assist
techniques to attain a low power. Due to the low-energy in row-based support methods, the row-based
boosted VWL is chosen with a boosted WL voltage to ensure the circuit has a 3σ stability. The negative
VWWL for a 3σ write capability of the proposed and ST 9T SRAM cells are shown in Fig. 8, which
indicates the proposed method has better results.
0.40 0.42 0.44 0.46 0.48 0.50
-70
-60
-50
-40
-30
-20
-10
0
Proposed
ST 9T
Supply Voltage (V)
)
V
m
(
e
g
a
t
l
o
V
e
v
i
t
a
g
e
N
Figure 8: Comparison of the 3σ write capabilities for the negative VWWL and ST 9T SRAM cells
Monte Carlo simulations were implemented to estimate the write-0 and write-1 operations for
each SRAM cell. Statistical simulations are performed using the static power loss of the proposed cell
through the Monte Carlo distribution, as shown in Fig. 9. The waveforms for the control terminals
with write-0 and write-1 procedures and the storage node at Vdd = 0.5 V are obtained from 1000
Monte Carlo simulations to verify the required functionality of the circuit.
9. CMC, 2022, vol.72, no.1 1317
Figure 9: Write-0 and write-1 operational waveforms for (a) The control signals, (b) Selected cells in
the storage node, and (c) Column-based cells
4.4 Leakage Power
The leakage power of the proposed SRAM cell is compared with various SRAM cells at v = 0.5 V,
as shown in Fig. 10a. As the ST inverter has a greater trip voltage than standard inverters, the SRAM
cells that use cross-coupled ST inverters have higher hold stability yields than cross-coupled standard
inverter SRAM cells. The leakage power of the proposed design has a maximum of 52.72% greater
than the 7T SRAM cell, 82.16% greater than the 10T SRAM Cell, 77.27% greater than the 11T SRAM
Cell, 50.83% greater than the ST 11T SRAM cell, and 36.72% lower than the ST 9T Cell due to the
MTCMOS in the proposed design.
4.5 Power Consumption
A comparison of the total power consumption for the proposed SRAM cell with traditional cells
is performed and shown in Fig. 10b. The proposed design has 72.18%, 64.98%, 72.28%, 77.76%, and
33.18% smaller power consumptions compared with the 7T, 10T, 11T, ST 11T, and ST 9T SRAM cells,
respectively.
10. 1318 CMC, 2022, vol.72, no.1
Figure 10: (a) Leakage power comparison of various SRAM cells and (b) Total power consumption at
0.5 V
4.6 Comparison at Vdd = 0.5 V
The proposed SRAM cell is implemented and simulated in the Cadence virtuoso environment for
45-nm CMOS technology. An energy-delay product (EDP) is commonly used to consider both the
energy and efficiency. The power supply (Vdd) and EDP will not reflect the delay and energy values.
Thus, these will be considered based on the power supply. Eqs. (1)–(3) show the EDP, static PDP, and
PDP calculations, respectively. Tab. 3 shows simulations of the proposed and previous SRAM Cells at
Vdd.
EDP = Energy ∗ delay (1)
Static PDP = Leakage power ∗ delay (2)
PDP = Total power ∗ delay (3)
Tab. 3 indicates that the proposed Multi-Vt TG-ST 9T SRAM cell consumes a read energy of 50.2
nJ whereas the ST 9T, ST 11T, 11T, 10T, and 7T SRAM cells have read energies of 78.2, 86.7, 73.4,
57.4, and 73.4 nJ, respectively. The write energy of the proposed SRAM cell is 6.47 nJ and the ST 9T,
ST 11T, 11T, 10T, and 7T SRAM consume 24.5, 107, 89.4, 60.1, and 45.5 nJ, respectively. Similarly,
the total energy of the proposed SRAM cell design is 5.39 nJ and those for the ST 9T, ST 11T, 11T,
10T, and 7T SRAM are 24.8, 48.3, 32.1, 25.2, and 32.7 nJ, respectively. Thus, the proposed design has
low read and write energies.
Table 3: Comparison of SRAM approaches for 45-nm CMOS technologies
SRAM cell 7T [22] 10T [23] 11T [24] ST 11T [26] ST 9T [27] Proposed
#BL 1-BL 1-RBL
1-WBL
1-BL 1-BL
1-RBL
1-BL 1-BL
#WL 1-WL
1-WLB
1-WWL
1-WWL
1-RWL
1-WL
1-WLB
1-RWL
1-WWL
1-WL
1-WLB
1-RWL
1-WL
1-WWLA
1-WWLB
1-WL
1-WLB
1-WWL
Supply voltage
(V)
0.5 0.5 0.5 0.5 0.5 0.5
(Continued)
11. CMC, 2022, vol.72, no.1 1319
Table 3: Continued
SRAM cell 7T [22] 10T [23] 11T [24] ST 11T [26] ST 9T [27] Proposed
Read delay (ns) 120 153 122 179 122 69.4
Write ability
yield
3σ 3σ 3σ 3σ 3σ 3σ
Write assist
voltage (row)
0.5 V 0.5 0.5 0.5 V 0.6 V Not
required
Write assist
voltage
(column)
- - - - 0.6 V 0.3 V
Leakage power
(nW)
6.76 2.55 3.25 7.03 22.6 14.3
Static PDP
(f ws)
0.811 0.39 0.396 1.258 2.757 0.992
Total power (W) 55 43.7 55.2 68.8 22.9 15.3
PDP (f ws) 6.6 6.68 6.73 12.31 2.79 1.06
Read energy
(nJ)
73.4 57.4 73.4 86.7 78.2 50.2
Write energy
(nJ)
45.5 60.1 89.4 107 24.5 6.47
Total energy
(nJ)
32.7 25.2 32.1 48.3 24.8 5.39
EDP (f Js) 3.92 3.901 3.916 8.627 3.025 0.374
5 Conclusions
The increased power dissipation is due primarily to the scaling down of the system dimensions,
input voltage, and threshold voltage. The proposed design uses a column-based assist technique to
further reduce the energy consumption. The energy and delay are compared for the 7T SRAM, 10T
SRAM, 11T SRAM, ST 11T SRAM, ST 9T SRAM, and the proposed design. The SRAM cell designs
are simulated with 45-nm CMOS technology for a 0.5 V VDD using the Cadence Virtuoso ADE.
Power reduction techniques such as the MTCMOS technique and transmission gate property allow the
proposed design to reduce the power consumption and operate the SRAM cells faster. In the proposed
method, the ST inverter with a single BL design is used to attain a high read stability. The proposed
multi vt TG-ST improves the write ability yield using the negative VWWL write assist technique, which
does not require a write assist row voltage. The total energy consumption is only 5.39 nJ and is lower
than the ST 9T, ST 11T, and 7T SRAM cells. The proposed multi vt TG-ST 9T SRAM cell design has
87.63%, 95.66%, 90.44%, 90.41%, and 90.45% smaller EDPs than the ST 9T, ST 11T, 11T, 10T, and
7T SRAM cells, respectively, at a supply voltage of 0.5 V.
Funding Statement: The authors received no specific funding for this study.
Conflicts of Interest: The authors declare that they have no conflicts of interest to report regarding the
present study.
12. 1320 CMC, 2022, vol.72, no.1
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