The document discusses transistor-transistor logic (TTL) NAND gates. It begins with an introduction to the topic and outlines what will be covered. It then shows the basic TTL NAND circuit and symbol. The document simulates the circuit in PSpice under different input conditions and discusses the results. It also examines the propagation delay and switching times. In conclusion, it states that TTL NAND gates were discussed and confirms the circuit behaves as expected. It notes additional topics that could be covered if there was more time.

1. Hello instructor and peers, my name is Loren Karl
Schwappach. I am a working towards my BSEE and BSCE at CTU.
Today I am going to speak to you about Transistor Transistor Logic NAND
gates. To get the most from this briefing you will need to have an
understanding of BJTs and basic electronics.
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2. Today I am going to cover the following topics:
 Transistor Transistor Logic (TTL)
 Basic TTL NAND Circuit & Symbol
 PSpice Results for High Inputs
 PSpice Results for Low Inputs
 Simulation Results
If time permits I will also talk to you about:
 Totem Pole Output Stage & Fanout
 TTL Families
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3. This diagram uses two 2N3904 NPN transistors to emulate
the dual-emitter NPN transistor commonly used in TTL NAND gates. I
had to tie transistors Q1a’s and Q1b’s collectors and bases together to
simulate the two-emitter transistor commonly used in TTL gates. Resistor
RB is called a pull resistor and is used to increase transistor Q3’s
switching speed. The symbols for representing NAND gates are
illustrated.
Some of the advantages and disadvantages of TTL (Davis,
2011) include: CMOS is generally smaller and typically requires less
voltage and uses less power than TTL. TTL typically benefits from faster
switching speeds than CMOS. TTL uses bipolar transistors where CMOS
uses MOSFET (metal oxide semiconductor field effect transistor). CMOS
is more sensitive to ESD than TTL.
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4. I had to modify my original TTL circuit inputs into VDC
sources in order to correctly simulate the currents and voltages with both
inputs high. After running a PSpice simulation on the circuit I observed
the following results. First, the two logic highs (5VDC) resulted in a logic
low output (30.55mV) as should a NAND gate. Second, current flowed
from R1 to the base and collector of Q1a and Q1b (working in reverse
active state), the current then proceeded through the base of Q2 and Q3,
saturating both and sending the current to ground and resulting in a low
output.
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5. After modifying both of the inputs to provide 0VDC (logic low)
I observed the following results. First, the two logic lows resulted in a
logic high (5VDC) output. The easiest path to ground was from VCC
through resister R1, through the base of transistors Q1a and Q1b and then
to the inputs. Little current flowed to the base of transistors Q2 and Q3 as
a result, leaving both in cutoff mode and driving an output of 5VDC as a
NAND gate should.
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6. I next used the original TTL circuit with VPulse input sources
with Input A’s frequency at 1kHz (period = 1ms) and Input B’s frequency
at 500Hz (period = 2ms). The results were pleasing and confirmed my TTL
NAND gate circuit was correctly producing the results of a two input
NAND gate.
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7. I next checked the propagation delay and rise/fall times of the
circuit. The results were much better than I expected and showed
approximately: a fall time of 4ns, a high to low propagation delay of 2ns, a
rise time between 50-100ns, and a low to high propagation delay of around
25-50ns. These were in close agreement with TI’s (used to be National
Semiconductor) DM7400 quad two input NAND gate.
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8. Today I talked to you about transistor transistor logic. I
showed the most common TTL NAND gate, I tested a self engineered TTL
NAND circuit in PSpice against all possible inputs and confirmed the use
of TTL for gate creation. If I had additional time I would also introduced
the Totem Pole Output Stage, Fanout, and some popular TTL families.
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9. Does anyone have any questions?
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10. References:
Davis, L. (2011). Logic Threshold Voltage Levels. Retrieved August 16,
2011, from: http://www.interfacebus.com/voltage_threshold.html
DM7400 Specifications. (1989). National Semiconductor. Retrieved August
16, 2011, from:
http://www.datasheetcatalog.org/datasheet/nationalsemiconductor/DS0066
13.PDF
Falstad, P. (2010). TTL NAND Gate Java Demonstration. Retrieved
August 16, 2011, from: http://falstad.com/circuit/e-ttlnand.html
Neamen, D. (2007). Microelectronics: Circuit Analysis and Design (3rd ed.).
New York, NY: McGraw-Hill.
Tokheim, R. (1988). Schaum’s Outline Series: Digital Principles (2nd ed.).
New York, NY: McGraw-Hill.
[Untitled SN7400]. (n.d.). Retrieved August 16, 2011, from:
http://focus.ti.com/graphics/folders/partimages/SN7400.jpg
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11. References Continued:
[Untitled NAND]. (n.d.). Retrieved August 16, 2011, from:
http://www.kpsec.freeuk.com/symbols/nand.gif
[Untitled IEEE NAND]. (n.d.). Retrieved August 16, 2011, from:
http://wiki-images.enotes.com/thumb/d/d8/NAND_IEC.svg/100px-
NAND_IEC.svg.png
[Untitled Question Mark]. (n.d.). Retrieved August 16, 2011, from:
http://healmyptsd.com/wp-content/uploads/2009/09/question-mark3-
misallphoto.jpg
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12. I had to modify my original TTL circuit inputs into VDC
sources in order to correctly simulate the currents and voltages with both
inputs high. After running a PSpice simulation on the circuit I observed
the following results. First, the two logic highs (5VDC) resulted in a logic
low output (30.55mV) as should a NAND gate. Second, current flowed
from R1 to the base and collector of Q1a and Q1b (working in reverse
active state), the current then proceeded through the base of Q2 and Q3,
saturating both and sending the current to ground and resulting in a low
output.
12

13. After modifying both of the inputs to provide 0VDC (logic low)
I observed the following results. First, the two logic lows resulted in a
logic high (5VDC) output. The easiest path to ground was from VCC
through resister R1, through the base of transistors Q1a and Q1b and then
to the inputs. Little current flowed to the base of transistors Q2 and Q3 as
a result, leaving both in cutoff mode and driving an output of 5VDC as a
NAND gate should.
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14. If additional time permits:
You can add another stage to the simple TTL model called a
Totem Pole Output Stage by adding another transistor and diode below
resister RC and above transistor Q3. This is used in most TTL circuits to
improve propagation delay times (Neamen, 2007, p. 1278).
Fanout is another important TTL circuit consideration. The
Fanout number quantifies the maximum amount of similar logic circuits
that can be connected to the output (Neamen, 2007, p. 1279).
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15. TTL logic gates are in the 7400 and 5400 series. The 5400
series is typically used for military technologies due to the temperature
hardiness. TTL families include standard, Low Power, Low Power
Schottky, Schottky, Advanced low-power Schottky, and Advanced
Schottky. The Low Power Schottky is the most commonly used TTL and
the Advanced Schottky has the fastest switching speed and works in the
GHz range (Tokheim, 1988).
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