TTL logic gate characteristics. Theory & operation of TTL NAND gate circuitry. Open collector TTL. Three state output logic. TTL subfamilies. MOS& CMOS logic families. Realization of logic gates in RTL, DTL, ECL, C-MOS & MOSFET.

1. Unit 3
Digital Logic Gate Characteristics

2. Digital Logic Gate Characteristics
• TTL logic gate characteristics.
• Theory & operation of TTL NAND gate
circuitry.
• Open collector TTL.
• Three state output logic.
• TTL subfamilies MOS& CMOS logic families.
• Realization of logic gates in RTL, DTL, ECL, C-
MOS & MOSFET

4. TTL logic gate characteristics
• The Transistor-Transistor Logic (TTL) is a logic
family made up of BJTs (bipolar junction
transistors).
• The designing of TTL logic gates can be done
with resistors and BJTs.

5. Types of Transistor-Transistor Logic
• Standard TTL
• Fast TTL
• Schottky TTL
• High Power TTL
• Low Power TTL
• Advanced Schottky TTL.

9. TTL Family Features
• Logic low level is at 0 or 0.2V.
• Logic high level is at 5V.
• Typical fan out of 10. It means it can support at
most 10 gates at its output.
• A basic TTL device draws a power of almost
10mW, which reduces with the use of Schottky
devices.
• The average propagation delay is about 9ns.
• The noise margin is about 0.4V.

10. TTL Applications
• Used in controller application for providing 0
to 5Vs
• Used as a switching device in driving lamps
and relays
• Used in printers and video display terminals

13. Open collector TTL

14. Open collector TTL
• The main feature is that its output is 0 when
low and floating when high. Usually, an
external Vcc may be applied.

15. Open collector TTL
• Transistor Q1 behaves as a cluster of diodes
placed back to back.
• With any of the input at logic low, the
corresponding emitter-base junction is
forward biased and the voltage drop across
the base of Q1 is around 0.9V, not enough for
the transistors Q2 and Q3 to conduct.
• Thus the output is either floating or Vcc, i.e.
High level.

16. Open collector TTL
• Similarly, when all inputs are high, all base-
emitter junctions of Q1 are reverse biased
and transistor Q2 and Q3 get enough base
current and are in saturation mode.
• The output is at logic low. (For a transistor to
go to saturation, collector current should be
greater than β times the base current).

17. Applications
• The applications of open collector output
include the following.
• In driving lamps or relays
• In performing wired logic
• In the construction of a common bus system

18. Three state output logic

22. TTL subfamilies
1. MOS logic families
2. CMOS logic families

23. 1. MOS logic families

33. Realization of logic gates
• in RTL, DTL, ECL, C-MOS & MOSFET.

34. Realization of logic gates in RTL
• The RTL circuit consists of resistors at inputs
and transistors at the output side. Transistors
are used as the switching device.
• The resistors are the input network while the
transistors function as switching devices.
• The disadvantage of Diode logic (DL) is
overcome using RTL since the transistors not
only operate as switches but also amplify
signals.

35. • The resistors are the input network while the
transistors function as switching devices.
• The disadvantage of Diode logic (DL) is
overcome using RTL since the transistors not
only operate as switches but also amplify
signals.

36. Resistor-Transistor Logic (RTL) NOT
Gate

37. • The resistance R1 is chosen in such a way that
it saturates the transistor and obtains high
input resistance.
• The collector resistor R2 converts collector
current into voltage.
• The resistance of R2 is high to saturate the
transistor and low to obtain output resistance.

38. RTL NOR Gate

39. RTL NOR Gate
• When both A and B are given logic 0, then the
transistor is cut-off. The output is inverted
since it is complimentary.
• This is because the voltage drop across the
collector-emitter junction of the transistor
Q1 is taken at Q instead of taking it across
collector resistor R2.

41. Limitations of RTL
• When the transistor is switched on, the power
dissipation increases as the current flows
through base and collector.
• Also, the RTL gate has poor noise margin, poor
fan-out and the propagation delay is more.

43. DIODE TRANSISTOR LOGIC (DTL)
• Diode transistor logic(DTL) belongs to the
digital logic family.
• This logic circuit has diodes at the input side
and transistor at the output side and so the
name diode transistor logic.
• It has more advantages than resistor
transistor logic(RTL)

44. Logic circuit of 2-input DTL NAND gate

45. DTL NAND GATE
• The following figure shows the circuit for the
2-input DTL NAND gate.
• It consists of two diodes and a transistor.
• The two diodes DA, DB and the resistor R1
form the input side of the logic circuit.
• The common emitter configuration of
transistor Q1 and resistor R2 forms the output
side.

46. • When both the inputs A and B are LOW, the diodes DA
and DB become forward biased and so both diodes will
conduct in the forward direction.
• So the current due to the supply voltage +VCC = 5 V
will go to the ground through R1 and the two diodes
DA and DB.
• The supply voltage gets dropped in the resistor R1 and
it will not be sufficient to turn ON the transistor. So the
transistor will be in cut off mode.
• Therefore, the output at the terminal Y will have HIGH
value, that is Logic 1

47. Advantages
• It has better advantages than RTL Logic. The
Diode Transistor Logic has improved noise
margin, greater fan-out. However, the
propagation delay is more for this device,
when compared to Transistor-transistor
logic(TTL). But the speed is better than RTL.

48. DTL NOR GATE

49. Realization of logic gates ECL
• Emitter-coupled logic is the fastest of all
digital logic families.
• It is also called as current mode logic.
• The design of ECL circuit consists of transistors
and resistors.
• By preventing the transistor from entering into
saturation, the high-speed operation is
achieved in ECL logic family

50. • Emitter-coupled logic family offers an
incredible propagation delay of 1ns

52. Inverter circuit of emitter-coupled
logic
• The circuit shown below represents the
emitter-coupled logic circuit of an inverter.
• It has two NPN transistors connected in
differential single-ended input mode.
• Both the emitters are connected together with
common resistance RE.

53. • It is a current limiting resistance, used to
prevent the transistor from entering into
saturation.
• It has two outputs: inverting output(VOUT1)
and non-inverting output(VOUT12).
• VIN is the input terminal, where LOW or HIGH
input is given.

54. • When the input is HIGH, it will turn ON the
transistor Q1 but not saturated and the
transistor Q2 is turned OFF.
• This will pull the output VOUT2 to HIGH but
due to the drop in resistant R1, the output at
terminal VOUT1 will be at LOW value

55. • On the other side, when the input VIN is given
LOW value, it will turn OFF the transistor Q1
and the transistor is turned ON.
• The transistor Q2 will not enter into
saturation.
• It will make the output at terminal VOUT1 to
be pulled HIGH value.
• Due to the drop in resistance R2, the output at
terminal VOUT2 will have LOW value

56. Two input ECL OR/NOR gate
• the Emitter-coupled logic circuit of the 2-
input OR/NOR gate.
• It is the slight modification of the inverter
circuit given above.
• In this, an additional transistor is used at the
input side.

58. Two input ECL OR/NOR gate
• If the input at both the transistors Q1 and Q2
are LOW, it will make VOUT1 to HIGH value.
• It corresponds to the NOR gate output.
• At the same time, transistor Q3 is turned ON,
which will make the VOUT2 to be HIGH.
• It corresponds to the OR gate output.

59. Two input ECL OR/NOR gate
• if both the input of transistors Q1 and Q2 are
HIGH, it will turn on both the transistors.
• It will drive the output at terminal VOUT1 to
be LOW.
• The transistor Q3 is turned OFF during this
operation.
• It will drive the output at terminal VOUT2 to
be HIGH.

60. truth table for OR/NOR gate

61. Advantages
• High-speed operation is possible and so the
fastest logic family.
• Since transistors are not allowed to enter into
saturation, which reduces the storage delay.
• Fan-out capability is high.