This presentation summarizes the design of a 2-bit arithmetic logic unit (ALU). It includes the group members, an overview of what an ALU is and its methodology. It shows the block diagram and needed integrated circuits. The circuit diagram, truth table, and how it works are described. Advantages like minimum delay and disadvantages like limited output are discussed. Verilog code for the ALU is also included.

1. 2-BIT ALU
Wellcome to our presentation.
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2. Group Members
 MAHMUDULHASAN
 FARHANTANVIR
 RISULislam
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3.  What is 2 bit Alu?
 Methodology
 Block Diagram of 2 bit ALU...
 Introduce Various Kinds of IC
 Circuit Diagram
 How to construct
 Verilog Code part
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OVERVIEW

4. 2-BIT ALU
 An arithmetic logic unit is a multi-operation, combinational logic
function. It can perform a set of basic arithmetic operations and
set of logic operations. The Alu has a number of selection line to
select a particular operation in the unit. The four data inputs from
A are combined with the four inputs from B to generate an
operation at the F. The mode select input M distinguish between
arithmetic and logic operation. The three function select inputs
A,B,C specify particular arithmetic or logic operation to be
granted
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5. Methodology
 An arithmetic logic unite system has been development by sequence of operation.
To active a successful ALU design we use following methodologies:
 Studying literature on different types of bit and their implementation.
 Studying the existing method for ALU arithmetic and logic operation.
 Analyze and design for the proposed System.
 Implement of a desiring design of Arithmatic Logic Unit.
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6. Block Diagram of 2 Bit Alu
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7.  Two Construct 2-bit ALU
 Efficiently use
 Minimize Circuit and Gate
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8. NEED IC FOR CONSTRUCTION
AND GATE(7408)
OR GATE(7432)
EXOR GATE(7432)
NOT GATE(7408)
8-TO-1 MULTIPLEXER(74151)
ADDER(7483)
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9. REAL VIEW OF IC OR PORT NUMBER
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10. NOT GATE
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11. 8-TO-1 MULTIPLEXER(74151)
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12. Logic gate:Adder/substructor:
 Dfsd
 Adder/substructor:
 Full adder truth table. If
mode bit change it work
as a substructor
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13. And|NAND
 And gate and truth table  Nand gate and truth table
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14. OR|NOR
 OR gate and truth Table  Nor gate and truth table
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15. XOR|XNOR
 Xor gate and truth table  Xnor gate and truth
table
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16. Circuit Diagram
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17. TruthTable of the following Circuit
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18. How the Project Work
 In 8*1 multiplexer have 8 input and 1 output. When we select 000 then it select
I(0),when we select 001 then it select I(1).It frequently goes to I(7).when one gate
will select other gate cant work. so we can get 8 operation by frequently change
A,B,C value.
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19. Hardware Implimentation
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20. Advantage
 2 bit ALU has minimum delay time to implimentation
 Minimize the logic Gate
 Less expensive due to use minimum gate
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21. Disadvantage
 Complex circuit Diagram
 Output only 0-15
 They have no memory.we will look at adding some next time
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22. Conclusion
 In this project we design and impliment 2-bit ALU.for simulation we impliment
this project on breadboard found satisfactory result different type of
simulation like and or xor addition and substruction operation.
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23. Future Implimentation
 We impliment 2-bit ALU, but we want to work on 8 bit ALU, later on we
will try to work on 32 bit and 64 bit ALU as much we can
 Our purpose is to reduce delay time
 To make circuit complex free and less expensive.
 Reduce logic gate as much as possible.
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24. Verilog code
 module ALU(input [3:0]ALUOP,input [1:0]A,B,
 output reg [1:0]R,output reg C);
 always@(*)begin
 case(ALUOP)
 4'b0000: {C,R}=(A+B);
 4'b0001: {C,R}=(A-B);
 4'b0010: R=(A&B);
 4'b0011: R=~(A&B);
 4'b0100: R=(A|B);
 4'b0101: R=~(A|B);
 4'b0110: R=(A^B);
 4'b0111: R=~(A^B);
 4'b1000,4'b1001:R=~(A);
 default: R=4'bxxxx;
 endcase
 end
 endmodule
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25. Verilog code screen shot
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26. Verilog code screen shot
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27. Verilog code screen shot
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28. Inquiry
2014-2-60-035@ewu.edu.bd
farhatanvir65@gmail.com
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29. Referrance
 https://commons.wikimedia.org/wiki/File:2
-bit_ALU.png
 https://www.mathworks.com/matlabcentra
l/fileexchange/36074-2-bit-
alu?requestedDomain=www.mathworks.c
om
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