Name of the project: Logic Gate Tester for DELD EE3114
1.1Abstract:
Performing various types of logic operation we need to use logic gates and in integrated circuit there are more than one gates fabricated in a single IC. Before using gates for various purposes we need to check logic gates including all logic
combination considering in Binary (Logic 1 & 0) needs to implement. It is a time consuming task to check all the input combinations, thus the sole purpose of this project to make it automatic to check all the logic .
Keypad is a common interface with any microcontroller. This presentation gives details of keypad can be interfaced with 8051. The key pressed may be dispalyed on LCD/7 segment/LED displays.
This presentation discusses the support for interrupts in 8051. The interrupt types, interrupts versus polling etc are discussed. The register formats of IE, IP register are discussed. The concept of priority among the interrupts is discussed.
Counters:
Introduction, Asynchronous counter, Terms related to counters, IC-7493 (4-bit binary counter), Synchronous counter, Bushing, Type T-Design, Type JK Design, Presettable counter, IC-7490, IC 7492, Synchronous counter ICs, Analysis of counter circuits
Keypad is a common interface with any microcontroller. This presentation gives details of keypad can be interfaced with 8051. The key pressed may be dispalyed on LCD/7 segment/LED displays.
This presentation discusses the support for interrupts in 8051. The interrupt types, interrupts versus polling etc are discussed. The register formats of IE, IP register are discussed. The concept of priority among the interrupts is discussed.
Counters:
Introduction, Asynchronous counter, Terms related to counters, IC-7493 (4-bit binary counter), Synchronous counter, Bushing, Type T-Design, Type JK Design, Presettable counter, IC-7490, IC 7492, Synchronous counter ICs, Analysis of counter circuits
it covers topics Introduction
Classification of Logic Families
Important point
Level of Integration
Specification of Digital ICs
TTL Circuit
TTL NAND Gates
MOS/CMOS Circuits
CMOS NAND Gate
ECL Circuit
Comparison
Numbers of Digital ICs
1.Introduction
The 555 IC was designed in 1971 by Hans Camenzind under contract to SigNetics Corporation.
555 timer is a highly stable circuit used to generate time delays, or Oscillations.
A single 555 timer can provide time delay ranging from microseconds to hours.
It operates from a wide range of power supplies ranging from + 5 Volts to + 18 Volts supply voltage.
2.Pin Configuration
3.Working of Pin
4.555 Integral circuit
5.Operating modes of IC
6. Bistable Mode
In bistable (also called Schmitt trigger) mode, the 555 timer acts as a basic flip-flop.
The trigger and reset inputs (pins 2 and 4 respectively on a 555) are held high via pull-up resistors while the threshold input (pin 6) is simply floating.
Thus configured, pulling the trigger momentarily to ground acts as a 'set' and transitions the output pin (pin 3) to Vcc (high state).
Pulling the reset input to ground acts as a 'reset' and transitions the output pin to ground (low state). No timing capacitors
Pin 5 (control voltage) is connected to ground via a small-value capacitor (usually 0.01 to 0.1 μF). Pin 7 (discharge) is left floating
7.Monostable Mode
Pulse generator circuit which the period is calculated from RC network and connected to external of 555 timer
Stable when the output logic LOW (logic = 0)
When a pulse is trigger at pin 2 (normally negative trigger pulse), timer output will change to HIGH (+Vs) for a while and change to LOW (stable condition). The condition will continue LOW until pulse is trigger again.
The timing period is triggered (started) when trigger input (555 pin 2) is less than 1/3 Vs, this makes the output high (+Vs) and the capacitor C1 starts to charge through resistor R1. Once the time period has started further trigger pulses are ignored.
The threshold input (555 pin 6) monitors the voltage across C1 and when this reaches 2/3 Vs the time period over and the output becomes LOW,
At the same time discharge (555 pin 7) is connected to 0V, discharging the capacitor ready for the next trigger.
8.Astable Mode
Astable multivibrators are also known as Free-running Multivibrator.
Astable do not need trigger pulse for external to change the output.
The period for LOW and HIGH can be calculated based on resistor and capacitor value that connected at outside of timer.
9.Applications
Schmitt trigger
PPM
PWM
Linear Ramp generator
Precision Timing
Pulse Generation
Time Delay Generation
Sequential Timing
Used as a quad timer
10. Conclusion
Hence 555 IC timer can produce very accurate and stable time delays, from microseconds to hours. It can be used with supply voltage varying from 5 to 18 V. Timer can be used in monostable mode of operation or astable mode of operation. Its various applications include waveform generator, missing pulse detector, frequency divider, pulse width modulator, burglar alarm, FSK generator, ramp generator, pulse position modulator etc.
Microcontroller based Integrated Circuit TesterIJERA Editor
The digital integrated circuit (IC) tester is implemented by using the ATmega32 microcontroller . The microcontroller processes the inputs and outputs and displays the results on a Liquid Crystal Display (LCD). The basic function of the digital IC tester is to test a digital IC for correct logical functioning as described in the truth table and/or function table. The designed model can test digital ICs having 14 pins. Since it is programmable, any number of ICs can be tested . This model applies the necessary signals to the inputs of the IC, monitoring the outputs at each stage and comparing them with the outputs in the truth table. Any discrepancy in the functioning of the IC results in a fail indication, displays the faulty and good gates on the LCD. The testing procedure is accomplished with the help of keypad keys present on the main board design. The test has been accomplished with most commonly used digital IC's, mainly belonging to the 74 series. Digital IC tester tests three samples of IC's ( NAND, NOT, NOR). The design is flexible . We can add extra IC bases and subroutines to test any other IC in the 74 series.
it covers topics Introduction
Classification of Logic Families
Important point
Level of Integration
Specification of Digital ICs
TTL Circuit
TTL NAND Gates
MOS/CMOS Circuits
CMOS NAND Gate
ECL Circuit
Comparison
Numbers of Digital ICs
1.Introduction
The 555 IC was designed in 1971 by Hans Camenzind under contract to SigNetics Corporation.
555 timer is a highly stable circuit used to generate time delays, or Oscillations.
A single 555 timer can provide time delay ranging from microseconds to hours.
It operates from a wide range of power supplies ranging from + 5 Volts to + 18 Volts supply voltage.
2.Pin Configuration
3.Working of Pin
4.555 Integral circuit
5.Operating modes of IC
6. Bistable Mode
In bistable (also called Schmitt trigger) mode, the 555 timer acts as a basic flip-flop.
The trigger and reset inputs (pins 2 and 4 respectively on a 555) are held high via pull-up resistors while the threshold input (pin 6) is simply floating.
Thus configured, pulling the trigger momentarily to ground acts as a 'set' and transitions the output pin (pin 3) to Vcc (high state).
Pulling the reset input to ground acts as a 'reset' and transitions the output pin to ground (low state). No timing capacitors
Pin 5 (control voltage) is connected to ground via a small-value capacitor (usually 0.01 to 0.1 μF). Pin 7 (discharge) is left floating
7.Monostable Mode
Pulse generator circuit which the period is calculated from RC network and connected to external of 555 timer
Stable when the output logic LOW (logic = 0)
When a pulse is trigger at pin 2 (normally negative trigger pulse), timer output will change to HIGH (+Vs) for a while and change to LOW (stable condition). The condition will continue LOW until pulse is trigger again.
The timing period is triggered (started) when trigger input (555 pin 2) is less than 1/3 Vs, this makes the output high (+Vs) and the capacitor C1 starts to charge through resistor R1. Once the time period has started further trigger pulses are ignored.
The threshold input (555 pin 6) monitors the voltage across C1 and when this reaches 2/3 Vs the time period over and the output becomes LOW,
At the same time discharge (555 pin 7) is connected to 0V, discharging the capacitor ready for the next trigger.
8.Astable Mode
Astable multivibrators are also known as Free-running Multivibrator.
Astable do not need trigger pulse for external to change the output.
The period for LOW and HIGH can be calculated based on resistor and capacitor value that connected at outside of timer.
9.Applications
Schmitt trigger
PPM
PWM
Linear Ramp generator
Precision Timing
Pulse Generation
Time Delay Generation
Sequential Timing
Used as a quad timer
10. Conclusion
Hence 555 IC timer can produce very accurate and stable time delays, from microseconds to hours. It can be used with supply voltage varying from 5 to 18 V. Timer can be used in monostable mode of operation or astable mode of operation. Its various applications include waveform generator, missing pulse detector, frequency divider, pulse width modulator, burglar alarm, FSK generator, ramp generator, pulse position modulator etc.
Microcontroller based Integrated Circuit TesterIJERA Editor
The digital integrated circuit (IC) tester is implemented by using the ATmega32 microcontroller . The microcontroller processes the inputs and outputs and displays the results on a Liquid Crystal Display (LCD). The basic function of the digital IC tester is to test a digital IC for correct logical functioning as described in the truth table and/or function table. The designed model can test digital ICs having 14 pins. Since it is programmable, any number of ICs can be tested . This model applies the necessary signals to the inputs of the IC, monitoring the outputs at each stage and comparing them with the outputs in the truth table. Any discrepancy in the functioning of the IC results in a fail indication, displays the faulty and good gates on the LCD. The testing procedure is accomplished with the help of keypad keys present on the main board design. The test has been accomplished with most commonly used digital IC's, mainly belonging to the 74 series. Digital IC tester tests three samples of IC's ( NAND, NOT, NOR). The design is flexible . We can add extra IC bases and subroutines to test any other IC in the 74 series.
Stanley a Meyers analysis and test results of gated pulse frequency generator...Daniel Donatelli
Stanley a Meyers analysis and test results of gated pulse frequency generator functional description www.hot-rod-usa.com #hydrogen #hho #electronics #circuits
LF Energy Webinar: Electrical Grid Modelling and Simulation Through PowSyBl -...DanBrown980551
Do you want to learn how to model and simulate an electrical network from scratch in under an hour?
Then welcome to this PowSyBl workshop, hosted by Rte, the French Transmission System Operator (TSO)!
During the webinar, you will discover the PowSyBl ecosystem as well as handle and study an electrical network through an interactive Python notebook.
PowSyBl is an open source project hosted by LF Energy, which offers a comprehensive set of features for electrical grid modelling and simulation. Among other advanced features, PowSyBl provides:
- A fully editable and extendable library for grid component modelling;
- Visualization tools to display your network;
- Grid simulation tools, such as power flows, security analyses (with or without remedial actions) and sensitivity analyses;
The framework is mostly written in Java, with a Python binding so that Python developers can access PowSyBl functionalities as well.
What you will learn during the webinar:
- For beginners: discover PowSyBl's functionalities through a quick general presentation and the notebook, without needing any expert coding skills;
- For advanced developers: master the skills to efficiently apply PowSyBl functionalities to your real-world scenarios.
Accelerate your Kubernetes clusters with Varnish CachingThijs Feryn
A presentation about the usage and availability of Varnish on Kubernetes. This talk explores the capabilities of Varnish caching and shows how to use the Varnish Helm chart to deploy it to Kubernetes.
This presentation was delivered at K8SUG Singapore. See https://feryn.eu/presentations/accelerate-your-kubernetes-clusters-with-varnish-caching-k8sug-singapore-28-2024 for more details.
GraphRAG is All You need? LLM & Knowledge GraphGuy Korland
Guy Korland, CEO and Co-founder of FalkorDB, will review two articles on the integration of language models with knowledge graphs.
1. Unifying Large Language Models and Knowledge Graphs: A Roadmap.
https://arxiv.org/abs/2306.08302
2. Microsoft Research's GraphRAG paper and a review paper on various uses of knowledge graphs:
https://www.microsoft.com/en-us/research/blog/graphrag-unlocking-llm-discovery-on-narrative-private-data/
GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using Deplo...James Anderson
Effective Application Security in Software Delivery lifecycle using Deployment Firewall and DBOM
The modern software delivery process (or the CI/CD process) includes many tools, distributed teams, open-source code, and cloud platforms. Constant focus on speed to release software to market, along with the traditional slow and manual security checks has caused gaps in continuous security as an important piece in the software supply chain. Today organizations feel more susceptible to external and internal cyber threats due to the vast attack surface in their applications supply chain and the lack of end-to-end governance and risk management.
The software team must secure its software delivery process to avoid vulnerability and security breaches. This needs to be achieved with existing tool chains and without extensive rework of the delivery processes. This talk will present strategies and techniques for providing visibility into the true risk of the existing vulnerabilities, preventing the introduction of security issues in the software, resolving vulnerabilities in production environments quickly, and capturing the deployment bill of materials (DBOM).
Speakers:
Bob Boule
Robert Boule is a technology enthusiast with PASSION for technology and making things work along with a knack for helping others understand how things work. He comes with around 20 years of solution engineering experience in application security, software continuous delivery, and SaaS platforms. He is known for his dynamic presentations in CI/CD and application security integrated in software delivery lifecycle.
Gopinath Rebala
Gopinath Rebala is the CTO of OpsMx, where he has overall responsibility for the machine learning and data processing architectures for Secure Software Delivery. Gopi also has a strong connection with our customers, leading design and architecture for strategic implementations. Gopi is a frequent speaker and well-known leader in continuous delivery and integrating security into software delivery.
Smart TV Buyer Insights Survey 2024 by 91mobiles.pdf91mobiles
91mobiles recently conducted a Smart TV Buyer Insights Survey in which we asked over 3,000 respondents about the TV they own, aspects they look at on a new TV, and their TV buying preferences.
Connector Corner: Automate dynamic content and events by pushing a buttonDianaGray10
Here is something new! In our next Connector Corner webinar, we will demonstrate how you can use a single workflow to:
Create a campaign using Mailchimp with merge tags/fields
Send an interactive Slack channel message (using buttons)
Have the message received by managers and peers along with a test email for review
But there’s more:
In a second workflow supporting the same use case, you’ll see:
Your campaign sent to target colleagues for approval
If the “Approve” button is clicked, a Jira/Zendesk ticket is created for the marketing design team
But—if the “Reject” button is pushed, colleagues will be alerted via Slack message
Join us to learn more about this new, human-in-the-loop capability, brought to you by Integration Service connectors.
And...
Speakers:
Akshay Agnihotri, Product Manager
Charlie Greenberg, Host
State of ICS and IoT Cyber Threat Landscape Report 2024 previewPrayukth K V
The IoT and OT threat landscape report has been prepared by the Threat Research Team at Sectrio using data from Sectrio, cyber threat intelligence farming facilities spread across over 85 cities around the world. In addition, Sectrio also runs AI-based advanced threat and payload engagement facilities that serve as sinks to attract and engage sophisticated threat actors, and newer malware including new variants and latent threats that are at an earlier stage of development.
The latest edition of the OT/ICS and IoT security Threat Landscape Report 2024 also covers:
State of global ICS asset and network exposure
Sectoral targets and attacks as well as the cost of ransom
Global APT activity, AI usage, actor and tactic profiles, and implications
Rise in volumes of AI-powered cyberattacks
Major cyber events in 2024
Malware and malicious payload trends
Cyberattack types and targets
Vulnerability exploit attempts on CVEs
Attacks on counties – USA
Expansion of bot farms – how, where, and why
In-depth analysis of the cyber threat landscape across North America, South America, Europe, APAC, and the Middle East
Why are attacks on smart factories rising?
Cyber risk predictions
Axis of attacks – Europe
Systemic attacks in the Middle East
Download the full report from here:
https://sectrio.com/resources/ot-threat-landscape-reports/sectrio-releases-ot-ics-and-iot-security-threat-landscape-report-2024/
UiPath Test Automation using UiPath Test Suite series, part 3DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 3. In this session, we will cover desktop automation along with UI automation.
Topics covered:
UI automation Introduction,
UI automation Sample
Desktop automation flow
Pradeep Chinnala, Senior Consultant Automation Developer @WonderBotz and UiPath MVP
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
Knowledge engineering: from people to machines and back
Logic gate tester for IC's ( Digital Electronics and Logic deisgn EE3114 )
1. Date of Submission
23-Jan-2019
Course No: EE3200
Course Title: Electrical and Electronic Project Design
Report on
Logic Gate Tester for DELD EE3114
Submitted To
Dr.Md.Habibullah
AssistantProfessr
Dept of EEE, KUET
Submitted By
Md. Jikrul Sayeed Hossain
Roll: 1503048
Dept of EEE, KUET
2. 1
Name of the project: Logic Gate Tester for DELD EE3114
1.1Abstract:
Performing various types of logic operation we need to use logic gates and in
integrated circuit there are more than one gates fabricated in a single IC. Before
using gates for various purposes we need to check logic gates including all logic
combination considering in Binary (Logic 1 & 0) needs to implement. It is a time
consuming task to check all the input combinations, thus the sole purpose of this
project to make it automatic to check all the logic .
1.2Objectives:
i) To make an automatic system to check logic gates.
ii) To Display every checking information including all logic
combinations.
iii) To learn about designing PCB & making it by hand.
3. 2
1.3Introduction:
Logic gates are the basic building blocks of any digital system. It is an electronic
circuit having one or more than one input and only one output. The relationship
between the input and the output is based on a certain logic. Based on this, logic
gates are named as AND gate, OR gate, NOT gate, NAND gate, NOR gate, EXOR gate
and EXNOR gate.
AND Gate
A circuit which performs an AND operation is shown in figure. It has n input
(n >= 2) and one output.
Logic diagram Truth Table
OR Gate
A circuit which performs an OR operation is shown in figure. It has n input (n
>= 2) and one output.
Logic diagram Truth Table
4. 3
NOT Gate
NOT gate is also known as Inverter. It has one input A and one output Y.
Logic diagram Truth Table
NAND Gate
A NOT-AND operation is known as NAND operation. It has n input (n >= 2)
and one output.
Logic diagram Truth Table
NOR Gate
A NOT-OR operation is known as NOR operation. It has n input (n >= 2) and
one output.
Logic diagram Truth Table
5. 4
XOR Gate
XOR or Ex-OR gate is a special type of gate. It can be used in the half adder,
full adder and subtractor. The exclusive-OR gate is abbreviated as EX-OR
gate or sometime as X-OR gate. It has n input (n >= 2) and one output.
Logic diagram Truth Table
XNOR Gate
XNOR gate is a special type of gate. It can be used in the half adder, full
adder and subtractor. The exclusive-NOR gate is abbreviated as EX-NOR gate
or sometime as X-NOR gate. It has n input (n >= 2) and one output.
Logic diagram Truth Table
In this project moreover we need to use power supply for constant supply. Which
we use 7809 IC’s & an Arduino Mega is being used to implement logic conditions
automatically. 12 LCD’s are being used to indicate the result to confirm which gate
is Good & which one is Bad.
7. 6
1.5PCB Diagram:
Fig3: PCB Diagram Footer.
1.6WorkingPrinciple:
As we know that High Voltage (+5VDC) as a logic HIGH or 1 and Low Voltage (0VDC)
as a logic LOW or 0 is used in Binary Calculation. Here a Arduino Mega is used to
set various DIGITAL PIN as HIGH(1) LOW(0) combination for 2 input get like HIGH
HIGH , LOW HIGH , HIGH LOW , LOW LOW combinations. Then we use another PIN
to read the output state of the Gate and compare the output with the predefined
LOGIC table previously saved in the ARDUINO MEGA memory Unit. If the conditions
matched (all combination) then we can call the Gate as good & the Green LED is
being bright for corresponding gate in the IC. If any of the combinational output
makes a false result after comparing with Truth Table then the gate will be declared
as BAD gate and Red light is being bright for the corresponding number of Gate in
the IC. This process is being set with the respective IC number which needs to give
from the user interface keyboard & a display also shows the running logic that is
being used to check to find out the logic gate as good or bad.
8. 7
1.7Operating Principle:
Plug IN to 220V line of Power suppy
Put your IC on Zif Socket from left
Enter you IC number
Press “#” to Confirm IC number
LCD will Show the Logic’s
& LED will Show the gate’s Condition as
Green is good & Red is Bad
9. 8
1.8List of Permissible IC for the Project Prototype: (Table 1.1)
IC Number Name Number of
input
Number of
Gate
7400 2-input NAND 2 4
7402 2-input NOR 2 4
7404 NOT 1 6
7408 2-input AND 2 4
7432 2-input OR 2 4
7486 2-input EXOR 2 4
74286 2-input EXNOR 2 4
7411 3-input AND 3 3
1.9List & Cost of component:
SL NO Name Rating Quantity Cost(tk)
1. Ardunio Mega2560 ATmega2560
microcontroller
Input voltage - 7-12V
54 Digital I/O Pins (14
PWM outputs)
16 Analog Inputs
256k Flash Memory
16Mhz Clock Speed
01 850
2. 16*2 LCD Display Vdd -Vss (0-5VDC)
Imax 3mA
Duty 1/16
16*2 characters
built-in 5*8 alpha
numeric character ROM
standard 4bit or 8bit
parallel interface
01 180
3. 4*4 Key Pad Cable Length: 3.3 inch
Keypad Width: 2.7 inch
Keypad Length : 3.0inch
Number of keys: 16
Matrix: 4×4
01 75
4. Zif socket (28 pin)
(IC base)
ZIF (zero insertion force)
design
01 85
10. 9
contacts: 28
lead pitch 0.1" (100 mil)
an ideal IC test socket
5. LED
(Green & Red)
Vf= 1.90V
Rated If=10mA
14 28
6. Registor 220ohm, 1k ; 0.5W 2 4
7. Variable Registor 10K 1 15
8. IC7809 Output Voltage:9V
Peak Current:2.2A
Short Circuit
Current:250mA
1 15
9. Transformer
(220/12V)
Primary Voltage:220V
Secondary Voltage:12V
Current rating:1A
1 110
10. Plug 220V,10A 1 20
11. PCB Board 1 280
12. Jumper
Male to male
Male to female
As required 20
13. Connector Copper (26G) As required 20
14. Test IC’s
(Logic Gates)
7804,7808 As required 30
Total Cost: 1732tk
1.10Description of Circuit Component: [Pictorial View of Circuit Components]
Arduino Mega R3 2560 16*2 LCD Display (LMB162ABC)
11. 10
4*4 Key Pad Zif socket (28 pin)
LED (RED) 10K (Potentiometer)
IC7809 220/12V 1A step down transformer
Fig4: Pictorial View of Used Circuit Component
14. 13
1.12Conclusion:
This is a project to check logic gates simply & automatically. The basic principle of
checking gates is that every logic has an individual truth table and we set the truth
table in memory when we call it through IC number it will check the truth table
and give the result of the IC conditions. This project is designed to use in the
Digital Electronics and Logic Design Laboratory (a course of EE3114) to make IC
checking easily and reduce the time.
1.12Future Improvement:
This project has a lot of possibilities as follows:
1) Adding 3 input IC’s
2) The circuit and code can be made more advanced to check other IC’s such as
T, D, F flip-flop.
3) Some modified truth tables to compare any other complete circuits those
are made by Logic Gates.
1.13 References
i) Digital Logic and Computer Design by M. Morris Mano
ii) www.en.wikipedia.org/wiki/Logic_gate