SlideShare a Scribd company logo
Date of Submission
23-Jan-2019
Course No: EE3200
Course Title: Electrical and Electronic Project Design
Report on
Logic Gate Tester for DELD EE3114
Submitted To
Dr.Md.Habibullah
AssistantProfessr
Dept of EEE, KUET
Submitted By
Md. Jikrul Sayeed Hossain
Roll: 1503048
Dept of EEE, KUET
1
Name of the project: Logic Gate Tester for DELD EE3114
1.1Abstract:
Performing various types of logic operation we need to use logic gates and in
integrated circuit there are more than one gates fabricated in a single IC. Before
using gates for various purposes we need to check logic gates including all logic
combination considering in Binary (Logic 1 & 0) needs to implement. It is a time
consuming task to check all the input combinations, thus the sole purpose of this
project to make it automatic to check all the logic .
1.2Objectives:
i) To make an automatic system to check logic gates.
ii) To Display every checking information including all logic
combinations.
iii) To learn about designing PCB & making it by hand.
2
1.3Introduction:
Logic gates are the basic building blocks of any digital system. It is an electronic
circuit having one or more than one input and only one output. The relationship
between the input and the output is based on a certain logic. Based on this, logic
gates are named as AND gate, OR gate, NOT gate, NAND gate, NOR gate, EXOR gate
and EXNOR gate.
AND Gate
A circuit which performs an AND operation is shown in figure. It has n input
(n >= 2) and one output.
Logic diagram Truth Table
OR Gate
A circuit which performs an OR operation is shown in figure. It has n input (n
>= 2) and one output.
Logic diagram Truth Table
3
NOT Gate
NOT gate is also known as Inverter. It has one input A and one output Y.
Logic diagram Truth Table
NAND Gate
A NOT-AND operation is known as NAND operation. It has n input (n >= 2)
and one output.
Logic diagram Truth Table
NOR Gate
A NOT-OR operation is known as NOR operation. It has n input (n >= 2) and
one output.
Logic diagram Truth Table
4
XOR Gate
XOR or Ex-OR gate is a special type of gate. It can be used in the half adder,
full adder and subtractor. The exclusive-OR gate is abbreviated as EX-OR
gate or sometime as X-OR gate. It has n input (n >= 2) and one output.
Logic diagram Truth Table
XNOR Gate
XNOR gate is a special type of gate. It can be used in the half adder, full
adder and subtractor. The exclusive-NOR gate is abbreviated as EX-NOR gate
or sometime as X-NOR gate. It has n input (n >= 2) and one output.
Logic diagram Truth Table
In this project moreover we need to use power supply for constant supply. Which
we use 7809 IC’s & an Arduino Mega is being used to implement logic conditions
automatically. 12 LCD’s are being used to indicate the result to confirm which gate
is Good & which one is Bad.
5
1.4Circuit Diagram:
fig1: Main Circuit Diagram without Arduino
Fig2: Main Circuit Diagram with Arduino MEGA
6
1.5PCB Diagram:
Fig3: PCB Diagram Footer.
1.6WorkingPrinciple:
As we know that High Voltage (+5VDC) as a logic HIGH or 1 and Low Voltage (0VDC)
as a logic LOW or 0 is used in Binary Calculation. Here a Arduino Mega is used to
set various DIGITAL PIN as HIGH(1) LOW(0) combination for 2 input get like HIGH
HIGH , LOW HIGH , HIGH LOW , LOW LOW combinations. Then we use another PIN
to read the output state of the Gate and compare the output with the predefined
LOGIC table previously saved in the ARDUINO MEGA memory Unit. If the conditions
matched (all combination) then we can call the Gate as good & the Green LED is
being bright for corresponding gate in the IC. If any of the combinational output
makes a false result after comparing with Truth Table then the gate will be declared
as BAD gate and Red light is being bright for the corresponding number of Gate in
the IC. This process is being set with the respective IC number which needs to give
from the user interface keyboard & a display also shows the running logic that is
being used to check to find out the logic gate as good or bad.
7
1.7Operating Principle:
Plug IN to 220V line of Power suppy
Put your IC on Zif Socket from left
Enter you IC number
Press “#” to Confirm IC number
LCD will Show the Logic’s
& LED will Show the gate’s Condition as
Green is good & Red is Bad
8
1.8List of Permissible IC for the Project Prototype: (Table 1.1)
IC Number Name Number of
input
Number of
Gate
7400 2-input NAND 2 4
7402 2-input NOR 2 4
7404 NOT 1 6
7408 2-input AND 2 4
7432 2-input OR 2 4
7486 2-input EXOR 2 4
74286 2-input EXNOR 2 4
7411 3-input AND 3 3
1.9List & Cost of component:
SL NO Name Rating Quantity Cost(tk)
1. Ardunio Mega2560 ATmega2560
microcontroller
Input voltage - 7-12V
54 Digital I/O Pins (14
PWM outputs)
16 Analog Inputs
256k Flash Memory
16Mhz Clock Speed
01 850
2. 16*2 LCD Display Vdd -Vss (0-5VDC)
Imax 3mA
Duty 1/16
16*2 characters
built-in 5*8 alpha
numeric character ROM
standard 4bit or 8bit
parallel interface
01 180
3. 4*4 Key Pad Cable Length: 3.3 inch
Keypad Width: 2.7 inch
Keypad Length : 3.0inch
Number of keys: 16
Matrix: 4×4
01 75
4. Zif socket (28 pin)
(IC base)
ZIF (zero insertion force)
design
01 85
9
contacts: 28
lead pitch 0.1" (100 mil)
an ideal IC test socket
5. LED
(Green & Red)
Vf= 1.90V
Rated If=10mA
14 28
6. Registor 220ohm, 1k ; 0.5W 2 4
7. Variable Registor 10K 1 15
8. IC7809 Output Voltage:9V
Peak Current:2.2A
Short Circuit
Current:250mA
1 15
9. Transformer
(220/12V)
Primary Voltage:220V
Secondary Voltage:12V
Current rating:1A
1 110
10. Plug 220V,10A 1 20
11. PCB Board 1 280
12. Jumper
Male to male
Male to female
As required 20
13. Connector Copper (26G) As required 20
14. Test IC’s
(Logic Gates)
7804,7808 As required 30
Total Cost: 1732tk
1.10Description of Circuit Component: [Pictorial View of Circuit Components]
Arduino Mega R3 2560 16*2 LCD Display (LMB162ABC)
10
4*4 Key Pad Zif socket (28 pin)
LED (RED) 10K (Potentiometer)
IC7809 220/12V 1A step down transformer
Fig4: Pictorial View of Used Circuit Component
11
1.11Practical Implementation:
12
Fig5: Practical view of circuit Implementation
13
1.12Conclusion:
This is a project to check logic gates simply & automatically. The basic principle of
checking gates is that every logic has an individual truth table and we set the truth
table in memory when we call it through IC number it will check the truth table
and give the result of the IC conditions. This project is designed to use in the
Digital Electronics and Logic Design Laboratory (a course of EE3114) to make IC
checking easily and reduce the time.
1.12Future Improvement:
This project has a lot of possibilities as follows:
1) Adding 3 input IC’s
2) The circuit and code can be made more advanced to check other IC’s such as
T, D, F flip-flop.
3) Some modified truth tables to compare any other complete circuits those
are made by Logic Gates.
1.13 References
i) Digital Logic and Computer Design by M. Morris Mano
ii) www.en.wikipedia.org/wiki/Logic_gate

More Related Content

What's hot

Distance measurement using Ultrasonic sensor on Arduino Uno
Distance measurement using Ultrasonic sensor on Arduino UnoDistance measurement using Ultrasonic sensor on Arduino Uno
Distance measurement using Ultrasonic sensor on Arduino Uno
Aswin KP
 
8051 Assembly Language Programming
8051 Assembly Language Programming8051 Assembly Language Programming
8051 Assembly Language Programming
Ravikumar Tiwari
 
2019 2 testing and verification of vlsi design_verification
2019 2 testing and verification of vlsi design_verification2019 2 testing and verification of vlsi design_verification
2019 2 testing and verification of vlsi design_verification
Usha Mehta
 
Ring Counter.pptx
Ring Counter.pptxRing Counter.pptx
Ring Counter.pptx
hepzijustin
 
Timer programming for 8051 using embedded c
Timer programming for 8051 using embedded cTimer programming for 8051 using embedded c
Timer programming for 8051 using embedded c
Vikas Dongre
 
Floor plan & Power Plan
Floor plan & Power Plan Floor plan & Power Plan
Floor plan & Power Plan
Prathyusha Madapalli
 
Subroutine in 8051 microcontroller
Subroutine in 8051 microcontrollerSubroutine in 8051 microcontroller
Subroutine in 8051 microcontroller
bhadresh savani
 
Digital electronics logic families
Digital electronics logic familiesDigital electronics logic families
Digital electronics logic families
BLESSINAR0
 
Logic synthesis using Verilog HDL
Logic synthesis using Verilog HDLLogic synthesis using Verilog HDL
Logic synthesis using Verilog HDL
anand hd
 
Hybrid Transistor Model with Two Port Network
Hybrid Transistor Model with Two Port NetworkHybrid Transistor Model with Two Port Network
Hybrid Transistor Model with Two Port Network
Ridwanul Hoque
 
A.gate by-rk-kanodia
A.gate by-rk-kanodiaA.gate by-rk-kanodia
A.gate by-rk-kanodia
Venugopala Rao P
 
Ic 555
Ic 555Ic 555
Password Security System
Password Security SystemPassword Security System
Password Security System
Green University of Bangladesh
 
Presentation on 8086 Microprocessor
Presentation  on   8086 MicroprocessorPresentation  on   8086 Microprocessor
Presentation on 8086 Microprocessor
Nahian Ahmed
 
Vlsi physical design
Vlsi physical designVlsi physical design
Vlsi physical designI World Tech
 
Wallace tree multiplier.pptx1
Wallace tree multiplier.pptx1Wallace tree multiplier.pptx1
Wallace tree multiplier.pptx1
vamshi krishna
 

What's hot (20)

Vlsi design
Vlsi designVlsi design
Vlsi design
 
Distance measurement using Ultrasonic sensor on Arduino Uno
Distance measurement using Ultrasonic sensor on Arduino UnoDistance measurement using Ultrasonic sensor on Arduino Uno
Distance measurement using Ultrasonic sensor on Arduino Uno
 
8051 Assembly Language Programming
8051 Assembly Language Programming8051 Assembly Language Programming
8051 Assembly Language Programming
 
2019 2 testing and verification of vlsi design_verification
2019 2 testing and verification of vlsi design_verification2019 2 testing and verification of vlsi design_verification
2019 2 testing and verification of vlsi design_verification
 
Ring Counter.pptx
Ring Counter.pptxRing Counter.pptx
Ring Counter.pptx
 
Timer programming for 8051 using embedded c
Timer programming for 8051 using embedded cTimer programming for 8051 using embedded c
Timer programming for 8051 using embedded c
 
Floor plan & Power Plan
Floor plan & Power Plan Floor plan & Power Plan
Floor plan & Power Plan
 
logic family
logic familylogic family
logic family
 
Subroutine in 8051 microcontroller
Subroutine in 8051 microcontrollerSubroutine in 8051 microcontroller
Subroutine in 8051 microcontroller
 
Digital electronics logic families
Digital electronics logic familiesDigital electronics logic families
Digital electronics logic families
 
Logic synthesis using Verilog HDL
Logic synthesis using Verilog HDLLogic synthesis using Verilog HDL
Logic synthesis using Verilog HDL
 
Hybrid Transistor Model with Two Port Network
Hybrid Transistor Model with Two Port NetworkHybrid Transistor Model with Two Port Network
Hybrid Transistor Model with Two Port Network
 
A.gate by-rk-kanodia
A.gate by-rk-kanodiaA.gate by-rk-kanodia
A.gate by-rk-kanodia
 
Shift register
Shift registerShift register
Shift register
 
Ic 555
Ic 555Ic 555
Ic 555
 
Password Security System
Password Security SystemPassword Security System
Password Security System
 
Presentation on 8086 Microprocessor
Presentation  on   8086 MicroprocessorPresentation  on   8086 Microprocessor
Presentation on 8086 Microprocessor
 
Vlsi physical design
Vlsi physical designVlsi physical design
Vlsi physical design
 
Pass transistor logic
Pass transistor logicPass transistor logic
Pass transistor logic
 
Wallace tree multiplier.pptx1
Wallace tree multiplier.pptx1Wallace tree multiplier.pptx1
Wallace tree multiplier.pptx1
 

Similar to Logic gate tester for IC's ( Digital Electronics and Logic deisgn EE3114 )

Microcontroller based Integrated Circuit Tester
Microcontroller based Integrated Circuit TesterMicrocontroller based Integrated Circuit Tester
Microcontroller based Integrated Circuit Tester
IJERA Editor
 
Deld lab manual
Deld lab manualDeld lab manual
Deld lab manual
Vivek Kumar Sinha
 
Microprocessorlabmanual ee0310
Microprocessorlabmanual ee0310Microprocessorlabmanual ee0310
Microprocessorlabmanual ee0310
Hari Prakash
 
Micro Processor Lab Manual!
Micro Processor Lab Manual!Micro Processor Lab Manual!
Micro Processor Lab Manual!
PRABHAHARAN429
 
2th year iv sem de lab manual
2th year iv sem de lab manual2th year iv sem de lab manual
2th year iv sem de lab manual
HARISH KUMAR MAHESHWARI
 
Boolean Algebra- Digital Logic gates
Boolean Algebra- Digital Logic gatesBoolean Algebra- Digital Logic gates
Boolean Algebra- Digital Logic gates
NTBsnull
 
FPGA Implementation with Digital Devices
FPGA Implementation with Digital Devices FPGA Implementation with Digital Devices
FPGA Implementation with Digital Devices
Sachin Mehta
 
Bidirect visitor counter
Bidirect visitor counterBidirect visitor counter
Bidirect visitor counter
Electric&elctronics&engineeering
 
ARDUINO BASED TIME AND TEMPERATURE DISPLAY
ARDUINO BASED TIME AND TEMPERATURE DISPLAY ARDUINO BASED TIME AND TEMPERATURE DISPLAY
ARDUINO BASED TIME AND TEMPERATURE DISPLAY
ajit kumar singh
 
Microprocessor lab manual
Microprocessor lab manualMicroprocessor lab manual
Microprocessor lab manual
Dhaval Shukla
 
Cse
CseCse
Microprocessorlabmanual ee0310
Microprocessorlabmanual ee0310Microprocessorlabmanual ee0310
Microprocessorlabmanual ee0310
DHEERAJ DHAKAR
 
Stanley a Meyers analysis and test results of gated pulse frequency generator...
Stanley a Meyers analysis and test results of gated pulse frequency generator...Stanley a Meyers analysis and test results of gated pulse frequency generator...
Stanley a Meyers analysis and test results of gated pulse frequency generator...
Daniel Donatelli
 
Digital Logic Design basic gate and Logic Probe
Digital Logic Design basic gate and Logic ProbeDigital Logic Design basic gate and Logic Probe
Digital Logic Design basic gate and Logic Probe
AQCreations
 
CMEL 2.4 inch Amoled(240x320) Datasheet
CMEL 2.4 inch Amoled(240x320) DatasheetCMEL 2.4 inch Amoled(240x320) Datasheet
CMEL 2.4 inch Amoled(240x320) Datasheet
Panox Display
 
Worksheet de 1.2
Worksheet de 1.2Worksheet de 1.2
Worksheet de 1.2
ManojB66
 

Similar to Logic gate tester for IC's ( Digital Electronics and Logic deisgn EE3114 ) (20)

Microcontroller based Integrated Circuit Tester
Microcontroller based Integrated Circuit TesterMicrocontroller based Integrated Circuit Tester
Microcontroller based Integrated Circuit Tester
 
Deld lab manual
Deld lab manualDeld lab manual
Deld lab manual
 
Microprocessorlabmanual ee0310
Microprocessorlabmanual ee0310Microprocessorlabmanual ee0310
Microprocessorlabmanual ee0310
 
Micro Processor Lab Manual!
Micro Processor Lab Manual!Micro Processor Lab Manual!
Micro Processor Lab Manual!
 
2th year iv sem de lab manual
2th year iv sem de lab manual2th year iv sem de lab manual
2th year iv sem de lab manual
 
Boolean Algebra- Digital Logic gates
Boolean Algebra- Digital Logic gatesBoolean Algebra- Digital Logic gates
Boolean Algebra- Digital Logic gates
 
FPGA Implementation with Digital Devices
FPGA Implementation with Digital Devices FPGA Implementation with Digital Devices
FPGA Implementation with Digital Devices
 
Bidirect visitor counter
Bidirect visitor counterBidirect visitor counter
Bidirect visitor counter
 
Final Presentation
Final PresentationFinal Presentation
Final Presentation
 
ARDUINO BASED TIME AND TEMPERATURE DISPLAY
ARDUINO BASED TIME AND TEMPERATURE DISPLAY ARDUINO BASED TIME AND TEMPERATURE DISPLAY
ARDUINO BASED TIME AND TEMPERATURE DISPLAY
 
Anup2
Anup2Anup2
Anup2
 
project 3 full report
project 3 full reportproject 3 full report
project 3 full report
 
Microprocessor lab manual
Microprocessor lab manualMicroprocessor lab manual
Microprocessor lab manual
 
Cse
CseCse
Cse
 
Microprocessorlabmanual ee0310
Microprocessorlabmanual ee0310Microprocessorlabmanual ee0310
Microprocessorlabmanual ee0310
 
Stanley a Meyers analysis and test results of gated pulse frequency generator...
Stanley a Meyers analysis and test results of gated pulse frequency generator...Stanley a Meyers analysis and test results of gated pulse frequency generator...
Stanley a Meyers analysis and test results of gated pulse frequency generator...
 
Digital Logic Design basic gate and Logic Probe
Digital Logic Design basic gate and Logic ProbeDigital Logic Design basic gate and Logic Probe
Digital Logic Design basic gate and Logic Probe
 
Bds lab 4
Bds lab 4Bds lab 4
Bds lab 4
 
CMEL 2.4 inch Amoled(240x320) Datasheet
CMEL 2.4 inch Amoled(240x320) DatasheetCMEL 2.4 inch Amoled(240x320) Datasheet
CMEL 2.4 inch Amoled(240x320) Datasheet
 
Worksheet de 1.2
Worksheet de 1.2Worksheet de 1.2
Worksheet de 1.2
 

Recently uploaded

From Daily Decisions to Bottom Line: Connecting Product Work to Revenue by VP...
From Daily Decisions to Bottom Line: Connecting Product Work to Revenue by VP...From Daily Decisions to Bottom Line: Connecting Product Work to Revenue by VP...
From Daily Decisions to Bottom Line: Connecting Product Work to Revenue by VP...
Product School
 
LF Energy Webinar: Electrical Grid Modelling and Simulation Through PowSyBl -...
LF Energy Webinar: Electrical Grid Modelling and Simulation Through PowSyBl -...LF Energy Webinar: Electrical Grid Modelling and Simulation Through PowSyBl -...
LF Energy Webinar: Electrical Grid Modelling and Simulation Through PowSyBl -...
DanBrown980551
 
FIDO Alliance Osaka Seminar: Passkeys and the Road Ahead.pdf
FIDO Alliance Osaka Seminar: Passkeys and the Road Ahead.pdfFIDO Alliance Osaka Seminar: Passkeys and the Road Ahead.pdf
FIDO Alliance Osaka Seminar: Passkeys and the Road Ahead.pdf
FIDO Alliance
 
When stars align: studies in data quality, knowledge graphs, and machine lear...
When stars align: studies in data quality, knowledge graphs, and machine lear...When stars align: studies in data quality, knowledge graphs, and machine lear...
When stars align: studies in data quality, knowledge graphs, and machine lear...
Elena Simperl
 
Accelerate your Kubernetes clusters with Varnish Caching
Accelerate your Kubernetes clusters with Varnish CachingAccelerate your Kubernetes clusters with Varnish Caching
Accelerate your Kubernetes clusters with Varnish Caching
Thijs Feryn
 
GraphRAG is All You need? LLM & Knowledge Graph
GraphRAG is All You need? LLM & Knowledge GraphGraphRAG is All You need? LLM & Knowledge Graph
GraphRAG is All You need? LLM & Knowledge Graph
Guy Korland
 
GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using Deplo...
GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using Deplo...GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using Deplo...
GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using Deplo...
James Anderson
 
Smart TV Buyer Insights Survey 2024 by 91mobiles.pdf
Smart TV Buyer Insights Survey 2024 by 91mobiles.pdfSmart TV Buyer Insights Survey 2024 by 91mobiles.pdf
Smart TV Buyer Insights Survey 2024 by 91mobiles.pdf
91mobiles
 
Unsubscribed: Combat Subscription Fatigue With a Membership Mentality by Head...
Unsubscribed: Combat Subscription Fatigue With a Membership Mentality by Head...Unsubscribed: Combat Subscription Fatigue With a Membership Mentality by Head...
Unsubscribed: Combat Subscription Fatigue With a Membership Mentality by Head...
Product School
 
Connector Corner: Automate dynamic content and events by pushing a button
Connector Corner: Automate dynamic content and events by pushing a buttonConnector Corner: Automate dynamic content and events by pushing a button
Connector Corner: Automate dynamic content and events by pushing a button
DianaGray10
 
Designing Great Products: The Power of Design and Leadership by Chief Designe...
Designing Great Products: The Power of Design and Leadership by Chief Designe...Designing Great Products: The Power of Design and Leadership by Chief Designe...
Designing Great Products: The Power of Design and Leadership by Chief Designe...
Product School
 
State of ICS and IoT Cyber Threat Landscape Report 2024 preview
State of ICS and IoT Cyber Threat Landscape Report 2024 previewState of ICS and IoT Cyber Threat Landscape Report 2024 preview
State of ICS and IoT Cyber Threat Landscape Report 2024 preview
Prayukth K V
 
PCI PIN Basics Webinar from the Controlcase Team
PCI PIN Basics Webinar from the Controlcase TeamPCI PIN Basics Webinar from the Controlcase Team
PCI PIN Basics Webinar from the Controlcase Team
ControlCase
 
GenAISummit 2024 May 28 Sri Ambati Keynote: AGI Belongs to The Community in O...
GenAISummit 2024 May 28 Sri Ambati Keynote: AGI Belongs to The Community in O...GenAISummit 2024 May 28 Sri Ambati Keynote: AGI Belongs to The Community in O...
GenAISummit 2024 May 28 Sri Ambati Keynote: AGI Belongs to The Community in O...
Sri Ambati
 
UiPath Test Automation using UiPath Test Suite series, part 3
UiPath Test Automation using UiPath Test Suite series, part 3UiPath Test Automation using UiPath Test Suite series, part 3
UiPath Test Automation using UiPath Test Suite series, part 3
DianaGray10
 
The Future of Platform Engineering
The Future of Platform EngineeringThe Future of Platform Engineering
The Future of Platform Engineering
Jemma Hussein Allen
 
Mission to Decommission: Importance of Decommissioning Products to Increase E...
Mission to Decommission: Importance of Decommissioning Products to Increase E...Mission to Decommission: Importance of Decommissioning Products to Increase E...
Mission to Decommission: Importance of Decommissioning Products to Increase E...
Product School
 
To Graph or Not to Graph Knowledge Graph Architectures and LLMs
To Graph or Not to Graph Knowledge Graph Architectures and LLMsTo Graph or Not to Graph Knowledge Graph Architectures and LLMs
To Graph or Not to Graph Knowledge Graph Architectures and LLMs
Paul Groth
 
Empowering NextGen Mobility via Large Action Model Infrastructure (LAMI): pav...
Empowering NextGen Mobility via Large Action Model Infrastructure (LAMI): pav...Empowering NextGen Mobility via Large Action Model Infrastructure (LAMI): pav...
Empowering NextGen Mobility via Large Action Model Infrastructure (LAMI): pav...
Thierry Lestable
 
Knowledge engineering: from people to machines and back
Knowledge engineering: from people to machines and backKnowledge engineering: from people to machines and back
Knowledge engineering: from people to machines and back
Elena Simperl
 

Recently uploaded (20)

From Daily Decisions to Bottom Line: Connecting Product Work to Revenue by VP...
From Daily Decisions to Bottom Line: Connecting Product Work to Revenue by VP...From Daily Decisions to Bottom Line: Connecting Product Work to Revenue by VP...
From Daily Decisions to Bottom Line: Connecting Product Work to Revenue by VP...
 
LF Energy Webinar: Electrical Grid Modelling and Simulation Through PowSyBl -...
LF Energy Webinar: Electrical Grid Modelling and Simulation Through PowSyBl -...LF Energy Webinar: Electrical Grid Modelling and Simulation Through PowSyBl -...
LF Energy Webinar: Electrical Grid Modelling and Simulation Through PowSyBl -...
 
FIDO Alliance Osaka Seminar: Passkeys and the Road Ahead.pdf
FIDO Alliance Osaka Seminar: Passkeys and the Road Ahead.pdfFIDO Alliance Osaka Seminar: Passkeys and the Road Ahead.pdf
FIDO Alliance Osaka Seminar: Passkeys and the Road Ahead.pdf
 
When stars align: studies in data quality, knowledge graphs, and machine lear...
When stars align: studies in data quality, knowledge graphs, and machine lear...When stars align: studies in data quality, knowledge graphs, and machine lear...
When stars align: studies in data quality, knowledge graphs, and machine lear...
 
Accelerate your Kubernetes clusters with Varnish Caching
Accelerate your Kubernetes clusters with Varnish CachingAccelerate your Kubernetes clusters with Varnish Caching
Accelerate your Kubernetes clusters with Varnish Caching
 
GraphRAG is All You need? LLM & Knowledge Graph
GraphRAG is All You need? LLM & Knowledge GraphGraphRAG is All You need? LLM & Knowledge Graph
GraphRAG is All You need? LLM & Knowledge Graph
 
GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using Deplo...
GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using Deplo...GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using Deplo...
GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using Deplo...
 
Smart TV Buyer Insights Survey 2024 by 91mobiles.pdf
Smart TV Buyer Insights Survey 2024 by 91mobiles.pdfSmart TV Buyer Insights Survey 2024 by 91mobiles.pdf
Smart TV Buyer Insights Survey 2024 by 91mobiles.pdf
 
Unsubscribed: Combat Subscription Fatigue With a Membership Mentality by Head...
Unsubscribed: Combat Subscription Fatigue With a Membership Mentality by Head...Unsubscribed: Combat Subscription Fatigue With a Membership Mentality by Head...
Unsubscribed: Combat Subscription Fatigue With a Membership Mentality by Head...
 
Connector Corner: Automate dynamic content and events by pushing a button
Connector Corner: Automate dynamic content and events by pushing a buttonConnector Corner: Automate dynamic content and events by pushing a button
Connector Corner: Automate dynamic content and events by pushing a button
 
Designing Great Products: The Power of Design and Leadership by Chief Designe...
Designing Great Products: The Power of Design and Leadership by Chief Designe...Designing Great Products: The Power of Design and Leadership by Chief Designe...
Designing Great Products: The Power of Design and Leadership by Chief Designe...
 
State of ICS and IoT Cyber Threat Landscape Report 2024 preview
State of ICS and IoT Cyber Threat Landscape Report 2024 previewState of ICS and IoT Cyber Threat Landscape Report 2024 preview
State of ICS and IoT Cyber Threat Landscape Report 2024 preview
 
PCI PIN Basics Webinar from the Controlcase Team
PCI PIN Basics Webinar from the Controlcase TeamPCI PIN Basics Webinar from the Controlcase Team
PCI PIN Basics Webinar from the Controlcase Team
 
GenAISummit 2024 May 28 Sri Ambati Keynote: AGI Belongs to The Community in O...
GenAISummit 2024 May 28 Sri Ambati Keynote: AGI Belongs to The Community in O...GenAISummit 2024 May 28 Sri Ambati Keynote: AGI Belongs to The Community in O...
GenAISummit 2024 May 28 Sri Ambati Keynote: AGI Belongs to The Community in O...
 
UiPath Test Automation using UiPath Test Suite series, part 3
UiPath Test Automation using UiPath Test Suite series, part 3UiPath Test Automation using UiPath Test Suite series, part 3
UiPath Test Automation using UiPath Test Suite series, part 3
 
The Future of Platform Engineering
The Future of Platform EngineeringThe Future of Platform Engineering
The Future of Platform Engineering
 
Mission to Decommission: Importance of Decommissioning Products to Increase E...
Mission to Decommission: Importance of Decommissioning Products to Increase E...Mission to Decommission: Importance of Decommissioning Products to Increase E...
Mission to Decommission: Importance of Decommissioning Products to Increase E...
 
To Graph or Not to Graph Knowledge Graph Architectures and LLMs
To Graph or Not to Graph Knowledge Graph Architectures and LLMsTo Graph or Not to Graph Knowledge Graph Architectures and LLMs
To Graph or Not to Graph Knowledge Graph Architectures and LLMs
 
Empowering NextGen Mobility via Large Action Model Infrastructure (LAMI): pav...
Empowering NextGen Mobility via Large Action Model Infrastructure (LAMI): pav...Empowering NextGen Mobility via Large Action Model Infrastructure (LAMI): pav...
Empowering NextGen Mobility via Large Action Model Infrastructure (LAMI): pav...
 
Knowledge engineering: from people to machines and back
Knowledge engineering: from people to machines and backKnowledge engineering: from people to machines and back
Knowledge engineering: from people to machines and back
 

Logic gate tester for IC's ( Digital Electronics and Logic deisgn EE3114 )

  • 1. Date of Submission 23-Jan-2019 Course No: EE3200 Course Title: Electrical and Electronic Project Design Report on Logic Gate Tester for DELD EE3114 Submitted To Dr.Md.Habibullah AssistantProfessr Dept of EEE, KUET Submitted By Md. Jikrul Sayeed Hossain Roll: 1503048 Dept of EEE, KUET
  • 2. 1 Name of the project: Logic Gate Tester for DELD EE3114 1.1Abstract: Performing various types of logic operation we need to use logic gates and in integrated circuit there are more than one gates fabricated in a single IC. Before using gates for various purposes we need to check logic gates including all logic combination considering in Binary (Logic 1 & 0) needs to implement. It is a time consuming task to check all the input combinations, thus the sole purpose of this project to make it automatic to check all the logic . 1.2Objectives: i) To make an automatic system to check logic gates. ii) To Display every checking information including all logic combinations. iii) To learn about designing PCB & making it by hand.
  • 3. 2 1.3Introduction: Logic gates are the basic building blocks of any digital system. It is an electronic circuit having one or more than one input and only one output. The relationship between the input and the output is based on a certain logic. Based on this, logic gates are named as AND gate, OR gate, NOT gate, NAND gate, NOR gate, EXOR gate and EXNOR gate. AND Gate A circuit which performs an AND operation is shown in figure. It has n input (n >= 2) and one output. Logic diagram Truth Table OR Gate A circuit which performs an OR operation is shown in figure. It has n input (n >= 2) and one output. Logic diagram Truth Table
  • 4. 3 NOT Gate NOT gate is also known as Inverter. It has one input A and one output Y. Logic diagram Truth Table NAND Gate A NOT-AND operation is known as NAND operation. It has n input (n >= 2) and one output. Logic diagram Truth Table NOR Gate A NOT-OR operation is known as NOR operation. It has n input (n >= 2) and one output. Logic diagram Truth Table
  • 5. 4 XOR Gate XOR or Ex-OR gate is a special type of gate. It can be used in the half adder, full adder and subtractor. The exclusive-OR gate is abbreviated as EX-OR gate or sometime as X-OR gate. It has n input (n >= 2) and one output. Logic diagram Truth Table XNOR Gate XNOR gate is a special type of gate. It can be used in the half adder, full adder and subtractor. The exclusive-NOR gate is abbreviated as EX-NOR gate or sometime as X-NOR gate. It has n input (n >= 2) and one output. Logic diagram Truth Table In this project moreover we need to use power supply for constant supply. Which we use 7809 IC’s & an Arduino Mega is being used to implement logic conditions automatically. 12 LCD’s are being used to indicate the result to confirm which gate is Good & which one is Bad.
  • 6. 5 1.4Circuit Diagram: fig1: Main Circuit Diagram without Arduino Fig2: Main Circuit Diagram with Arduino MEGA
  • 7. 6 1.5PCB Diagram: Fig3: PCB Diagram Footer. 1.6WorkingPrinciple: As we know that High Voltage (+5VDC) as a logic HIGH or 1 and Low Voltage (0VDC) as a logic LOW or 0 is used in Binary Calculation. Here a Arduino Mega is used to set various DIGITAL PIN as HIGH(1) LOW(0) combination for 2 input get like HIGH HIGH , LOW HIGH , HIGH LOW , LOW LOW combinations. Then we use another PIN to read the output state of the Gate and compare the output with the predefined LOGIC table previously saved in the ARDUINO MEGA memory Unit. If the conditions matched (all combination) then we can call the Gate as good & the Green LED is being bright for corresponding gate in the IC. If any of the combinational output makes a false result after comparing with Truth Table then the gate will be declared as BAD gate and Red light is being bright for the corresponding number of Gate in the IC. This process is being set with the respective IC number which needs to give from the user interface keyboard & a display also shows the running logic that is being used to check to find out the logic gate as good or bad.
  • 8. 7 1.7Operating Principle: Plug IN to 220V line of Power suppy Put your IC on Zif Socket from left Enter you IC number Press “#” to Confirm IC number LCD will Show the Logic’s & LED will Show the gate’s Condition as Green is good & Red is Bad
  • 9. 8 1.8List of Permissible IC for the Project Prototype: (Table 1.1) IC Number Name Number of input Number of Gate 7400 2-input NAND 2 4 7402 2-input NOR 2 4 7404 NOT 1 6 7408 2-input AND 2 4 7432 2-input OR 2 4 7486 2-input EXOR 2 4 74286 2-input EXNOR 2 4 7411 3-input AND 3 3 1.9List & Cost of component: SL NO Name Rating Quantity Cost(tk) 1. Ardunio Mega2560 ATmega2560 microcontroller Input voltage - 7-12V 54 Digital I/O Pins (14 PWM outputs) 16 Analog Inputs 256k Flash Memory 16Mhz Clock Speed 01 850 2. 16*2 LCD Display Vdd -Vss (0-5VDC) Imax 3mA Duty 1/16 16*2 characters built-in 5*8 alpha numeric character ROM standard 4bit or 8bit parallel interface 01 180 3. 4*4 Key Pad Cable Length: 3.3 inch Keypad Width: 2.7 inch Keypad Length : 3.0inch Number of keys: 16 Matrix: 4×4 01 75 4. Zif socket (28 pin) (IC base) ZIF (zero insertion force) design 01 85
  • 10. 9 contacts: 28 lead pitch 0.1" (100 mil) an ideal IC test socket 5. LED (Green & Red) Vf= 1.90V Rated If=10mA 14 28 6. Registor 220ohm, 1k ; 0.5W 2 4 7. Variable Registor 10K 1 15 8. IC7809 Output Voltage:9V Peak Current:2.2A Short Circuit Current:250mA 1 15 9. Transformer (220/12V) Primary Voltage:220V Secondary Voltage:12V Current rating:1A 1 110 10. Plug 220V,10A 1 20 11. PCB Board 1 280 12. Jumper Male to male Male to female As required 20 13. Connector Copper (26G) As required 20 14. Test IC’s (Logic Gates) 7804,7808 As required 30 Total Cost: 1732tk 1.10Description of Circuit Component: [Pictorial View of Circuit Components] Arduino Mega R3 2560 16*2 LCD Display (LMB162ABC)
  • 11. 10 4*4 Key Pad Zif socket (28 pin) LED (RED) 10K (Potentiometer) IC7809 220/12V 1A step down transformer Fig4: Pictorial View of Used Circuit Component
  • 13. 12 Fig5: Practical view of circuit Implementation
  • 14. 13 1.12Conclusion: This is a project to check logic gates simply & automatically. The basic principle of checking gates is that every logic has an individual truth table and we set the truth table in memory when we call it through IC number it will check the truth table and give the result of the IC conditions. This project is designed to use in the Digital Electronics and Logic Design Laboratory (a course of EE3114) to make IC checking easily and reduce the time. 1.12Future Improvement: This project has a lot of possibilities as follows: 1) Adding 3 input IC’s 2) The circuit and code can be made more advanced to check other IC’s such as T, D, F flip-flop. 3) Some modified truth tables to compare any other complete circuits those are made by Logic Gates. 1.13 References i) Digital Logic and Computer Design by M. Morris Mano ii) www.en.wikipedia.org/wiki/Logic_gate