This document describes the design of an 8-bit reduced instruction set computer (RISC) processor using Verilog hardware description language. The processor uses a simple instruction set and includes components like a control unit, arithmetic logic unit, shift registers, and accumulator register. It is implemented using a Field Programmable Gate Array (FPGA) for applications like signal processing. The processor follows a three-stage pipeline of fetch, decode, and execute cycles. It was tested through simulation and achieved the goals of high performance and efficiency.