This document summarizes a laboratory experiment where a student designed and implemented digital circuits on an FPGA board to produce sequences of running lights. The student used components like counters, decoders, and logic gates to create circuits that caused LEDs on the board to light up in different patterns. Two circuits were made - one produced a running light sequence that changed direction when a button was pressed, and another made a "bouncing light" that switched directions when reaching the ends of the LED strip. The goal was to demonstrate an understanding of digital logic design and its application to producing specific outputs on an FPGA board.

1. Implementation of FPGA Devices with Digital Systems
Written By: Sachin Mehta
University of Nevada, Reno

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Abstract: This laboratory experiment—conducted over a two week period—provided an
understanding and insight into the basics of digital logic and/or VHDL, Verilog circuit design.
The circuits that were constructed used various bits of digital logic design, such as decoders,
counters, and logic gates in order to obtain a specific output of LED’s on the Spartan 3-E board.
The designs we used took into account the system clock specifically in order to provide the
counters with the proper clock impulses—which helped give us our desired output of a
sequence of running lights. The importance of comprehending and understand digital logic
couldn’t be overstated for this laboratory experiment.
Results: The first portion of this laboratory experiment was to use the Spartan 3E FPGA
XC3S500E, a Xilinx FPGA board, to design and implement a digital circuit. There were two
routes to go by in order to complete the circuit—one was to use a hardware description
language (such as VHDL) and the other was to use digital logic. We used digital logic in order to
make a circuit that implements a running light of the eight light emitting diodes (or LED’s) on
the Xilinx board. If you look closely at Fig. 1, you can see the LEDs on the lower right corner of
the board.
Figure 1: Xilinx Spartan 3-E FPGA Board
LEDs

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The circuit was constructed in the Integrated Synthesis Environment (ISE), where we could
input AND gates, decoders, clocks, and much more. In order to implement the sequence of
running lights we used various components, which allowed us to hone in on the exact circuit
that would give the desired output. Fig. 2 depicts the finished digital circuit for this portion of
the experiment.
Figure 2: Digital Circuit Schematic for Running LED’s
The circuit which we constructed used the following components: system clock, logic gates, a 3
to 8 decoder, various counters, and LED’s. In addition, it was important to input buffers
between the LED’s and the decoder, as well as between the switch and the logic gates. These
buffers were components that needed to be implemented since we were connecting a
‘symbolic’ component to a ‘board’ component.
Control of the onboard clock was a vital function that was required for the circuit to work
properly. The output of this clock, if left to a default, would essentially just keep the LED’s at a
‘1’ position—or ‘on’ position. This would result because the 3-E board systemclock has a
continuous 50 MHz run time and therefore, the lights would be constantly on and the circuit
useless. To alleviate this problem, we capitalized on the use of counters—which would serve to

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integrate the onboard clock to the remaining digital circuit which we had in place. Four
counters were used in total and each is discussed shortly as follows:
1) CB16CE
The CB16CE was a 16 bit counter that had its ‘clock enable’ input connected to the Vcc and its
‘clock’ input connected to the system clock. Doing this connection allows the clock to remain
permanently high, which then allows each pulse the clock makes to increment the counter that
is being controlled. This 16 bit counter has the following amount of pulses:
216 = 65,563
When these 65,563 pulses have occurred, the terminal count (TC) pin will go active—allowing
cascade to occur to the next counter of the circuit: the 8 bit counter. Table 1 below discusses
the component summary of the counter and pin active/low designations.
Table 1: CB16CE Counter Summary
2) CB8CE
The CB8CE counter is designed as an 8 bit component that has the ability to work similarly to
that of the 16 bit counter discussed above. Since we are working with 8 bits, the maximum
number of clock pulse is 28 or 256. After 256 pulses the period of the clock reduces to 0.336 s.
This calculation is shown next:
50 𝑀𝐻𝑧
216+8
=
50 𝑀𝐻𝑧
224
=
50 𝑀𝐻𝑧
16777216
= 2.98 𝐻𝑧
2.98 Hz = 0.336 seconds
A summary of the 8 bit counter used for the digital circuit designed is shown in Table 2.

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Table 2: 8 bit Counter Summary
3) CB4CE
The next portion of the circuit used two 4 bit counters. The output of the first counter is taken
at Q2 (Fig. 3) and has a maximum count of 23 = 8 pulses. The output count pulse of after the 16
bit, 8 bit and first 4 bit counter becomes: 216
× 28
× 24
= 134,217,728
This makes the clock input that arises at the second 4 bit counter:
50 𝑀𝐻𝑧
216+8+4
=
50 𝑀𝐻𝑧
228
=
50 𝑀𝐻𝑧
268435456
= 0.3725 𝐻𝑧
0.3725 Hz = 2.684 seconds
Figure 3: CB4CE Counter Pin-out
A summary of the 4 bit counter is shown below in Table 3.

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Table 3: CB4CE Counter Summary
4) CB4CE
The second 4 bit counter is essentially the connection between the logic gates of the circuit and
all of the counters. Looking at Fig. 3, once Q0 – Q2 go high, they make a ‘high’ logic to all of the
AND2B1 gates (the six gates in Fig. 2).
The digital circuit that we designed uses double input AND2B1 gates with one inverted input
and one non-inverted input in order to provide the interface between the switch and the
output (Q0-Q2) of the second 4 bit counter, discussed above, and the three logic OR gates.
The schematic in Fig. 2 shows that the each of the Q0-Q2 outputs are fed to the following AND
terminals: the non-inverting input of one AND gate and the respective inverting terminal of its
neighboring AND gate. This allows the switch of the circuit to connect to the inverting input of
the former and the non-inverting input of the latter. Both the switch and the Q0-Q2 4 bit
counter outputs makes a combination that comprise a pair of AND gates. In order to construct
this design we made use of contemporary digital logic design and applied truth tables, which
show that the state of an AND gate pair, given an input from the second 4 bit counter’s Qx
terminal and the circuit switch. Table 4 discusses the truth table for an AND gate pair. The table
has a shaded region that clearly shows the state of the first two AND gates given the state of
the output Q0 from the second 4 bit counter and the state of the switch.

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Table 4: AND Gate Pair Truth Table
Note that the remaining AND gates use the same logic as shown above.
The next portion of the circuit is the connection of the AND gates to the OR gates. The OR gate
triplet takes in and input of logic from the three pairs of AND gates. We have to remember that
the only output available in logic is a 1 or 0. The three OR gates make up the combinations that
make up the inputs to the 3-to-8 decoder. The truth table depicted in Table 5 shows the output
of the OR gates.
Table 5: Truth Table for OR Gate Logic
Discussion of the 3-to-8 decoder follows next. This decoder has inputs accepted at the pins A0-
A2 that are from the OR gate triplet. The respective LED will be selected and turned depending
upon the binary input to the 3-to-8 decoder. These outputs are discussed and shown in Table
6.

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Table 6: 3-to-8 Decoder Truth Table
Part 6 of this laboratory experiment was the simple implementation of the circuit designed
discussed above. Two different designs were required:
1) Simply the running light sequence that moves in one direction and changes direction when a
button was pressed.
This design was discussed throughout the earlier parts of this lab report, and responded to a
button press of L13. This means that once the circuit starts running, pressing this button will
make the lights light up in the opposite direction (right to left -- left to right)
2) A bouncing light that changes direction when it reaches the last LED on both ends of the LED
bar.
The figure below (Fig. 4) shows this second design circuit schematic. Note, how the digital
circuit design is essentially the same as the first design, but by replacing the switch with the
second 4 bit counter output Q3.

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Figure 4: Second Design Circuit Schematic
Summary
This laboratory experiment used the properties of digital logic in order to obtain a desired
circuit and output. Operating the FPGA board became somewhat complicated when pins
needed to be chosen in the implementation on the physical board. However, the design of the
two circuits relied solely upon digital logic and binary. Knowing this was critical for complete
design specifications, and all details lain out prior in this report discuss what component was
used and why that component was used. This laboratory experiment differed from the others
that we have completed in that, again, digital logic was used—and not simple electrical circuit
laws like Kirchoff’s Voltage or Current Law. All in all, this laboratory experiment tested our
ability to comprehend and analyze logic design to obtain a desired output—like running LED’s
on the Spartan 3-E FPGA board.