This document describes two different models for a full adder circuit - a dataflow model and a gate level model. The dataflow model uses assign statements to directly define the sum (s) and carry out (cout) outputs in terms of the inputs (a, b, cin). The gate level model builds the full adder using lower level logic gates like xor, and, or connected via internal wires to compute the sum and carry outputs.

1. Full Adder in Dataflow model:
Code:
module fulladder(
input a,
input b,
input cin,
output s,
output cout
);
assign s=a^b^cin;
assign cout=(a & b) | cin & (a ^ b);
endmodule
Output:

2. RTL Schematic:

3. Hardware:

5. Full Adder in Gate level model :
Code:
module fa(
input a,
input b,
input cin,
output s,
output cout
);
wire x1,x2,x3;
xor(x1,a,b);
and(x3,a,b);
xor(s,x1,cin);
and(x2,x1,cin);
or(cout,x2,x3);
endmodule
Output:

6. RTL Schematic: