The Pentium processor introduced in 1993 features a superscalar architecture that allows multiple instructions to be executed simultaneously. It has separate 8KB instruction and data caches and a 64-bit data bus. The Pentium uses dynamic branch prediction and out-of-order execution to further improve performance through superscalar design.
The document describes the architecture of the Pentium family processor. It discusses the Pentium processor's architecture including its 64-bit data bus, separate code and data caches, pipeline sequence, and superscalar execution using two pipelines. It also describes the Pentium's registers including the general purpose, segment, debug, and EFlags registers. Finally, it discusses the Pentium's bus description including the address bus, data bus, control bus, byte enables, and bus cycles.
The document describes the 8 addressing modes of the 8086 microprocessor. These are: 1) Immediate, where the operand is specified in the instruction itself. 2) Register, where operands are registers. 3) Direct memory, using a segment and offset address. 4) Register indirect, using a base register address. 5) Register relative, using a base register and displacement. 6) Base indexed, using a base and index register. 7) Relative indexed, using a base, index, and displacement. 8) Implied, where operands are implied and not specified.
General register organization (computer organization)rishi ram khanal
This document discusses the organization of a CPU and its registers. It includes tables that encode the register selection fields and ALU operations. It also provides examples of micro-operations for the CPU, showing the register selections, ALU operations, and control words. Key registers discussed include the accumulator, instruction register, address register, and program counter.
The document describes the Intel 8086 microprocessor, which was launched in 1978 as the first 16-bit microprocessor. It had major improvements over the 8085 microprocessor, with higher execution speeds. The 8086 had a 16-bit data bus, 20-bit address bus, and could address up to 1MB of memory. It included features like multiplication and division support. The document provides detailed information on the various pins and signals of the 8086 microprocessor.
This document provides an overview of interrupts in the 8086 microprocessor. It defines an interrupt as an event that breaks the normal execution sequence of a program to run an interrupt service routine. The 8086 can be interrupted by hardware interrupts from external devices, software interrupts using the INT instruction, or internal exceptions. Hardware interrupts are further divided into maskable interrupts, which can be enabled or disabled, and non-maskable interrupts, which must always be serviced. Software interrupts allow programs to define their own interrupt handlers. The 8086 supports 256 different software interrupt types.
The 8086 microprocessor has an architecture that separates it into a Bus Interface Unit (BIU) and Execution Unit (EU). The BIU fetches instructions and data from memory and handles address calculation on the buses. The EU decodes and executes instructions using its 16-bit ALU. The 8086 has 16 general purpose registers including 4 data registers (AX, BX, CX, DX) and segment/pointer registers. It also contains a flag register for storing status flags. The 8086 can queue up to 6 bytes of upcoming instructions to improve performance.
The document describes the architecture of the Pentium family processor. It discusses the Pentium processor's architecture including its 64-bit data bus, separate code and data caches, pipeline sequence, and superscalar execution using two pipelines. It also describes the Pentium's registers including the general purpose, segment, debug, and EFlags registers. Finally, it discusses the Pentium's bus description including the address bus, data bus, control bus, byte enables, and bus cycles.
The document describes the 8 addressing modes of the 8086 microprocessor. These are: 1) Immediate, where the operand is specified in the instruction itself. 2) Register, where operands are registers. 3) Direct memory, using a segment and offset address. 4) Register indirect, using a base register address. 5) Register relative, using a base register and displacement. 6) Base indexed, using a base and index register. 7) Relative indexed, using a base, index, and displacement. 8) Implied, where operands are implied and not specified.
General register organization (computer organization)rishi ram khanal
This document discusses the organization of a CPU and its registers. It includes tables that encode the register selection fields and ALU operations. It also provides examples of micro-operations for the CPU, showing the register selections, ALU operations, and control words. Key registers discussed include the accumulator, instruction register, address register, and program counter.
The document describes the Intel 8086 microprocessor, which was launched in 1978 as the first 16-bit microprocessor. It had major improvements over the 8085 microprocessor, with higher execution speeds. The 8086 had a 16-bit data bus, 20-bit address bus, and could address up to 1MB of memory. It included features like multiplication and division support. The document provides detailed information on the various pins and signals of the 8086 microprocessor.
This document provides an overview of interrupts in the 8086 microprocessor. It defines an interrupt as an event that breaks the normal execution sequence of a program to run an interrupt service routine. The 8086 can be interrupted by hardware interrupts from external devices, software interrupts using the INT instruction, or internal exceptions. Hardware interrupts are further divided into maskable interrupts, which can be enabled or disabled, and non-maskable interrupts, which must always be serviced. Software interrupts allow programs to define their own interrupt handlers. The 8086 supports 256 different software interrupt types.
The 8086 microprocessor has an architecture that separates it into a Bus Interface Unit (BIU) and Execution Unit (EU). The BIU fetches instructions and data from memory and handles address calculation on the buses. The EU decodes and executes instructions using its 16-bit ALU. The 8086 has 16 general purpose registers including 4 data registers (AX, BX, CX, DX) and segment/pointer registers. It also contains a flag register for storing status flags. The 8086 can queue up to 6 bytes of upcoming instructions to improve performance.
The document discusses processor organization and architecture. It covers the Von Neumann model, which stores both program instructions and data in the same memory. The Institute for Advanced Study (IAS) computer is described as the first stored-program computer, designed by John von Neumann to overcome limitations of previous computers like the ENIAC. The document also covers the Harvard architecture, instruction formats, register organization including general purpose, address, and status registers, and issues in instruction format design like instruction length and allocation of bits.
The 80486 microprocessor features an integrated math coprocessor that is 3 times faster than the 80386/387 combination. It has an 8KB internal code and data cache and uses a 168-pin PGA package. New signals support burst mode memory access and bus sharing. The 80486 includes parity checking/generation and additional page table entry bits control internal caching.
The Intel 8086 is a 16-bit microprocessor that can access up to 1 MB of memory. It has two main components: the Bus Interface Unit (BIU) handles bus operations like instruction fetching and memory access, while the Execution Unit (EU) decodes and executes instructions. The BIU contains registers for the code, data, extra, and stack segments as well as an instruction queue. The EU has registers for accumulation, base, count, data, pointers, and flags, and contains an ALU and decoder. It executes instructions from the queued bytes using a pipeline architecture.
The document describes the internal architecture of the 8086 microprocessor. It has two main blocks: the Bus Interface Unit (BIU) and Execution Unit (EU). The BIU handles fetching instructions and data from memory and I/O, while the EU decodes and executes instructions. The 8086 uses general purpose registers like AX, BX, CX, DX as well as segment registers, pointers, and a flag register to control operations and store temporary data as it executes instructions.
This document provides an overview of input/output interfaces in 3 paragraphs. It discusses how I/O devices communicate differently than internal storage due to differences in operation, data transfer rates, word formats, and peripheral operating modes. It describes how interface modules connect I/O devices like keyboards, displays, printers and storage to the I/O bus and processor. Finally, it provides an example of an I/O interface unit that uses control and status registers to facilitate communication between a CPU and I/O device over control, data and status lines.
The document discusses the Intel 80486 microprocessor. Some key points:
1) The 80486 is an evolutionary step up from the 80386, integrating the math coprocessor on the chip for faster performance.
2) It has an 8KB internal code and data cache, a floating point unit, and 168 pins in a pin grid array package.
3) The architecture includes address and data buses, cache control signals, and status flags in registers like the 80386. It supports protected mode with virtual memory and multitasking capabilities.
The document discusses the architecture of the Intel 8085 microprocessor. It describes the 8085 as an 8-bit microprocessor introduced in 1976 that uses a single +5 volt power supply. The internal architecture includes a control unit, arithmetic logic unit (ALU), registers including the accumulator, program counter, stack pointer, instruction register/decoder, and timing and control unit. The document also briefly discusses interrupts, serial I/O, and some applications of microprocessors like mobile phones, watches, and appliances.
The document discusses memory segmentation in the Intel 8086 processor. It explains that the 8086's 1MB of memory is divided into segments of varying sizes, including code, data, stack, and extra segments. Each segment is addressed by a 16-bit segment register that stores the segment's base address. To generate the full 20-bit physical address, the base address is combined with a 16-bit offset value contained in registers like IP, BX, DI, SI, and SP. This allows each segment to be up to 64KB in size. Examples are provided to demonstrate how logical addresses are translated to physical memory locations using the segment registers and offsets.
8086 Microprocessor is an enhanced version of 8085 Microprocessor that was designed by Intel in 1976. It is a 16-bit Microprocessor having 20 address lines and 16 data lines that provides up to 1MB storage. In April 1978, intel introduced this microprocessor and it was officially released on June 8.
The document discusses the Intel 80286 microprocessor. It was introduced in 1982 as the 5th generation of Intel's x86 family. It had several improvements over the 8086 including a faster clock speed of 12.5MHz, more transistors at 125K, and an advanced memory management system. The 80286 could address up to 16MB of memory and had two operating modes: real address mode for compatibility and protected virtual address mode for multitasking. It also introduced the ability to use virtual memory in protected mode.
The document discusses the 8088 microprocessor hardware configuration. It describes the 8088 chip, which contains the microprocessing unit (MPU), and external memory. The 8088 has three buses - control bus, data bus with 8 lines, and address bus with 20 lines. This allows it to access up to 1,048,576 memory locations, with each location being 8 bits. The document then provides an example assembly language program to initialize memory location 00002 with the value 3F. It explains that memory segmentation is used to access memory locations beyond 0000-FFFF, through the use of segment registers like DS which specify the memory segment.
This document discusses floating point arithmetic operations including:
- The components of a floating point number including the mantissa and exponent.
- Normalization of floating point numbers to have a leading nonzero digit in the mantissa.
- Common floating point operations like addition, subtraction, multiplication, and division and how they are performed.
- The IEEE 754 standard for representing floating point numbers.
- How floating point arithmetic is implemented in hardware including registers and adders used to process mantissas and exponents.
The 8086 instruction set includes 8 categories of instructions: data transfer, arithmetic, branch, loop, machine control, flag manipulation, shift/rotate, and string instructions. Some key instructions include MOV for data transfer, PUSH/POP for stack operations, ADD/SUB for arithmetic, JMP for branching, LOOP for looping, and SHIFT/ROTATE for bitwise operations.
The x86 instruction set architecture began with Intel's 16-bit processors in the 1980s and has since evolved through numerous extensions. It supports multiple execution modes including 16-bit real mode, 32-bit protected mode, and 64-bit long mode. The instruction format includes optional prefixes, opcode bytes, addressing fields, and immediate data. General purpose registers are used for operands along with memory addressing modes. Subsequent x86 architectures, such as AMD64, expanded register sizes and added new instructions while maintaining backwards compatibility.
The document describes the instruction formats of the 8086 microprocessor. It has 1-6 byte instruction sizes with an opcode field in the first byte. The second byte contains mode, register, and register/memory fields that specify operands. It defines register codes and explains how the mode, register, and register/memory fields are used to determine operands and effective addresses. Examples show how to encode instructions like MOV, SUB, and ADD using the instruction format. Input/output instructions like IN and OUT are also described, indicating how port numbers can be immediate values or specified with the DX register.
The document discusses the accumulator register in a CPU. It describes the accumulator as a short-term storage register for arithmetic and logic operations. It contains details about the inputs and outputs to the accumulator from other registers like the data register and input register. It also explains the different microoperations that can be performed on the accumulator like addition, transfer, complement, and shift operations. The control gates for these microoperations are also defined.
The document provides information on the 8086 microprocessor, including:
- It was designed by Intel in the late 1970s and was used in early PCs.
- It has a 16-bit architecture and 20-bit address bus, allowing access to 1MB of memory.
- The 8086 CPU logic is partitioned into a Bus Interface Unit and Execution Unit, with the BIU handling bus operations and the EU executing instructions.
- The BIU generates physical addresses from logical addresses using segment registers and the instruction pointer. It also contains an instruction queue and registers.
- The EU contains general purpose registers, flags, and an ALU for arithmetic and logical operations.
The 80386 microprocessor was introduced by Intel in 1985. It had a 32-bit data bus and 32-bit address bus, allowing it to access up to 4GB of memory. It improved on the 80286 by including a memory management unit and paging capabilities. The 80386 operated in real, protected, and virtual modes and could address memory using various addressing modes including scaled indexed addressing. It had enhanced 32-bit registers and introduced debugging features like breakpoints using debug registers. Paging divided memory into fixed-size pages allowing more efficient memory management for multitasking systems.
The document provides an overview of the evolution of Intel processors from early 16-bit processors like the 8086 and 8088 through to the Pentium processor. It describes the key features and architectural changes introduced at each generation, including protected mode and segmentation in the 286, 32-bit registers and virtual memory support in the 386, pipelining and caching in the 486, and superscalar processing and branch prediction in the Pentium.
The document discusses processor organization and architecture. It covers the Von Neumann model, which stores both program instructions and data in the same memory. The Institute for Advanced Study (IAS) computer is described as the first stored-program computer, designed by John von Neumann to overcome limitations of previous computers like the ENIAC. The document also covers the Harvard architecture, instruction formats, register organization including general purpose, address, and status registers, and issues in instruction format design like instruction length and allocation of bits.
The 80486 microprocessor features an integrated math coprocessor that is 3 times faster than the 80386/387 combination. It has an 8KB internal code and data cache and uses a 168-pin PGA package. New signals support burst mode memory access and bus sharing. The 80486 includes parity checking/generation and additional page table entry bits control internal caching.
The Intel 8086 is a 16-bit microprocessor that can access up to 1 MB of memory. It has two main components: the Bus Interface Unit (BIU) handles bus operations like instruction fetching and memory access, while the Execution Unit (EU) decodes and executes instructions. The BIU contains registers for the code, data, extra, and stack segments as well as an instruction queue. The EU has registers for accumulation, base, count, data, pointers, and flags, and contains an ALU and decoder. It executes instructions from the queued bytes using a pipeline architecture.
The document describes the internal architecture of the 8086 microprocessor. It has two main blocks: the Bus Interface Unit (BIU) and Execution Unit (EU). The BIU handles fetching instructions and data from memory and I/O, while the EU decodes and executes instructions. The 8086 uses general purpose registers like AX, BX, CX, DX as well as segment registers, pointers, and a flag register to control operations and store temporary data as it executes instructions.
This document provides an overview of input/output interfaces in 3 paragraphs. It discusses how I/O devices communicate differently than internal storage due to differences in operation, data transfer rates, word formats, and peripheral operating modes. It describes how interface modules connect I/O devices like keyboards, displays, printers and storage to the I/O bus and processor. Finally, it provides an example of an I/O interface unit that uses control and status registers to facilitate communication between a CPU and I/O device over control, data and status lines.
The document discusses the Intel 80486 microprocessor. Some key points:
1) The 80486 is an evolutionary step up from the 80386, integrating the math coprocessor on the chip for faster performance.
2) It has an 8KB internal code and data cache, a floating point unit, and 168 pins in a pin grid array package.
3) The architecture includes address and data buses, cache control signals, and status flags in registers like the 80386. It supports protected mode with virtual memory and multitasking capabilities.
The document discusses the architecture of the Intel 8085 microprocessor. It describes the 8085 as an 8-bit microprocessor introduced in 1976 that uses a single +5 volt power supply. The internal architecture includes a control unit, arithmetic logic unit (ALU), registers including the accumulator, program counter, stack pointer, instruction register/decoder, and timing and control unit. The document also briefly discusses interrupts, serial I/O, and some applications of microprocessors like mobile phones, watches, and appliances.
The document discusses memory segmentation in the Intel 8086 processor. It explains that the 8086's 1MB of memory is divided into segments of varying sizes, including code, data, stack, and extra segments. Each segment is addressed by a 16-bit segment register that stores the segment's base address. To generate the full 20-bit physical address, the base address is combined with a 16-bit offset value contained in registers like IP, BX, DI, SI, and SP. This allows each segment to be up to 64KB in size. Examples are provided to demonstrate how logical addresses are translated to physical memory locations using the segment registers and offsets.
8086 Microprocessor is an enhanced version of 8085 Microprocessor that was designed by Intel in 1976. It is a 16-bit Microprocessor having 20 address lines and 16 data lines that provides up to 1MB storage. In April 1978, intel introduced this microprocessor and it was officially released on June 8.
The document discusses the Intel 80286 microprocessor. It was introduced in 1982 as the 5th generation of Intel's x86 family. It had several improvements over the 8086 including a faster clock speed of 12.5MHz, more transistors at 125K, and an advanced memory management system. The 80286 could address up to 16MB of memory and had two operating modes: real address mode for compatibility and protected virtual address mode for multitasking. It also introduced the ability to use virtual memory in protected mode.
The document discusses the 8088 microprocessor hardware configuration. It describes the 8088 chip, which contains the microprocessing unit (MPU), and external memory. The 8088 has three buses - control bus, data bus with 8 lines, and address bus with 20 lines. This allows it to access up to 1,048,576 memory locations, with each location being 8 bits. The document then provides an example assembly language program to initialize memory location 00002 with the value 3F. It explains that memory segmentation is used to access memory locations beyond 0000-FFFF, through the use of segment registers like DS which specify the memory segment.
This document discusses floating point arithmetic operations including:
- The components of a floating point number including the mantissa and exponent.
- Normalization of floating point numbers to have a leading nonzero digit in the mantissa.
- Common floating point operations like addition, subtraction, multiplication, and division and how they are performed.
- The IEEE 754 standard for representing floating point numbers.
- How floating point arithmetic is implemented in hardware including registers and adders used to process mantissas and exponents.
The 8086 instruction set includes 8 categories of instructions: data transfer, arithmetic, branch, loop, machine control, flag manipulation, shift/rotate, and string instructions. Some key instructions include MOV for data transfer, PUSH/POP for stack operations, ADD/SUB for arithmetic, JMP for branching, LOOP for looping, and SHIFT/ROTATE for bitwise operations.
The x86 instruction set architecture began with Intel's 16-bit processors in the 1980s and has since evolved through numerous extensions. It supports multiple execution modes including 16-bit real mode, 32-bit protected mode, and 64-bit long mode. The instruction format includes optional prefixes, opcode bytes, addressing fields, and immediate data. General purpose registers are used for operands along with memory addressing modes. Subsequent x86 architectures, such as AMD64, expanded register sizes and added new instructions while maintaining backwards compatibility.
The document describes the instruction formats of the 8086 microprocessor. It has 1-6 byte instruction sizes with an opcode field in the first byte. The second byte contains mode, register, and register/memory fields that specify operands. It defines register codes and explains how the mode, register, and register/memory fields are used to determine operands and effective addresses. Examples show how to encode instructions like MOV, SUB, and ADD using the instruction format. Input/output instructions like IN and OUT are also described, indicating how port numbers can be immediate values or specified with the DX register.
The document discusses the accumulator register in a CPU. It describes the accumulator as a short-term storage register for arithmetic and logic operations. It contains details about the inputs and outputs to the accumulator from other registers like the data register and input register. It also explains the different microoperations that can be performed on the accumulator like addition, transfer, complement, and shift operations. The control gates for these microoperations are also defined.
The document provides information on the 8086 microprocessor, including:
- It was designed by Intel in the late 1970s and was used in early PCs.
- It has a 16-bit architecture and 20-bit address bus, allowing access to 1MB of memory.
- The 8086 CPU logic is partitioned into a Bus Interface Unit and Execution Unit, with the BIU handling bus operations and the EU executing instructions.
- The BIU generates physical addresses from logical addresses using segment registers and the instruction pointer. It also contains an instruction queue and registers.
- The EU contains general purpose registers, flags, and an ALU for arithmetic and logical operations.
The 80386 microprocessor was introduced by Intel in 1985. It had a 32-bit data bus and 32-bit address bus, allowing it to access up to 4GB of memory. It improved on the 80286 by including a memory management unit and paging capabilities. The 80386 operated in real, protected, and virtual modes and could address memory using various addressing modes including scaled indexed addressing. It had enhanced 32-bit registers and introduced debugging features like breakpoints using debug registers. Paging divided memory into fixed-size pages allowing more efficient memory management for multitasking systems.
The document provides an overview of the evolution of Intel processors from early 16-bit processors like the 8086 and 8088 through to the Pentium processor. It describes the key features and architectural changes introduced at each generation, including protected mode and segmentation in the 286, 32-bit registers and virtual memory support in the 386, pipelining and caching in the 486, and superscalar processing and branch prediction in the Pentium.
Comparison of pentium processor with 80386 and 80486Tech_MX
The document compares the 80386, 80486, and Pentium processors. It discusses the limitations of the 80286 that led to the development of the 80386, which was a 32-bit processor that could address over 4GB of memory. The 80486 provided improvements like an 8KB cache and integrated floating point unit. The Pentium provided further enhancements such as separate 8KB instruction and data caches, dual integer pipelines, and branch prediction logic. It also introduced the 64-bit memory system. These changes helped significantly increase the processing power and speed of successive processor generations.
The 80386 microprocessor had two main versions - the 80386DX with a 32-bit address and data bus, and the 80386SX with a 24-bit address bus and 16-bit data bus. The 80386SX was developed later for applications that did not require the full 32-bit capabilities of the 80386DX. The 80386 supported protected mode which enabled virtual memory, paging, and memory protection in addition to the capabilities of the 80286. It had enhanced registers, addressing modes, and memory management compared to earlier Intel processors.
The document discusses the history and specifications of Intel Pentium processors from 1993 to the present. It describes the original Pentium processor and subsequent models including the Pentium II, Pentium III, and Pentium IV. It also discusses dual-core and Core 2 Duo processors, and provides details on the different Intel Core i3, i5, and i7 processors.
The Pentium III was a desktop and mobile CPU produced by Intel between 1999-2003. It had clock speeds between 400 MHz to 1.4 GHz and included features like MMX and SSE instructions. There were several stepping of the Pentium III including Katmai at 0.25 μm, Coppermine at 0.18 μm, Coppermine T at 0.18 μm, and Tualatin at 0.13 μm. Each stepping improved performance through higher clock speeds, larger caches, and support for newer instruction sets. Optimizing code for the Pentium III microarchitecture required techniques like scheduling instructions to maximize decoder throughput, balancing usage of execution units, and minimizing register dependencies. The Pentium III was also notable for including
The 80386 introduced 32-bit processing to the 8086 family, improving performance. It had multiple internal units that operated in parallel. The 80386 came in several versions, including the full 80386DX and reduced bus 80386SX. In protected mode, the 80386 supported virtual memory, multitasking, and memory protection through descriptor tables, paging, and privilege levels. New features like control registers and the task register enabled these protected mode capabilities.
The 80386 microprocessor was Intel's 32-bit processor introduced in 1985. It had several improvements over the 80286 including a 32-bit external data bus, increased virtual memory support up to 4GB using segmentation and paging, and faster instruction execution via parallel pipelining. The 80386 came in two versions - the 80386DX with a full 32-bit external data bus, and the lower-cost 80386SX which had a 16-bit data bus. It found use in personal computers and some embedded applications like early mobile phones and spacecraft due to its power and multitasking capabilities.
The document summarizes the key features and specifications of the Intel Core 2 Duo processor. It is a 64-bit dual-core processor introduced in 2006 as the successor to the Core Duo. Each of its cores are based on the Pentium M microarchitecture and have shorter pipelines, allowing for higher performance at lower clock speeds compared to previous architectures like the Pentium 4. The Core 2 Duo comes in desktop and notebook versions with performance about 20% lower in notebooks due to lower voltages and bus speeds.
The document provides details about the Pentium II processor, including that it is part of the P6 family of processors and utilizes Intel's MMX technology. It has multiple low power states for energy efficiency and utilizes a multi-processing system bus like the Pentium Pro. The processor uses a 12-stage pipeline and superscalar architecture to achieve high clock rates. It has an L2 cache in a Single Edge Contact cartridge packaging and uses the same dynamic execution microarchitecture as other P6 family processors.
The document discusses the architecture of the Intel 80386 microprocessor, including its salient features such as supporting 32-bit data and addressing as well as virtual memory capabilities. It describes the functional blocks of the 80386 including the central processing unit, memory management unit, and bus control unit. Details are provided on the pin layout and specifications of the 80386 as compared to the earlier 8086 processor.
The Pentium Pro was a sixth generation x86 microprocessor introduced by Intel on November 1, 1995. It contained 5.5 million transistors and had an 8KB + 8KB L1 cache and 256KB, 512KB, or 1024KB L2 cache clocked at CPU speed. The Pentium Pro had a Socket 8 connection and used a 60-66MHz front side bus with a 3.1-3.3V core and was fabricated at 0.50 or 0.35 microns, clocking at 150-200MHz.
8259 Programmable Interrupt Controller by vijayVijay Kumar
The 8259A Programmable Interrupt Controller (PIC) is used to simplify the interrupt interface of 8088/8086 microprocessor systems. It can accept up to 8 interrupt requests and expand to 64 requests by cascading additional PICs. The PIC is programmable through initialization command words to configure operating modes and interrupt vector assignments. It also has operation command words to control interrupt masking, priorities, and acknowledgement.
The 8086 microprocessor is a 16-bit processor with a 20-bit address bus that can access up to 1MB of memory. It has 14 general purpose 16-bit registers and operates in minimum and maximum modes. In minimum mode, the 8086 provides all control signals for memory and I/O interfacing, including address/data bus lines, status lines, and control signals to indicate read/write operations and memory versus I/O access.
The document discusses interrupts in computing systems. It defines an interrupt as either a hardware-generated call from an external signal or a software-generated call from an instruction. The main purposes of interrupts are to halt normal program execution and divert processing to an interrupt service routine in response to external events. It then provides details on different types of interrupts, including hardware interrupts from devices and software interrupts from instructions. It lists and describes the most common interrupt types and their associated vector numbers.
The document summarizes the history and architecture of Intel Pentium processors. It discusses the evolution from early 4-bit and 8-bit processors to later 32-bit processors including Pentium, Pentium Pro, and Pentium II. It describes the Pentium architecture including registers, protected mode with segmentation and paging for address translation, and real mode with segmented memory. Protected mode supports 32-bit addressing while real mode uses 16-bit segments. Mixed mode operation allows combining 16-bit and 32-bit code.
The document provides an overview of the evolution of Intel processors from early 16-bit processors like the 8086 and 8088 through to the Pentium processor. It describes the key features and architectural changes introduced at each generation, including protected mode and segmentation in the 286, 32-bit registers and virtual memory support in the 386, pipelining and caching in the 486, and superscalar processing and branch prediction in the Pentium.
Evolution of microprocessors and 80486 Microprocessor.Ritwik MG
The document discusses the evolution of Intel x86 microprocessors from 80186 to 80486. It describes the key features and improvements introduced in each generation, including additional instructions, memory management capabilities, and on-chip cache in 80486. The 80486 is a 32-bit processor compatible with 80386 with enhanced performance due to its highly integrated design and 8KB internal cache. It has the same 4GB memory address space and register set as 80386 but provides faster execution through fewer clock cycles and additional instructions.
The 8086 architecture introduced Intel's first 16-bit microprocessor. It uses a 40-pin IC with an n-channel depletion mode silicon gate technology. The CPU logic is divided into an Execution Unit and Bus Interface Unit. The BIU interfaces with the external bus and executes bus operations, fetching instructions from memory and passing them to the EU. The EU then executes the instructions, manipulating registers and flags. The 8086 has 14 registers including data, segment, pointer, index, program counter, and flag registers.
VTU 4TH SEM CSE MICROPROCESSORS SOLVED PAPERS OF JUNE-2014 & JUNE-2015vtunotesbysree
The document provides information about solved question papers for various competitive exams in computer science that can be found at a given URL. It then provides the answers to three questions from a microprocessors exam, including defining a microprocessor and explaining the programming model of the 8086 through Core 2 microprocessors. It also explains the internal architecture of the 8086 microprocessor and various bits of the flag register for the 8086.
8085 Microprocessor Architecture for beginners.It explains the Instruction Register(IR),Instruction Decoder, Address buffer register,Address data buffer,program execution,Serial I/O control etc.
The document describes the architecture of the 8085 microprocessor. It includes 8-bit registers like the accumulator and register sets that store data and perform arithmetic/logical operations. It has a 16-bit program counter that points to the next instruction and a stack pointer that manages subroutine calls. There is a flag register that stores status flags updated by operations. Other components are an ALU, instruction decoder, address/data buffers, and interrupt and I/O controls.
The Z80 CPU was first released in 1976 by Zilog. It has 16 pins for address and data buses, as well as pins for control signals like READ, WRITE, and INTERRUPT. The Z80 uses 8-bit bytes of memory addressed by 16-bit addresses, for a maximum of 64KB. It has registers like the accumulator, program counter, stack pointer, and flag register. The ALU performs arithmetic and logical operations. The Z80 supports 158 instruction types across various addressing modes like immediate, register, and indexed addressing.
The document discusses the architecture and features of the Intel 80386 16-bit microprocessor. It describes the key components of the 80386 including the central processing unit with execution and instruction units, memory management unit, and bus interface unit. It also summarizes the 80386's addressing modes, registers, memory management, and real address mode of operation.
A microcontroller is a small computer on a single integrated circuit containing a processor core, memory, and programmable input/output peripherals. It is used in embedded systems to make decisions. The AVR ATmega8 is an 8-bit microcontroller based on Harvard architecture. It has 8KB of flash memory, 512B of EEPROM, and 1KB of SRAM. It contains peripherals like timers, PWM channels, ADC, and serial interfaces. The ATmega8 comes in PDIP and TQFP packages and uses three registers - DDRx, PORTx, and PINx - to communicate with its I/O ports.
The 8086 is a 16-bit microprocessor introduced by Intel in 1978. It has a 16-bit external data bus and 20-bit address bus, can access up to 1 MB of memory, and has 14 general purpose 16-bit registers. The 8086 architecture consists of a Bus Interface Unit which handles memory access and I/O, and an Execution Unit which decodes and executes instructions. It supports two operating modes - minimum and maximum - which determine clock speed and timing.
The document discusses the architecture and features of the 16-bit Intel 80386 microprocessor. It describes the internal architecture including the central processing unit, memory management unit, and bus interface unit. The memory management unit uses segmentation and paging to translate virtual to physical addresses. The document provides details on the registers, addressing modes, operation in real and protected modes, and paging mechanism of the 80386 microprocessor.
The document provides information about training performed on the AVR microcontroller. It discusses the features of the ATmega8 microcontroller including its architecture, memory, I/O ports, and peripherals. It also describes tasks performed during training such as interfacing LEDs, buttons, keypads, displays, ADC, and DC motors to learn about digital I/O, serial communication, and analog input.
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2. Features of Pentium
• Introduced in 1993 with clock frequency ranging
from 60 to 66 MHz
• The primary changes in Pentium Processor were:
– Superscalar Architecture
– Dynamic Branch Prediction
– Pipelined Floating-Point Unit
– Separate 8K Code and Data Caches
– Writeback MESI Protocol in the Data Cache
– 64-Bit Data Bus
– Bus Cycle Pipelining
4. Pentium Architecture
• It has data bus of 64 bit and address bus of 32-
bit
• There are two separate 8kB caches – one for
code and one for data.
• Each cache has a separate address translation
TLB which translates linear addresses to
physical.
• Code Cache:
– 2 way set associative cache
– 256 lines b/w code cache and prefetch buffer,
permitting prefetching of 32 bytes (256/8) of
instructions
5. Pentium Architecture
• Prefetch Buffers:
▫ Four prefetch buffers within the processor works as
two independent pairs.
When instructions are prefetched from cache, they are
placed into one set of prefetch buffers.
The other set is used as when a branch operation is
predicted.
▫ Prefetch buffer sends a pair of instructions to
instruction decoder
• Instruction Decode Unit:
▫ It occurs in two stages – Decode1 (D1) and
Decode2(D2)
▫ D1 checks whether instructions can be paired
▫ D2 calculates the address of memory resident
operands
6. Pentium Architecture
• Control Unit :
▫ This unit interprets the instruction word and
microcode entry point fed to it by Instruction
Decode Unit
▫ It handles exceptions, breakpoints and interrupts.
▫ It controls the integer pipelines and floating point
sequences
• Microcode ROM :
▫ Stores microcode sequences
• Arithmetic/Logic Units (ALUs) :
▫ There are two parallel integer instruction pipelines: u-
pipeline and v-pipeline
▫ The u-pipeline has a barrel shifter
▫ The two ALUs perform the arithmetic and logical
operations specified by their instructions in their
respective pipeline
7. Pentium Registers
• Four 32-bit registers can be used as
∗ Four 32-bit register (EAX, EBX, ECX, EDX)
∗ Four 16-bit register (AX, BX, CX, DX)
∗ Eight 8-bit register (AH, AL, BH, BL, CH, CL, DH, DL)
• Some registers have special use
∗ ECX for count in loop instructions
8. Pentium Registers (Eflags)
• Flags never change for any data transfer or program control operation.
• Some of the flags are also used to control features found in the
microprocessor.
9. • Flag bits, with a brief description of function.
• C (carry) holds the carry after addition or
borrow after subtraction.
▫ also indicates error conditions
• P (parity) is the count of ones in a number
expressed as even or odd. Logic 0 for odd parity;
logic 1 for even parity.
▫ if a number contains three binary one bits, it has
odd parity
▫ if a number contains no one bits, it has even parity
10. • C (carry) holds the carry after addition or
borrow after subtraction.
▫ also indicates error conditions
• P (parity) is the count of ones in a number
expressed as even or odd. Logic 0 for odd parity;
logic 1 for even parity.
▫ if a number contains three binary one bits, it has
odd parity; If a number contains no one bits, it
has even parity
• A (auxiliary carry) holds the carry (half-
carry) after addition or the borrow after
subtraction between bit positions 3 and 4 of the
result.
11. • Z (zero) shows that the result of an arithmetic or
logic operation is zero.
• S (sign) flag holds the arithmetic sign of the result
after an arithmetic or logic instruction executes.
• T (trap) The trap flag enables trapping through an
on-chip debugging feature.
• I (interrupt) controls operation of the INTR
(interrupt request) input pin.
• D (direction) selects increment or decrement
mode for the DI and/or SI registers.
• O (overflow) occurs when signed numbers are
added or subtracted.
▫ an overflow indicates the result has exceeded
the capacity of the machine
12. • IOPL used in protected mode operation
to select the privilege level for I/O devices.
• NT (nested task) flag indicates the current
task is nested within another task in protected
mode operation.
• RF (resume) used with debugging to control
resumption of execution after the next
instruction.
• VM (virtual mode) flag bit selects virtual
mode operation in a protected mode system
13. • AC, (alignment check) flag bit activates if a word
or doubleword is addressed on a non-word or non-
doubleword boundary.
• VIF is a copy of the interrupt flag bit available to the
Pentium 4–(virtual interrupt)
• VIP (virtual) provides information about a virtual
mode interrupt for (interrupt pending) Pentium.
▫ used in multitasking environments to provide virtual
interrupt flags
• ID (identification) flag indicates that the
Pentium microprocessors support the CPUID
instruction.
▫ CPUID instruction provides the system with
information about the Pentium microprocessor
15. • CD cache disable controls the internal cache. If
CD=1 , the cache will not fill with new data . If CD=0
misses will cause the cache to fill with new data
• NW Not write through selects the mode of operation
for the data cache. If NW=1, the data cache is
inhibited from cache write though
• AM Alignment mask enables alignment checking
when set, it only occurs for protected mode
• WP write protect protects user level pages against
supervisor level write operations. When WP=1, the
supervisor can write to user level segments
• NE numeric error enables standard numeric
coprocessor error detection.
17. • CLOCK
▫ CLK - Clock (Input)
Fundamental Timing for the Pentium
The CPU uses this signal as the internal processor
clock.
▫ BF - Bus Frequency (Input)
Bus Frequency determines the bus-to-core frequency
ratio
When BF is strapped to Vcc, the processor will
operate at a 2 to 3 bus to core frequency ratio.
When BF is strapped to Vss, the processor will
operate at a 1 to 2 bus to core frequency ratio.
18. • Initialization
▫ RESET - (Input)
Forces the CPU to begin execution at a known state.
▫ INIT - Initialization (Input)
The Pentium processor initialization input pin forces
the Pentium processor to begin execution in a
known state.
The processor state after INIT is the same as the
state after RESET except that the internal caches,
write buffers, and floating point registers retain the
values they had prior to INIT.
19. • Address Bus
▫ A31:A3 - ADDRESS bus lines
Output except for cache snooping
▫ The number of address lines determines the
amount of memory supported by the processor.
▫ Determines where in the 4GB memory space or
64K IO space the processor is accessing.
▫ These are input lines when AHOLD & EADS# are
active for Inquire Cycles (snooping)
20. • Address Bus
▫ BE7#:BEO#: Byte Enable lines (Outputs)
▫ Byte Enables to enable each of the 8 bytes in the
64-bit data path.
Helps define the physical area of memory or I/O
accessed.
The Pentium uses Byte Enables to address locations
within a QWORD.
In effect a decode of the address lines A2-A0 which
the Pentium does not generate.
Which lines go active depends on the address, and
whether a byte, word, double word or quad word is
required.
21. • Address Mask
▫ A20M#: Address 20 Mask (Input)
Emulates the address wraparound at 1 MByte which
occurs on the 8086.
When A20M# is asserted, the Pentium processor
masks physical address bit 20 (A20) before
performing a lookup to the internal caches or driving
a memory cycle on the bus.
A20#M must be asserted only when the processor is
in real mode.
• Internal Parity
▫ IERR# - Internal Error (Output)
Alerts System of Internal Parity Errors
22. • Address Parity
▫ AP Address Parity (I/O)
Bi-directional address parity pin for the address lines.
Address Parity is driven by the Pentium processor with
even parity information on all CPU generated cycles in
the same clock that the address is driven
Even parity must be driven back to the CPU during
inquire cycles on this pin in the same clock as EADS#.
Not supported on all systems
▫ APCHK#: Address Parity Check Signal (Output)
The status of the address parity check is driven on the
APCHK# output.
Even Parity Checking
23. • Data Bus.
▫ D63:DO - Data Lines (I/O).
The bi-directional 64-bit data path to or from the
CPU.
The signal W/R# distinguishes direction.
During reads, the CPU samples the data bus when
BRDY# is asserted.
▫ DP7: DP0 - Data Parity (I/O)
Bi-directional data parity pins for the data bus.
Even Parity Check. One for each byte of the data bus
Output on writes, Input on reads.
Not supported on all systems.
24. • Bus Control
▫ ADS# - Address Strobe (output)
Indicates that a new valid bus cycle is currently
being driven by the Pentium processor.
The following are some of the signals which are valid
when ADS#=0
Addresses (A31:3)
Byte Enables (BE7#:0#)
Bus Cycle definition (M/IO#; D/C#; W/R#, CACHE#)
From power-on the ADS# signal should be asserted
periodically when bus cycles are running
25. • Bus Control (Cont.)
▫ BRDY# - Burst Ready (Input)
Transfer complete indication.
The burst ready input indicates that the external system
has presented data on the data pins in response to a read
or that the external system has accepted the Pentium
processor data in response to a write request.
This signal ends the current bus cycle and is used to
extend bus cycles to allow slow devices extra time.
If LOW (non-burst cycles), this signal ends the
current bus cycle and the next bus cycle can begin.
If HIGH the Pentium is prevented from continuing
processing and wait states are added.
26. • Bus Cycle Definition
▫ M/IO# - Memory or Input/Output (output)
M/IO# distinguishes between Memory and I/O
cycles.
The memory/input-output is one of the primary bus
cycle definition pins.
1 = Memory Cycle
0 = Input/Output Cycle
It is driven valid in the same clock as the ADS#
signal is asserted.
27. • Bus Cycle Definition (Cont.)
▫ D/C# - Data or Code (output)
D/C# distinguishes between data and code or special
cycles (control)
The data/code output is one of the primary bus cycle
definition pins.
1 = Data
0 = Code / Control
»Control for Interrupt Acknowledge or Special Cycles
It is driven valid in the same clock as the ADS#
signal is asserted.
28. • Bus Cycle Definition (Cont.)
▫ W/R# - Write or Read (output)
W/R# distinguishes between Write and Read cycles.
Write/read is one of the primary bus cycle
definition pins.
1 = Write
0 = Read
It is driven valid in the same clock as the ADS#
signal is asserted.
29. • Bus Cycle Definition (Cont.)
▫ Cache# - Cache ability (output)
Processor indication of internal cache ability.
The L1 cache must be enabled using the CD bit in
CR0 for Cache# to be asserted low.
The Cache# signal could also be described as the
BURST instruction signal, because the Cache# signal
(qualified with KEN#) results in a burst mode
transfer of 32 bytes of code or data.
Cache# and Ken# are used together to determine if
a read will be turned into a linefill. (Burst cycle).
During write-back cycles, the CPU asserts the
CACHE# signal (KEN# does not have to be asserted)
30. • Bus Cycle Definition (Cont.)
▫ NA# - Next Address (Input)
Indicates external memory is prepared for a pipeline
cycle.
An active next address input indicates that the
external memory system is ready to accept a new bus
cycle although all data transfers for the current cycle
have not yet completed.
When NA# is asserted, the Pentium supplies the
address for the start of the next transfer early, so
that the memory system can latch the new address
before the transfer is ready to start.
A detailed discussion of Address Pipelining is
beyond the scope of this course.
31. • Bus Cycle Definition (Cont.)
▫ Lock# - Bus Lock (Output)
The bus lock pin indicates that the current bus cycle is
locked, typically for a read-modify-write operation.
The CPU will not allow a bus hold when LOCK# is
asserted.
Locked cycles are generated when the programmer
prefixes certain instructions with the LOCK prefix.
e.g. LOCK INC [EDI] ;Increment a memory location
Locked cycles are generated automatically for certain bus
transfer operations.
Interrupt Acknowledge cycles
The XCHG instructions when 1 operand is memory-based.
See Pentium manual for more details.
32. • Cache Control
▫ KEN# - Cache Enable (Input)
Indicates to the Pentium whether or not the system
can support a cache line fill for the current cycle.
Cache# and Ken# are used together to determine if
a read will be turned into a linefill. (Burst cycle).
▫ WB/WT# - Write-back/Write-through (Input)
This pin allows a cache line to be defined as a a write
back or write-through on a line by line basis.
33. • Bus Arbitration
▫ HOLD - Bus Hold (Input)
Allows another bus master complete control of the
CPU bus.
In response to the bus hold request, the Pentium
processor will float most of its output and
input/output pins and assert HLDA after
completing all outstanding bus cycles.
The Pentium processor will maintain its bus in this
state until HOLD is de-asserted.
▫ HLDA - Bus Hold Acknowledge (Output)
External indication that the Pentium™ outputs are
floated.
34. • Bus Arbitration (Cont.)
▫ BOFF# - Backoff (Input)
Forces the Pentium to get off the bus in the next
clock.
After BOFF# is removed, the Pentium restarts the
bus cycle.
▫ BREQ - Bus Request (output)
Indicates externally when a bus cycle is pending
internally.
Used to inform the arbitration logic that the Pentium
need control of the bus to perform a bus cycle.
35. • Interrupts
▫ INTR - Maskable Interrupt (Input)
Indicates that an external interrupt has been
generated.
If the IF(Interrupt Enable Flag) bit in the EFLAGS
register is set, the Pentium processor will generate
two locked interrupt acknowledge bus cycles (to get
type number) and vectors to an interrupt handler
after the current instruction execution is completed.
▫ NMI - Non-Maskable Interrupt (Input)
Indicates that an external non maskable interrupt
has been generated.
The Pentium processor will vector to a Type 2
interrupt handler after the current instruction
execution is completed
36. • Probe Mode
▫ R/S# - Resume/Stop [Run/Scan] (Input)
The run/stop input is an asynchronous, edge-
sensitive interrupt used to stop the normal execution
of the processor and place it into an idle state.
▫ PRDY - Probe Ready (Output)
The probe ready output pin indicates that the
processor has stopped normal execution in response
to the R/S# pin going active. The CPU enters Probe
Mode.
37. What is Superscalar?
• Common instructions (arithmetic, load/store,
conditional branch) can be initiated and
executed independently
• Equally applicable to RISC & CISC
• In practice usually RISC
39. Superpipelined
• Many pipeline stages need less than half a clock
cycle
• Double internal clock speed gets two tasks per
external clock cycle
• Superscalar allows parallel fetch execute
42. True Data Dependency
• ADD r1, r2 (r1 := r1+r2;)
• MOVE r3,r1 (r3 := r1;)
• Can fetch and decode second instruction in
parallel with first
• Can NOT execute second instruction until first is
finished
43. Procedural Dependency
• Can not execute instructions after a branch in
parallel with instructions before a branch
• Also, if instruction length is not fixed,
instructions have to be decoded to find out how
many fetches are needed
• This prevents simultaneous fetches
44. Resource Conflict
• Two or more instructions requiring access to the
same resource at the same time
▫ e.g. two arithmetic instructions
• Can duplicate resources
▫ e.g. have two arithmetic units
45. Output Dependency
• Write-write dependency
▫ R3:=R3 + R5; (I1)
▫ R4:=R3 + 1; (I2)
▫ R3:=R5 + 1; (I3)
▫ R7:=R3 + R4; (I4)
In the above instruction sequence I2 cannot be
executed before I1 as of true dependency and
similar of I4 and I3
If They are not executed sequentially wrong values
will be fetched which is referred as output
dependency
46. Antidependency
• Write-write dependency
▫ R3:=R3 + R5; (I1)
▫ R4:=R3 + 1; (I2)
▫ R3:=R5 + 1; (I3)
▫ R7:=R3 + R4; (I4)
▫ I3 can not complete before I2 starts as I2 needs a
value in R3 and I3 changes R3
47. Design Issues
• Instruction level parallelism
▫ Instructions in a sequence are independent
▫ Execution can be overlapped
▫ Governed by data and procedural dependency
• Machine Parallelism
▫ Ability to take advantage of instruction level
parallelism
▫ Governed by number of parallel pipelines
48. Instruction Issue Policy
• Order in which instructions are fetched
• Order in which instructions are executed
• Order in which instructions change registers and
memory
49. In-Order Issue In-Order Completion
• Issue instructions in the order they occur
• Not very efficient
• May fetch >1 instruction
• Instructions must stall if necessary
50. In-Order Issue Out-of-Order Completion
• If any instruction is independent on current
instruction then it is then it is allowed to
execute before completion of current instruction
51. Out-of-Order Issue Out-of-Order Completion
• Decouple decode pipeline from execution pipeline
• Can continue to fetch and decode until this pipeline is
full
• When a functional unit becomes available an instruction
can be executed
• Since instructions have been decoded, processor can
look ahead
52. Register Renaming
• Output and antidependencies occur because
register contents may not reflect the correct
ordering from the program
• May result in a pipeline stall
• Registers allocated dynamically
▫ i.e. registers are not specifically named
54. Superscalar Implementation
• Simultaneously fetch multiple instructions
• Logic to determine true dependencies involving
register values
• Mechanisms to communicate these values
• Mechanisms to initiate multiple instructions in
parallel
• Resources for parallel execution of multiple
instructions
• Mechanisms for committing process state in
correct order
56. Data Transfer Instructions
• Move data between memory and the general
purpose and segment registers.
• Perform some operations as conditional moves,
stack access, and data conversion