1. Srishail Upadhye
Unit # 335, 625 W, 1st street 1-480-559-4867
Tempe, AZ 85281 supadhye@asu.edu
Linkedin : www.linkedin.com/in/srishail/
SUMMA RY
ASIC Design Engineer with 4 years of ASIC design experience, specializing in Static Timing Analysis (STA) , Physical
Design and Design for Test (DFT)
SKILLS
 STA and Timing closure on SoC’s in sub-micron technologies, Floorplanning, STASignoff
 DRC/LVS, Clock Tree Synthesis, Formal Verification, noise, Cross-talk, OCV effect analysis, Timing Triage
 MBIST, ATPG Stuck-At & Transition, BSCAN, PLL Debug, JTAG, Coverage analysis and improvement
 RTL Design & Verification
 RTL coding, Coverage analysis and improvement, RTL assertions
 Tools : Synopsys-ICC, Primetime, VCS, FPGA-Xilinx, Cadence-Virtuoso, Spectre, Encounter, Mentor-Fastscan, SPICE
 Languages: Verilog, System Verilog, VHDL, Perl, Tcl/Tk
EDUCA T ION
MS Candidate - Electrical Engineering, Mixed Signal Circuit Design Expected May 2016
Arizona State University, GPA 3.56
Bachelor of Engineering, Electronics and Telecommunication August 2009
Pune University, GPA 3.8
ACA DEMIC PROJECT S
 Register File – Layout and Design, optimization focus - area and EDP
 Complete schematic design, DRC/LVS clean, custom layout for 1KB with 9T cell along with read and write
peripheral circuitry for min area and EDP
 Spice level simulations for the RF cell across various corners
 Layout and Design of 8-bit pipelined adder and optimization for minimum EDP
 Custom FF and 1-bit FA design – DRC/LVS clean
 Complete layout of pipelined adder along with SPICE level simulations
RELA T ED EXPERIENCE
Physical Design Intern-Timing, Apple Inc. Aug – Dec 2015
 Work with design teams to understand and debug constraints
 Facilitate logic changes to improve timing
 Timing Triage and suggest timing fixes to FE team, PD team
RTL Design and FPGA Intern, Seagate Technology May 2015 – Aug 2015
 FPGA Validation for PCIe + NVMe accelerator chip
 Debug FPGA bring-up issues, Perl/Tcl automation for debug
ASIC Design Engineer 2, LSI Logic Oct 2011 - July 2014
Static Timing analysis & Design for Test, Physical Design team, Custom Silicon Design group
 Block level Static Timing Analysis (STA), Block Level DFT logic insertion and Silicon Verification/Debugging on Cisco
‘Strider’ – 28nm CAM intensive Router design with gate count of ~40 million
 Individual owner - Memory BIST synthesis and BSCAN/JTAG synthesis, STA for MBIST and SCAN modes
 ATE pattern generation and pattern simulation with/without timing annotation,
 Debug ATE pattern failures: MBIST, BSCAN, JTAG, SERDES (coreware/IP)
 Lead DFT for a 28nm SERDES test chip – flop count of ~1million
 ATPG for Stuck-At, Transition, IDDQ, DRC analysis, Coverage analysis and improvement
 Static Timing Analysis (STA) for 2 blocks with a gate count of ~500K - False path and Multicycle path
recognition, timing Constraint analysis and improvement, CDC checks
 Debug Post-Silicon SCAN chain integrity issues and MBIST issues for two 28nm SERDES test chips
 Pre-Test/Post-Test netlist quality check automation using Perl and Tcl
Intern - RTL Design, LSI Logic Jan 2011 - Oct 2011
RAID Accelerator engine and Storage Design group
 RTL Design and Implementation of AMBA-AHB module on a 28 nm RAID Accelerator chip