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Himabindu C
Himabindu.chitrapu@gmail.com
Ph: +91-8121576484
Summary:
 Over 3+ years of experience in the IT industry extensively in VLSI domain
 Strong experience in Verilog, VHDL
 Good experience in python scripting.
 Good experience in designing and verifying the I2C & AXI blocks using Cadence NCsim & Questasim
& Modelsim.
 Implementation of a Subset of I2C protocol - CCI
 Implementation of parallel sensor interface.
 Good experience in DDR2 & DDR3 simulation models
 Strong knowledge in Image sensors
 Strong knowledge of FPGA/ASIC Design Flows
 Wide exposure to VLSI EDA Tools
 Good Knowledge in AXI bus interface
 Comprehensive knowledge on the methodologies and applications of verification tools
Technical Skills:
Hardware:
Languages: Verilog, VHDL
Scripting languages: python scripting
Domain: VLSI, ASIC, FPGA Design Methodology
Front End EDA Tools: Xilinx ISE, ModelSim
Software:
Languages: C, C++
Database: SQL Server 2005
OS: UNIX, Linux, Windows
Educational Details:
 PG Diploma in VLSI Design from MS Ramaiah School Of Advanced Studies, Bangalore, India in
2009
 BTech (ECE) from Jawaharlal Nehru Technological University- Anantapur, Andhra Pradesh, India in
2008
 Diploma in Electronics and Communications from Sri Padmavathi Mahila Polytechnic College,
Tirupathi, Andhra Pradesh, India in 2005
 10th from Karunya English Medium High School, Tirupati AP in 2002
Employment Details:
 Working with IFM Engineering Pvt. Ltd., Pune, India as Design & Verification Engineer from Jun 12 –
May 14
 Worked with UTL Technologies Ltd, Bangalore, India as Associate Consultant-VLSI from Jan 11 -
May 12
Project Details:
Project #1
Title: performing on-chip hardware/software verification using Chipscope-Pro and the software
debugger.
Company: IFM Engineering Pvt. Ltd., Pune, India
Role: Design & Verification Engineer
Duration: Mar 14 to May 14
Tools/Environment: Xilinx EDK, SDK & Chipscope,vivado and logic analyzer
Role: To create and write the software and base builder project for the memory application for
interfacing micro blaze and Mcb using AXI bus and debug the configurations using
Chipscope,vivado
Description: The ChipScope AXI Monitor core is designed to monitor and debug AXI interfaces. The
core allows the probing of any signals going from a peripheral to the AXI interconnects. For example, the
user can instantiate a monitor on a MicroBlaze instruction or data interface to observe all memory
transactions going in and out of the processor. Have written a software code for interfacing MIG and MCB
for read and write data transactions and monitor the signals using ChipScope.
Project #2
Title: Automated testing using python
Company: IFM Engineering Pvt. Ltd., Pune, India
Role: Design & Verification Engineer
Duration: Dec 13 to Mar 14
Tools/Environment: python 3.3, pysvn, HDL Designer, Modelsim
Role: To Automate the testing process for High Resolution camera project
Description: Have written a python code for invoking HDL Designer and Modelsim. Developed different
test suites for entire project and automated the same. Used File comparison features, mat lab functions in
python. Written python code for simulating Vhdl codes with Modelsim.
Project #3
Title: Design and Development parallel sensor interface for generating 12 bit grayscale data
Company: IFM Engineering Pvt. Ltd., Pune, India
Role: Design & Verification Engineer
Duration: Oct 13 to Nov 13
Tools/Environment: Model-Sim, Xilinx, HDL-Designer tool for block diagrams and creating Fsm’s,
VHDL
Role: To study the complete PMD Sensor data sheet (M2440 Generic Device) and to
understand requirement. RTL Development for the same.
Description: Parallel interface (PIF) supports direct connection to 12 bit raw grayscale data complaint
controllers. The PIF provides the digital data stream on digital general ports (GPIO) of PMD sensor, as
well as horizontal and vertical synchronization (Hsync, Vsync) and the pixel clock (clkpix).
Project #4:
Title: Design and Development Camera Control Interface-CCI for MIPI Alliance Standard
Camera Serial Interface2-CSI2
Company: IFM Engineering Pvt. Ltd., Pune, India
Role: Design & Verification Engineer
Duration: sept 13 to Oct 13
Tools/Environment: Model-Sim, Xilinx, HDL-Designer tool for block diagrams and creating Fsm’s,
VHDL
Role: To study the complete HSI2C protocol. Study specifications for the protocol and to
understand requirement. RTL Development for the same. Testing and Verification of
complete RTL.
Description: CCI is a serial communication protocol. CCI is used for transmitting control signals from
host processor to camera module. It is a subset of I2C protocol. At the camera device, it stores
information in predefined register set for controlling the camera module.
Project #5:
Title: HIGH Resolution camera using 3D Image sensors (SoC)
Company: IFM Engineering Pvt. Ltd., Pune, India
Role: Design & Verification Engineer
Duration: July 13 –Sept 13
Module 1:
Title: FPGA firmware MCB writer
Tools/Environment: Model-Sim, Xilinx, HDL-Designer tool for block diagrams and creating Fsm’s,
VHDL, vivado and logic analyzer
Role: Writing Design document, VHDL coding, code coverage
Description:
The MCBWriter is a VHDL component for the FPGA subsystem of the high resolution camera. It controls
the writing of a 32 bit image to the DDR2 memory. To control the flow of the image data, control signals,
which include information like frame start, line start, frame end etc., are given to the MCBWriter. This
component is the counterpart to the MCBReader, which is also part of the high resolution project.
Module 2:
Title: FPGA firmware MCB Reader
Tools/Environment: Model-Sim, VHDL, vivado and logic analyzer
Role: Writing test cases document, Assertion based testing, Functional verification
code coverage, review of modules
Description:
The MCBReader is a VHDL component for the FPGA subsystem of the high resolution camera. It controls
the reading of (possibly) multiple images and correction matrices from DDR2 memory. The pixels from the
various images have to be output in parallel. That’s why the component has to buffer the multiple DDR2
bursts internally. To control the flow of the image data, control signals, which include information like
frame start, line start, frame end etc., are generated by a separate component which is part of the
MCBReader.
Module 3:
Title: Cordic Algorithm
Tools/Environment: Model-Sim, Xilinx, HDL-Designer tool for block diagrams, VHDL
Role: Writing Design document, VHDL coding, code coverage, Writing test cases
document, Assertion based testing, Functional verification code coverage, review
of modules
Description:
To calculate the distance between target and camera, the autocorrelation function of electrical and optical
signal is analyzed by a phase-shift algorithm. The module calculates ARCTAN function for input angle.
Computations are based on CORDIC algorithm. The module accepts 16 bit data as angle and gives
ARCTAN of input in radians, as 16 bit output.
Features:
 Parallel implementation of algorithm
 16 bit input and output width
 Latency of 18 clock cycles
 Maximum operating frequency is 250 MHz
 Maximum absolute accuracy is 0.004819929 degree (8.415 x 10-5 radian)
Module 4:
Title: SPI Interface (IP)
Tools/Environment: Model-Sim, vivado and logic analyzer, HDL-Designer tool for block diagrams,
Verilog, OVM
Role: Writing Design document, VHDL coding, code coverage, Writing test cases
document, Assertion based testing, Functional verification code coverage, review
of modules
Description:
The processor system uses this interface for reading/writing FPGA registers. To address different
components within the FPGA, the address is split into address ranges. Every address range sets a CS.
Responsibilities:
 Responsible for preparing and implementing the approach document, design document & detailed
test plans for the design modules
 Designed and verified the Memory Controller Blocks – Reader & Writer blocks, CORDIC Algorithm &
SPI interface
 Understanding MIRA Data sheet and documenting the same about possible algorithms
 Studying IMx6 processor for developing the processor interface block
 Played active role in simulation, verification coding, and review of modules
 Performed responsibilities of developing random, critical and application level tests to ensure full
feature coverage
 Handled the tasks of identifying, implementing and tracking test and code coverage against product
features and test plans
 Responsible for providing support to the design staff in debugging fixes and designing debugs.
 Familiar with HDL Designer tool
 Performed the tasks of implementing stimulus and checking modules with the help of senior
verification engineer
 Performed the verification of functional coverage by applying the assertions
Project #6:
Title: PCI-E
Company: UTL Technologies Pvt. Limited
Tools/Environment: Cadence tools, Xilinx, Synopsys DC compiler, Verilog
Role: Writing Design document, Verilog coding, code coverage, writing test cases
document, Assertion based testing, Functional verification code coverage, review
of modules
Duration: Sep 12 – Dec 12
Description:
PCI-Express is rapidly becoming the industry standard for high-speed bus interconnect. Leveraging the
existing software infrastructure for PCI while adding a high-speed serial physical layer has been a winning
combination. Designers who are trying to squeeze every ounce of performance and capability from PCI-
Express may be surprised however if a few important guidelines are overlooked. For example, long
latency and the resulting connection efficiency can stall performance in a system if they are not
understood and taken into account in a new design.
Project #7:
Title: I2C interface
Company: UTL Technologies Pvt. Limited
Environment: Verilog
Duration: Jun 12 - Aug 12
Description:
The I²C (Inter-Integrated Circuit generically referred to as "two-wire interface") is implemented using
Verilog and Field Programmable Gate Arrays (FPGA). This I²C interface will create the communication
between master and slave devices. The interface will read the command of the master and send
corresponding response to the master. Our interface design includes read and write operations and will
be able to communicate to master and slave through the I2C.
The verification environment has been developed and test cases have been implemented for I2C Design
under Test (DUT). The verification has been done using System Verilog Hardware Description and
Verification Language.
Project #8:
Title: Verification of AHB bus
Company: UTL Technologies Pvt. Limited
Environment: Verilog
Duration: Jan 12 - May 12
Description: This bus is used for high-performance, high clock frequency system modules. This bus is
acts as the backbone bus. AHB efficiently interconnects processors, on-chip memories and off-chip
external memories interfaces with low-power peripherals macro cell functions.
The design architecture is written using Verilog HDL using Modelsim tool. The timing diagrams are also
generated on this tool. The synthesis of the design is done on Xilinx tool. The mapping, floor planning,
places and routes are also generated on Xilinx tool.
Responsibilities:
 Interacting with Front end and Back End teams to understand the architecture and design
applications
 As a guest faculty handled the “Fundamentals of FPGA Design” at Anjuman Engineering College,
Bhatkal
 As a Technical Consultant handled the “Digital Design using Verilog” workshop at SVPCET, Puttoor,
and Andhra Pradesh
 Handled 5 days “VLSI Frontend workshop" for the faculty of CAPE Engineering College. This faculty
development program covers the following topics Verilog, System Design, DFT, Verification,
Simulation and synthesis issues, Static timing analysis
 Taught the following subjects for PG Students, faculty people in UTL Technologies Ltd., Bangalore.
Subjects Handled: VLSI Design & Verification, Synthesis by Synopsys DC compiler, Testing &
Verification of VLSI Circuits
 As a trainer handled the several projects for B.Tech and M.Tech students & helped them to solve
simulation & synthesis issues
 As a project coordinator handled 10 teams and helped them in front end design and helped them to
understand the verification flow
 Designed and verified the PCIE, I2C & AHB blocks using Cadence NCsim & Questasim
 Played active role in simulation, verification coding, and review of modules
 Assisted verification staff in creating, running, debugging and tracking tests against test plans
Internship Project-VLSI, MSRSAS, Bangalore, India Dec 09 - Dec 11
Design of Asynchronous FIFO:
 Designed and implemented Asynchronous FIFO Using Verilog
 Verified the same using System Verilog based on OVM/VMM methodology
Design & Implementation of VCO:
 Designed VCO using Cadence Virtuoso
 Designed the same using the Synopsys Tool

Academic Projects:
 “Intelligent Metal Sensing Bluetooth Robot” in MIC Electronics Pvt. Ltd, Hyderabad. (B.Tech)
 “Designing of LCD Thermometer for Industrial Applications”, Circuit design was done on PCB’s and
verified successfully in SPICE. (Diploma)

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Bindu_Resume

  • 1. Himabindu C Himabindu.chitrapu@gmail.com Ph: +91-8121576484 Summary:  Over 3+ years of experience in the IT industry extensively in VLSI domain  Strong experience in Verilog, VHDL  Good experience in python scripting.  Good experience in designing and verifying the I2C & AXI blocks using Cadence NCsim & Questasim & Modelsim.  Implementation of a Subset of I2C protocol - CCI  Implementation of parallel sensor interface.  Good experience in DDR2 & DDR3 simulation models  Strong knowledge in Image sensors  Strong knowledge of FPGA/ASIC Design Flows  Wide exposure to VLSI EDA Tools  Good Knowledge in AXI bus interface  Comprehensive knowledge on the methodologies and applications of verification tools Technical Skills: Hardware: Languages: Verilog, VHDL Scripting languages: python scripting Domain: VLSI, ASIC, FPGA Design Methodology Front End EDA Tools: Xilinx ISE, ModelSim Software: Languages: C, C++ Database: SQL Server 2005 OS: UNIX, Linux, Windows Educational Details:  PG Diploma in VLSI Design from MS Ramaiah School Of Advanced Studies, Bangalore, India in 2009  BTech (ECE) from Jawaharlal Nehru Technological University- Anantapur, Andhra Pradesh, India in 2008  Diploma in Electronics and Communications from Sri Padmavathi Mahila Polytechnic College, Tirupathi, Andhra Pradesh, India in 2005  10th from Karunya English Medium High School, Tirupati AP in 2002 Employment Details:  Working with IFM Engineering Pvt. Ltd., Pune, India as Design & Verification Engineer from Jun 12 – May 14  Worked with UTL Technologies Ltd, Bangalore, India as Associate Consultant-VLSI from Jan 11 - May 12
  • 2. Project Details: Project #1 Title: performing on-chip hardware/software verification using Chipscope-Pro and the software debugger. Company: IFM Engineering Pvt. Ltd., Pune, India Role: Design & Verification Engineer Duration: Mar 14 to May 14 Tools/Environment: Xilinx EDK, SDK & Chipscope,vivado and logic analyzer Role: To create and write the software and base builder project for the memory application for interfacing micro blaze and Mcb using AXI bus and debug the configurations using Chipscope,vivado Description: The ChipScope AXI Monitor core is designed to monitor and debug AXI interfaces. The core allows the probing of any signals going from a peripheral to the AXI interconnects. For example, the user can instantiate a monitor on a MicroBlaze instruction or data interface to observe all memory transactions going in and out of the processor. Have written a software code for interfacing MIG and MCB for read and write data transactions and monitor the signals using ChipScope. Project #2 Title: Automated testing using python Company: IFM Engineering Pvt. Ltd., Pune, India Role: Design & Verification Engineer Duration: Dec 13 to Mar 14 Tools/Environment: python 3.3, pysvn, HDL Designer, Modelsim Role: To Automate the testing process for High Resolution camera project Description: Have written a python code for invoking HDL Designer and Modelsim. Developed different test suites for entire project and automated the same. Used File comparison features, mat lab functions in python. Written python code for simulating Vhdl codes with Modelsim. Project #3 Title: Design and Development parallel sensor interface for generating 12 bit grayscale data Company: IFM Engineering Pvt. Ltd., Pune, India Role: Design & Verification Engineer Duration: Oct 13 to Nov 13 Tools/Environment: Model-Sim, Xilinx, HDL-Designer tool for block diagrams and creating Fsm’s, VHDL Role: To study the complete PMD Sensor data sheet (M2440 Generic Device) and to understand requirement. RTL Development for the same. Description: Parallel interface (PIF) supports direct connection to 12 bit raw grayscale data complaint controllers. The PIF provides the digital data stream on digital general ports (GPIO) of PMD sensor, as well as horizontal and vertical synchronization (Hsync, Vsync) and the pixel clock (clkpix). Project #4: Title: Design and Development Camera Control Interface-CCI for MIPI Alliance Standard Camera Serial Interface2-CSI2 Company: IFM Engineering Pvt. Ltd., Pune, India Role: Design & Verification Engineer Duration: sept 13 to Oct 13 Tools/Environment: Model-Sim, Xilinx, HDL-Designer tool for block diagrams and creating Fsm’s, VHDL
  • 3. Role: To study the complete HSI2C protocol. Study specifications for the protocol and to understand requirement. RTL Development for the same. Testing and Verification of complete RTL. Description: CCI is a serial communication protocol. CCI is used for transmitting control signals from host processor to camera module. It is a subset of I2C protocol. At the camera device, it stores information in predefined register set for controlling the camera module. Project #5: Title: HIGH Resolution camera using 3D Image sensors (SoC) Company: IFM Engineering Pvt. Ltd., Pune, India Role: Design & Verification Engineer Duration: July 13 –Sept 13 Module 1: Title: FPGA firmware MCB writer Tools/Environment: Model-Sim, Xilinx, HDL-Designer tool for block diagrams and creating Fsm’s, VHDL, vivado and logic analyzer Role: Writing Design document, VHDL coding, code coverage Description: The MCBWriter is a VHDL component for the FPGA subsystem of the high resolution camera. It controls the writing of a 32 bit image to the DDR2 memory. To control the flow of the image data, control signals, which include information like frame start, line start, frame end etc., are given to the MCBWriter. This component is the counterpart to the MCBReader, which is also part of the high resolution project. Module 2: Title: FPGA firmware MCB Reader Tools/Environment: Model-Sim, VHDL, vivado and logic analyzer Role: Writing test cases document, Assertion based testing, Functional verification code coverage, review of modules Description: The MCBReader is a VHDL component for the FPGA subsystem of the high resolution camera. It controls the reading of (possibly) multiple images and correction matrices from DDR2 memory. The pixels from the various images have to be output in parallel. That’s why the component has to buffer the multiple DDR2 bursts internally. To control the flow of the image data, control signals, which include information like frame start, line start, frame end etc., are generated by a separate component which is part of the MCBReader. Module 3: Title: Cordic Algorithm Tools/Environment: Model-Sim, Xilinx, HDL-Designer tool for block diagrams, VHDL Role: Writing Design document, VHDL coding, code coverage, Writing test cases document, Assertion based testing, Functional verification code coverage, review of modules Description: To calculate the distance between target and camera, the autocorrelation function of electrical and optical signal is analyzed by a phase-shift algorithm. The module calculates ARCTAN function for input angle. Computations are based on CORDIC algorithm. The module accepts 16 bit data as angle and gives ARCTAN of input in radians, as 16 bit output. Features:  Parallel implementation of algorithm  16 bit input and output width  Latency of 18 clock cycles  Maximum operating frequency is 250 MHz  Maximum absolute accuracy is 0.004819929 degree (8.415 x 10-5 radian)
  • 4. Module 4: Title: SPI Interface (IP) Tools/Environment: Model-Sim, vivado and logic analyzer, HDL-Designer tool for block diagrams, Verilog, OVM Role: Writing Design document, VHDL coding, code coverage, Writing test cases document, Assertion based testing, Functional verification code coverage, review of modules Description: The processor system uses this interface for reading/writing FPGA registers. To address different components within the FPGA, the address is split into address ranges. Every address range sets a CS. Responsibilities:  Responsible for preparing and implementing the approach document, design document & detailed test plans for the design modules  Designed and verified the Memory Controller Blocks – Reader & Writer blocks, CORDIC Algorithm & SPI interface  Understanding MIRA Data sheet and documenting the same about possible algorithms  Studying IMx6 processor for developing the processor interface block  Played active role in simulation, verification coding, and review of modules  Performed responsibilities of developing random, critical and application level tests to ensure full feature coverage  Handled the tasks of identifying, implementing and tracking test and code coverage against product features and test plans  Responsible for providing support to the design staff in debugging fixes and designing debugs.  Familiar with HDL Designer tool  Performed the tasks of implementing stimulus and checking modules with the help of senior verification engineer  Performed the verification of functional coverage by applying the assertions Project #6: Title: PCI-E Company: UTL Technologies Pvt. Limited Tools/Environment: Cadence tools, Xilinx, Synopsys DC compiler, Verilog Role: Writing Design document, Verilog coding, code coverage, writing test cases document, Assertion based testing, Functional verification code coverage, review of modules Duration: Sep 12 – Dec 12 Description: PCI-Express is rapidly becoming the industry standard for high-speed bus interconnect. Leveraging the existing software infrastructure for PCI while adding a high-speed serial physical layer has been a winning combination. Designers who are trying to squeeze every ounce of performance and capability from PCI- Express may be surprised however if a few important guidelines are overlooked. For example, long latency and the resulting connection efficiency can stall performance in a system if they are not understood and taken into account in a new design. Project #7: Title: I2C interface Company: UTL Technologies Pvt. Limited Environment: Verilog Duration: Jun 12 - Aug 12 Description: The I²C (Inter-Integrated Circuit generically referred to as "two-wire interface") is implemented using Verilog and Field Programmable Gate Arrays (FPGA). This I²C interface will create the communication between master and slave devices. The interface will read the command of the master and send
  • 5. corresponding response to the master. Our interface design includes read and write operations and will be able to communicate to master and slave through the I2C. The verification environment has been developed and test cases have been implemented for I2C Design under Test (DUT). The verification has been done using System Verilog Hardware Description and Verification Language. Project #8: Title: Verification of AHB bus Company: UTL Technologies Pvt. Limited Environment: Verilog Duration: Jan 12 - May 12 Description: This bus is used for high-performance, high clock frequency system modules. This bus is acts as the backbone bus. AHB efficiently interconnects processors, on-chip memories and off-chip external memories interfaces with low-power peripherals macro cell functions. The design architecture is written using Verilog HDL using Modelsim tool. The timing diagrams are also generated on this tool. The synthesis of the design is done on Xilinx tool. The mapping, floor planning, places and routes are also generated on Xilinx tool. Responsibilities:  Interacting with Front end and Back End teams to understand the architecture and design applications  As a guest faculty handled the “Fundamentals of FPGA Design” at Anjuman Engineering College, Bhatkal  As a Technical Consultant handled the “Digital Design using Verilog” workshop at SVPCET, Puttoor, and Andhra Pradesh  Handled 5 days “VLSI Frontend workshop" for the faculty of CAPE Engineering College. This faculty development program covers the following topics Verilog, System Design, DFT, Verification, Simulation and synthesis issues, Static timing analysis  Taught the following subjects for PG Students, faculty people in UTL Technologies Ltd., Bangalore. Subjects Handled: VLSI Design & Verification, Synthesis by Synopsys DC compiler, Testing & Verification of VLSI Circuits  As a trainer handled the several projects for B.Tech and M.Tech students & helped them to solve simulation & synthesis issues  As a project coordinator handled 10 teams and helped them in front end design and helped them to understand the verification flow  Designed and verified the PCIE, I2C & AHB blocks using Cadence NCsim & Questasim  Played active role in simulation, verification coding, and review of modules  Assisted verification staff in creating, running, debugging and tracking tests against test plans Internship Project-VLSI, MSRSAS, Bangalore, India Dec 09 - Dec 11 Design of Asynchronous FIFO:  Designed and implemented Asynchronous FIFO Using Verilog  Verified the same using System Verilog based on OVM/VMM methodology Design & Implementation of VCO:  Designed VCO using Cadence Virtuoso  Designed the same using the Synopsys Tool  Academic Projects:  “Intelligent Metal Sensing Bluetooth Robot” in MIC Electronics Pvt. Ltd, Hyderabad. (B.Tech)  “Designing of LCD Thermometer for Industrial Applications”, Circuit design was done on PCB’s and verified successfully in SPICE. (Diploma)