1. VARUN R GATNE
8510 Costa Verde Blvd, Apt No: 2202, varun.gatne@gmail.com
San Diego, CA -92122 +1 (404) 545 - 4392
OBJECTIVE
Seeking a full-time position in the domain of ASIC / VLSI / Physical Design / Low Power Design / Computer Architecture.
WORK EXPERIENCE
Qualcomm Inc. as Low Power Engineer (Contractor)
San Diego, CA / July 2014 - Present.
 Evaluating power reduction opportunities for next gen Adreno GPUs.
 Exposure to debugging and developing Synopsys Primetime flows for power rollup of next gen Qualcomm GPUs.
 Involved in evaluating the architectural inefficiencies of current and previous generation GPUs based on power estimation.
 Developed scripts to further automate various post-processing tasks and flows.
 Knowledge of graphics hardware pipeline architecture, while working on Qualcomm's Snapdragon SOC.
Intel Corporation as Low Power Design Intern
Folsom, CA / Sept 2013 - Jan 2014
 Worked in the Visual and Parallel Computing (VPG) group on Intel's SOC in evaluating the capabilities of Apache Power Artist to estimate and optimize power at the RTL level.
 Studied impact of factors like standard cell selection, interconnect capacitances, clock tree synthesis and worked on correlating the power estimation methods with those used in Synopsys Primetime PX post synthesis and placement.
 Obtained 85% accuracy in power estimation with respect to PTPX and power optimization suggestions based on clock gating.
 Worked on improving mapping between Emulation SAIF and gate level netlist for power analysis.
EDUCATION
Georgia Institute of Technology, Atlanta / M.S. in Electrical and Computer Engineering / Aug 12 - May 14
GPA : 3.3/ 4.0
University of Mumbai, Mumbai, India / BE in Electronics Engineering / Aug 08 - Jul 12
GPA : 3.7/4.0
PROJECTS
VLSI Physical Design:
 ASIC Design Implementation: Block level implementation of an execution stage of a pipelined processor with varied complexities (150-200 MHz, 45nm technology library). This lab based project consisted of implementing the backend ASIC design flow with a given RTL - Netlist to GDSII (Synthesis, Floorplanning, Placement, Routing, Physical verification checks and GDS release). Tools: Synopsys Design Compiler(DesignVision), Cadence Encounter, Cadence Virtuoso.
VLSI Systems:
 Digital FIR Filter Design: Designed a 4-Tap FIR filter using Wallace tree multiplier and a Carry look-ahead adder using FreePDK 45nm Predictive Technology. The 6-bit adder was laid out and was made DRC-LVS clean. Also, sleep transistors were implemented for power gating to reduce the standby leakage power.
TECHNICAL SKILLS
Languages: Python, TCL, Verilog, C, C++ Synthesis Tool: Synopsys Design Compiler
Place and Route : Cadence Encounter Layout Editor: Cadence Virtuoso
Power Analysis: Primetime (PTPX), Apache Power Artist Physical Verification: DRC, LVS
Device Simulation: PETE, FetToy (nanohub.org) Digital Design Debug: Synopsys Verdi
Simulation Tools: ModelSim, HSpice Operating System: Unix, Windows

2. Computer Architecture:
 Cache Design: Designed a parametric cache simulator using C++ to design data cache well suited to the SPEC benchmarks. The cache controller implemented two fetch policies - Blocking and Early Restart with Critical Word First; two replacement policies - Least Recently Used (LRU) scheme and First in First Out (FIFO) scheme.
 Tomasulo Algorithm Pipelined Processor Design in C++: Designed a simulator for out-of-order superscalar processor that uses the Tomasulo algorithm and fetches multiple instructions per cycle. Also a branch prediction was implemented using a bimodal Smith Counter. The simulator was used to find the appropriate number of function units and fetch rate for each benchmark.
 Cache Coherence Protocol Simulator: Implemented MI, MSI, MESI, MOSI and MOESI (cache coherence protocols) for multicore processor systems with a bus-based broadcast system in C++ language.
RELEVANT COURSEWORK
Advanced VLSI Design | Advanced Computer Architecture | Physical Design Automation of VLSI Systems | Digital Design with Modern VLSI Device | Digital Systems Test | Computer Aided Design(CAD) of VLSI Systems | Electronic Circuit Analysis and Design | Digital Design | Embedded Systems