1. SHIVANI SAKLANI
Portland, OR | shivaniskln8@gmail.com | Contact No. (971)222-4866 | www.linkedin.com/in/shivanisaklani
OBJECTIVE Seeking a full time position in Hardware Design/Verification/Validation from June onwards.
EDUCATION
 Master of Science in Electrical Engineering Sept 2015 – May 2017
Portland State University, Portland, Oregon Current GPA: 3.62
Coursework: Microprocessor System Design, Digital Integrated Circuits–I, Computer Architecture, Pre-Silicon Validation, Advance Computer
Architecture, SOC with FPGA
 Diploma In Digital VLSI Aug 2012 – Feb 2013
Center of Development And Advanced Computing, Pune, India Grade: A
 Bachelor Of Technology in Electronics and Communication Engineering Aug 2007 – July 2011
Govind Ballabh Pant Engineering College(Uttarakhand University) Percentage: 72%
SKILLS & ABILITIES
 Languages: Proficient in Verilog and VHDL, Fair Knowledge of MATLAB, C, C++, Scripting ( PERL, Python)
 EDA Tools: Questasim, ModelSim, Xilinx Plan Ahead/ISE14.4, Altera Quartus10, Vivado, Virtuoso, SimVision, Verdi, AMBA Designer
 From Work Exp.: RTL Development, Digital Design, Functional Verification, Synthesis, Hands on experience in Static Timing Analysis (STA) and
Placement and Routing (PAR)
PROFESSIONAL EXPERIENCE
 Digital Hardware Intern, Xilinx June 2016 - Dec 2016
Arteris NoC: i. Integrated the Arteris NoC with the already existing design. ii. Achieved timing closure by applying timing constraints and defining false
path in tcl script iii. Involved in the debugging of Arteris IP by testing all the paths in the interconnect through strategically selected verification test cases
PMC Interconnect: i. Designed interconnect for the PMC and IOU subsystem using the ARM’s AMBA Designer CAD tool ii. Build the SV wrapper and
filelist for the PMC and IOU switch iii. Performed synthesis run and lint check for this design
CPM: i. Developed working knowledge of PCIe protocol. Read and understood the architectural requirements of Xilinx’s first implementation of the CCIX
protocol for multi-chip coherency ii. Contributed to interface definition of the CCIX and PCIe Module (CPM) for next gen SOC iii. Utilized existing
automation to generate various software deliverables related to the CPM iv. Developed a PERL script for the RTL automation in PCIEA v. Designed the
interconnect for the CPM block vi.Integrated the PCIE-A core in the CPM block vii. Developed a PERL script for the register database automation in PCIEA
viii. Designed a PERL script for automating the wrapper generation for Arteris ix. Designed the address remap block in CPM
 PROJECT ENGINEER – I, CDAC R & D May 2013 - July 2015
Worked on the hardware implementation of Unified Threat Management (preprocessor unit) at 40Gbps in Kintex-7 board. Primary responsibilities
included:
o Study and Evaluation of different algorithm for preprocessor design
o Designed a signature matching logic using VHDL and PERL. Designed, Implemented and functionally verified Pre-Processor which supports over
1800 SNORT Rules and 3000 signatures.
o Designed the interface environment around the pre-processor unit to interact with the DMA.
o Successfully implemented the Pre-processor block on Virtex-6, Kintex-7 FPGAs and Stratix IV Altera board meeting 40Gbps.
o Done STA analysis particularly location and area constraints and analyzing the critical path in the design.
ACADEMIC PROJECTS
 2- PLAYER Real Steel Wrestling Game May 2016 – June 2016
Designed a 2-player wrestling game using Nexys4DDR boards. Game features: - 2 Nexys4DDR boards connected through UART - Bot selection via slide
switches,bot movement via accelerometer, robot motion logic implemented in Picoblaze - Icons, Timer, VGA controller written in Verilog.
 Verification for a Customized UART using System Verilog Feb 2016 – March 2016
Build the verification environment of a customized UART which was designed using arbiter and FIFO that can handle multiple requests and generate grant signal
to transfer data through UART. Verified the UART using layered testbench architecture. Also, successfully done the coverage for the same.
 5-Stage pipeline ISA for an Application specific-processor Feb 2016 – March 2016
Implemented 5-stage pipeline ISA, with 14 basic instructions (including mod operation) in Python. This was designed to test IDEA block cipher algorithm for
1024 bits with 128-bit encryption key (written in assembly code) to achieve high throughput.
 Satellite Hub Design Nov 2015 - Dec 2015
Designed a wireless satellite hub that can handle the traffic in Verilog. The satellite hub can handle up to 3 locally connected devices and a single satellite link.
The design was implemented to minimize the following benchmark measures: 1. User wait times 2. Communication cost 3. Unit cost
 Combinational and Physical Design Of Standard Cells Sept 2015 - Dec 2015
This project included combinational design using CMOS standard cells which involved rise time, fall time and propagation delay analysis and logical effort
calculation for inverter, AOI and Sea of Gates (SOG) circuits. All this was done using Cadence tool.