1. Swetha Pamudurthi Chandrasekharraju
925 SW 163rd
Avenue Unit 113 Beaverton OR 97006 | swetha2@pdx.edu |+19714443634
Objective
Seeking a Full-Time job opportunity in Digital design, Computer Architecture, Verification/Validation.
Education
 Master of Science in Electrical and Computer Engineering – Dec2016
Portland State University, OR GPA: 3.65
 Course Expertise
System on chip design with FPGA’s
Micro Processor System Design
Digital Integrated Circuits
ASIC: Modelling and Synthesis
Emerging Functional Verification Methods
Computer Architecture
Formal Verification
Post-silicon electrical validation
Low power Digital IC design
High Performance Digital Systems
 Bachelors in Electronics and Communication Engineering – May 2013
Anna University, India GPA: 3.75
Technical Experience
Programming Languages Good in C, C++, x86.
Hardware Languages Proficient in Verilog, VHDL.
Scripting Languages Good in UNIX, PERL, Python.
Developer tools Proficient in Cadence Virtuoso, Modelsim, Questasim, Eclipse, DesignCompiler,
JMP, PrimeTime.
Others Worked on Nexys4 DDR FPGA Board.
Good in Tortoise SVN Control, TLA+
Model Checker, NuSMV ModelChecker,
Oscilloscope.
Work Experience
 Teaching Assistant for Graduate level Digital designclass.
 Teaching Assistant for Graduate level Post Silicon Electrical Validationclass.
 Junior Embedded Developer in HCL technologies, Bangalore,India.
 Experience on Module testing, System testing and requirement based testing(RBT) in Client project CSeries
SPDA, Aero Space (UTAS).
Academic Projects
Designed Duck hunt game on Nexys4 DDR FPGA Board(“Wall of fame” runnerup)
 Designed a game that will score points when the duck is shot. Score increments when there is a hit signal and
number of bullets decrement for every left mouse click. This was achieved by integrating mouse to DDR
board to hit the duck, duck flight paths were designed using Picoblaze.
Design of PDP8 Simulator (ComputerArchitecture)
 Designed a PDP8 instruction set architecture (ISA) level simulator in Verilog, capable of generating memory
trace files, debug file, IO and branch tracefiles.
 Explored the impact of instruction set architecture changes on CPI, kept a track of instruction counts for
various program mixes (or benchmarks) and generated trace files useful foranalysing.
SCAN DFT for digital systems (Digital Integratedcircuits)
 Designed 1-bit adder in Verilog and created an 8-bit adder netlist from 1-bit adder netlist (Used RC compiler).
Created layout for 8-bit adder usingEncounter.
 Inserted scan chains into 8-bit adder, generated test vectors by performing ATPG and tested for broadside,
flush and serial scans. Inserted stuck at faults and verified them. Generated layouts for scan inserted circuits
using cadence.
Design of 8T Register Cell (SRAM) using Cadence Virtuoso and Static TimingAnalysis
 Designed 8T Register cell and verified read/write operations by varying sizes of NMOS and PMOS.
 Performed static timing analysis on adder design. Using encounter RC generated timing reports and fixed
negative time slacks
Project using VELOCE EMULATOR (Emerging functional verificationmethods)
 Developed different modes like standalone, DPI (Directed Programming Interface), BFM (Bus Functional
Model), TBX (Test Bench Express) for a synthesizable RSAencoder/decoder code.
 Used SCE-MI pipes technique to send large data between hardware & software and compared the results
between execution times of simulation andemulation.