1. KSHAMA PARAKH
Parakh Computers, Kampthee line, Rajnandgaon (Chhattisgarh)
Contact: +9176970-93000 Email: kshama.parakh@gmail.com
Career objective: To get a challenging position to design leading edge SoCs, IPs utilizing my
knowledge of Design compiler (Synthesis), DFT, UPF and VLSI.
Experience: Internship at Intel, Bengaluru Duration: June 2015-June 2016
Worked on Synthesis Flow
 Analyzed Impact of UPF on DFT by writing Dummy RTL, UPF and Scan configuration.
 Addressed various tool bugs by writing small test cases for reproducing and fixing the issue.
 Worked on Sequential Vectoring to validate some commands.
 Enabled Scan for a design by writing Scan configuration for all its partitions.
Worked on Regression and Flow Testing
 Added various test cases to regression, analyzed and debugged degradation of results.
 Enhanced a PERL script to capture metrics related to DFT.
 Enabled Cronjob for weekly regression.
 Developed a TCL utility to backup regression area.
 Ported several test cases from project environment to Regression suite.
Automation Work carried out during Internship
 Developed a TCL SCANDEF parser to extract various information like number of Scan
chains, elements per chain, average chain count from the SCANDEF file.
 Developed a PERL script to compare contents of two directories.
 Developed a PERL utility to check missing attributes on the port in design.
Skill Sets
Operating Systems Windows 7, LINUX (Ubuntu)
Programming/Scripting Language C, PERL and TCL
Hardware Description Language VHDL ,Verilog
Tools Design Compiler , Xilinx ISE Design Suite , Visual TCAD
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Major Projects and Seminars
lM.Tech Project: Impact of UPF on Design for Testability (DFT)
Guide: Dr. N.M Devashrayee, Nirma University
 Aim: To analyze the impact of UPF on DFT and observe the parameters like power, performance, area.
 Studied the effect of different strategies like Isolation, Level Shifter and Retention on Scan-Stitching.
 Compared the SCANDEF file with or without UPF and observed the differences.
M.Tech Seminar: Multi-Threshold CMOS (MTCMOS) for Low Power VLSI Circuits.
Guide: Dr. N.M Devashrayee, Nirma University
 Studied MTCMOS technology which provides solution to the high performance and low power design.
 Detailed study of MTCMOS, its operating modes, problems associated and Design issues, Design of
special cells, Design flow and its applications.
 MTCMOS is used in Mobile Computing and other high performance applications.

2. Course Projects (M.Tech)
Specification to Layout development of 8:3 Priority Encoder
 Aim: To design an 8:3 priority encoder using 4:2 priority encoder.
 It’s VHDL Coding, Functional Simulation and Synthesis is done using Xilinx ISE.
 Synthesized design is implemented on Spartan 6 FPGA board. Layout is developed using Microwind.
Implemented Fault Modelling algorithm for verification of VLSI Chip.
 Aim: To implement a fault equivalence algorithm to get the reduced single stuck at faults.
 Its takes ISCAS netlist as its input and has been developed using PERL.
 Collapse ratio and minimum set of stuck-at-faults are its outputs.
Designed TUNNEL DIODE using Visual TCAD
 Aim: To design a Tunnel Diode in nanometer (nm) technology and observe its characteristics using
Visual TCAD and to study its applications.
 Compared the characteristics of Tunnel Diode for different doping densities.
B.E. Project: Ultrasonic Security System
Guide: Prof. Kiran Dewangan, BIT Durg
 Designed a security system that generates an alarm and sends message to owner via GSM module.
 Implemented motion detection algorithm to capture image of an intruder and saves it.
 Enhanced security by incorporating features like high computational speed and password protection.
Academic Profile
Degree Institute/School University/Board Year Percentage/CPI
M.Tech Institute of Technology Nirma University 2016 8.95
B.E. Bhilai Institute of Technology, Durg CSVTU 2014 9.16
HSCE Yugantar Public School CBSE 2010 93.6%
SSCE Royal Kids Covent ICSE 2008 89.8%
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Training and workshops
 Participated in TEQIP II sponsored three days’ workshop on “An Intellectual insight into Analog and
Digital VLSI Design, GEC Gandhinagar.
 Attended a workshop on “Electronic System Design and Manufacturing”.
 Vocational training in Basic Telecomm: Bharat Sanchar Nigam Limited (BSNL), Durg.
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Declaration
I do hereby declare that all the above information is true to the best of my knowledge and I bear the
responsibility for the correctness of the above mentioned particulars.
Kshama Parakh