1. Jayesh Kumar Sharma
Mobile: +91-8105655590
E-Mail id: jayesh10791@gmail.com
PROFESSIONAL EXPERIENCE: --
Organization: Cadence Design Systems
Duration: July 2015 till Present
Designation: Consultant [ IP & Testchip Design ]
Organization: Orange Semiconductor Private Limited
Duration: November 2014 till June 2015 (8 Months)
Designation: Physical Design Trainee.
SUMMARY:-
 Currently working on Chip level Design.
 Comprehensive knowledge of physical design implementation, physical design strategies, and static
timing analysis
 Excellent knowledge of ASIC design flow, digital circuit design.
 Familiar with scripting languages, VLSI designs.
 In-depth knowledge of EDA tools, Verilog HDL.
PROFESSIONAL SKILLS:
Operating Systems Windows XP/7/8, Linux (Redhat, CentOS)
Programming Languages
C
HDL Languages
Verilog
Script language
Perl, TCL.
EDA Tools
Cadence -Virtuoso, RC Compiler, NC launch, Xilinx ISE, Modelsim,
LASI, FPGA (Xilinx-spartan3e, Altera- cyclone) SoC Encounter,
Synopsys – IC Compiler, Prime Time.
PROJECT DETAILS:
Project#1:-
Project Block level
Technology 45nm
GateCount/Macros 90K / 29
Role Complete PNR
Clocks / Frequency
8/ 125Mhz
Duration
3 months

2. Roles and Responsibilities:-
 Responsible for manual floor plan and placement of all 29 Macros and standard
cells.
 Responsible for power planning for block.
 Responsible for removing opens and check connectivity.
 Responsible for maintaining congestion at acceptable level.
 Responsible for fixing timing.
 Responsible for fixing DRC’s and LVS.
 Wrote script for fixing congestion and timing.
Language and tools used Perl, TCL, SOC Encounter.
Project#2:-
Project Block level
Technology 45nm
GateCount/Macros 245K / 45
Role Complete PNR
Clocks / Frequency
8/ 250Mhz
Duration
3 months
Roles and Responsibilities:-
 Responsible for full PNR flow of the block.
 Responsible for static timing analysis.
 Written scripts for performing complete PNR flow.
 Extracting information (WNS, TNS, slack, logical depth, all path information etc.)
from timing report using PERL and TCL.
 Fixing DRVs.
 Fixing connectivity and geometrical issues (DRC and LVS).
Language and tools used Perl, TCL, SOC Encounter.
ACADEMIC PROJECTS
 PG Projects:
Project Title Design of Digital circuits using Constant Delay Logic.
Project Details An effectual method of implementing Arithmetic circuit using Constant Delay (CD)
logic style. Main focus of this logic is to increase speed of typical arithmatic logical
applications.
Project Title A Memory less Pipelining Scheme for High-Performance Digital Systems.
Project Details This research work presents an efficient method of implementing various Arithmetic
circuits using Dynamic logic with memory less pipelining scheme.
Project Title High Performance and Low power Digital Circuit Design Using FTL Logic with
efficient LEAKAGE reduction techniques.
Project Details This research work presents a proficient method of instigating different logical

3. circuits using Feed Through Logic (FTL) style with different leakage current
reduction techniques.
Project Title Design of CISC processor.
Project Details Using Cadence EDA tool (Cadence NC Launch, RC, and Encounter) full custom CISC
processor was designed.

 UG Projects: 

Project Title Gsm Based Home Security System.
Project Details This project deals with study of home security system using laser. This whole system
consists of Transmitter circuit, receiver circuit and light sensitive elements like photo
transistor. The detection signal can be detected on a specific mobile in form of
message by use of HDL coding.
ACADEMIA
Examination University Institute Year Percentage (%)
M.Tech
(pursuing)
Vellore Institute of
Technology
Vellore Institute of Technology,
Chennai
2013 8.03
B.Tech Rajasthan Technical
University (RTU)
Government Engineering
College, Ajmer
2012 65.73
Intermediate/+2 RBSE Govt.Sr.Sec. School GGC 2007 75.54
Matriculation RBSE G.D.M.A.V.M GGC 2005 85.67
PERSONAL VITAE
Date of Birth : 10th July, 1991.
Address (Per.) : E-44 New Jawahar Nagar
Kota -324005.(Rajasthan).
Alternative email ID: Jayesh.kumar2013@vit.ac.in
Languages Known : English, Hindi (Read, Write and Speak) Marwadi (Speak Only)
DECLARATION
I hereby declare that the information furnished above is true to the best of my knowledge and
understanding.
Jayesh Kumar Sharma