1. KANUGANTI RAVI TEJA
H.No: 9-1-1/C/32/A
Defense colony, Langar house,
Hyderabad, Telangana-500008.
Ravifriends.leo@gmail.com
Mobile: +919032893006
CAREER OBJECTIVE
Achieving a dynamic and carrier oriented position in semiconductor industry by utilizing my skills and abilities
that offers professional growth while being resourceful, innovative and flexible.
EDUCATIONAL QUALIFICATIONS
Course Institution University Period of
Study
Aggregate
M.Tech(VLSI) Vellore institute of
technology
Vellore Institute Of
Technology, Vellore
2013-15 7.86
(CGPA)
B.Tech (ECE) Joginpally B.R
Engineering College
Jawaharlal Nehru
Technological University,
Hyderabad
2008-12 73.20%
Intermediate
(MPC)
Narayana Junior College Board Of Intermediate
Education, Andhra Pradesh
2006-08 92.80%
Matriculation Kendriya Vidyalaya No.1
Golconda
Central Board Of Secondary
Education
2005-06 71.60%
TOOLS AND LANGUAGES
Scripting language : PERL
Hardware description language : Verilog-HDL (IEEE Standard 1364-2001)
Pre-layout simulator : NC-launch (Cadence),ModelSim (Mentor Graphic)
FPGA Kits : DE1,DE2 (Altera)
Synthesis tool : RTL-compiler (Cadence), Quartus-II (Altera)
Layout Editor : Virtuoso (Cadence)
Physical design : SOC-Encounter (Cadence)
Electronic circuit package : Tina-TI (Texas-Instruments), Multi-Sim (NI)
Protocols : AXI, AXI-lite, APB, AHB (ARM)
Programming Language : C
AREA OF INTEREST
ASIC design and verification

2. SUMMARY OF CREDENTIAL
 Thorough knowledge of ASIC design flow including both frontend and backend.
 Hands-on experience on Tsmc45nm, Tsmc90nm, and Tsmc180nm technology nodes.
 Ample practice on PERL-automation and Good knowledge of DFT concepts.
 Capable of performing Code-Coverage verification for given specifications and at present started learning
System verilog.
 Worked with DE1 and DE2 Altera FPGA kits belonging to cyclone family.
 Able to solve DRC and LVS issues.
 Familiar with interfacing protocols such as AXI, AXI-lite, APB and AHB.
PROJECTS
1. A HIGH-PERFORMANCE VLSI ARCHITECTURE FOR VBSME IN H.264
Description: Demands for AVC, especially in the area of VBSME (variable block size motion
estimation) has created lot of impact. The proposed architecture supports 3 data flows of scan format
by using an array of computational units and search algorithms in search area of the memory. It
reuses smaller blocks of SAD’s to compute motion vectors of a 16*16 block which leads to 100% PE
(processing element ) utilization. This design is successfully taped out in TSMC 180µm of CMOS
technology. Tools used are SOC encounter, RTL compiler, NC-launch, MATLAB.
2. DESIGN, IMPLEMENTATION AND CODE-COVERAGE VERIFICATION OF AXI-LITE
TO APB BRIDGE
Description: Synchronizing the performance of different IP’s from various vendors using AMBA de-
facto standard bus architecture developed by ARM inc. GDS-II was developed in SOC-Encounter of
Cadence at 180nm technology node using Slow.lib library. Code coverage verification of entire
design was carried out using Checker based methodology in Verilog. Ultimately this project achieved
a code coverage of 73% in NC-launch of Cadence.
3. ADVANCED LOW POWER RISC PROCESSOR DESIGN USING MIPS INSTRUCTION
SET
Description: As the technology shrinking to sub-micrometer technology node, there exists a huge
scope of undesirable hazards in processors. These hazards may lead to disturbance in area, power
and timing which deviate from desired quantities. This paper focuses mainly on solving some of
these issues. In-order to tackle these problems, we are introducing the enhanced version of
Microprocessor without Interlocked Pipeline Stages. Design was synthesized and GDS-II was
developed using RTL-compiler and SOC-encounter of Cadence respectively at 180nm technology
node using Slow.lib library.
4. DESIGN AND IMPLEMENTATION OF FLOATING POINT FFT BASED CONVLOUTION
Description: Performing FFT of two individual signals, followed by convolution and then IFFT of
resultant signal with pipelining approach aiming towards reduced power consumption. This project
had undergone entire ASIC design flow. Design was synthesized and GDS-II was developed using
RTL-compiler and SOC-encounter of Cadence respectively at 180nm technology node using Slow.lib
library. The same architecture had been implemented on DE2 Altera FPGA kit belonging to cyclone
family.

3. 5. DESIGN AND CODE COVERAGE VERIFICATION OF SYNCHRONOUS FIFO-
CONTROLLER
Description: Main objective is to perform code-coverage verification of a black-box for a given
specification. This project achieved a code coverage of 75% in Nc-launch of cadence.
6. DESIGN AND IMPLEMENTATION OF VEDIC MULTIPLER on FPGA and at 45nm
7. ZERO CLOCK SKEW ALGORITHM USING MATLAB
8. LEE’S ALGORITHM FOR ROUTING USING MATLAB
HOBBIES
 Reading articles related to semi-conductor industry, playing cricket and watching movies.
PERSONAL SKILLS
 Flexible, Hardworking, Self-supervising, Punctual, Negotiation and Good team player.
PUBLICATIONS
Our “ADVANCED LOW POWER RISC PROCESSOR DESIGN USING MIPS INSTRUCTION SET” project
got selected for "ICECS 2015" IEEE conference which was held on 26th
and 27th
of February 2015 at Karpagam
College of Engineering, Tamil Nadu. Our paper is going to be published under ISBN 978-1-4799-7225-8
PERSONAL DETAILS
Nationality : Indian
Date of Birth : 25.04.1991
Marital status : Un-married
Father’s name : K. Sudhakar
Languages known : English, Hindi and Telugu
DECLARATION
I hereby declare that the above information and particulars are true and correct to the best of my
knowledge and belief.
Place: Hyderabad
Date: (K.RAVI TEJA)