1. Profile Information
Name: Chandan Merwade Email: chandanmerwade@gmail.com
Phone: 9632548572 Address: TKM Building, kurhatti peta
Gadag-Betgeri 582101
Karnataka
Career Objective
• Seeking challenging assignments as a Physical Design Engineer where i can utilise my skill and
knowledge to be the best of my abilities and contribute positively to my personal growth as well
as growth of the organisation.
Core Competency
• Good Understanding of complete ASIC design flow.
• Good understanding of fundamentals of CMOS theory.
• Good understanding of Physical design flow.
• Efficient in placement of high count macros during Floor planning as well as good
understanding of Power planning, Placement, CTS and Routing.
• Good understanding of Digital design.
• Good in concepts of Static Timing Analysis and efficient in interpretation of timing
reports for Setup and Hold.
• Good understanding of Physical Verification (DRC and LVS) and DFM.
• Good understanding of Design rule violations (max transition ,max and min
capacitance,max fanout).
• Basic knowledge of industry standard formats LEF (layout exchange format), DEF
(Design exchange format).
• Familiar with shell scripting.
• Basic knowledge of Power Reduction Techniques.
• Basic knowledge of RTL coding and verification.
• Hands on experience on Synopsys tools and Cadence tools.
Education Details
Degree Discipline School/College Year of
passing
Aggregate
PG Diploma Advanced Diploma in
ASIC Design - Physical
Design
RV-VLSI Design Center 2015 -
Degree Electronics and
communication
Basaveshwar engineering college,
Bagalkot
2014 61.2%
PUC - Smt.Parvathamma shamanur
shivashankrarappa college
Davangere
2010 55.6%
SSLC SRV Hulkoti (CBSE) 2008 60.5%

2. Work Experience (Internship for 1 Year)
• Advanced Diploma in ASIC Design - Physical Design at RV_VLSI Design centre Banglore
(Duration - 6 months)
• Physical Design Trainer at Sankalp Semiconductors Eklakshya Hubli. (Duration - 6 months)
Roles and responsibilities :
• Trainer for company freshers under complete Physical Design flow.
• Simultaneously worked on Block implementation Rapid Adoption Kit (RAK).
Project Details
Project title Block level physical design of Torpedo subsystem
Institute Name RV-VLSI Design Center, Bangalore.
Project
Description
Technology: 180nm, Supply Voltage: 1.8V, Frequency: 400 MHz, Power Budget: 300mW, IR
drop (VDD+VSS): 5%, Area: 5.9 mm sq, Metal Layers: 6, Number of Macros: 32, Fab: Jazz
Semiconductor, Number of Clocks: 5 (System Clock: 2, Generated Clock: 2, Test Clock: 1).
Tools Used IC compiler for Physical Design and Hercules for Physical Verification.
Duration 6 months
Challenges 1. Placing the hard macros during floor planning with proper spacing and coming up with a
good power plan with acceptable amount of IR drop.
2. Fixing LVS errors (floating ports, total open nets) and DRC errors (minimum area,
minimum spacing and minimum enclosure).
3. Fixing antenna violations by jumping to the upper metal layer or inserting the diode.
Project title Block implementation Rapid Adoption Kit (RAK)
Project
Description
The design in this workshop is a Leon processor. The Leon design is a block level design
with 35K instances, 4 memories, and 1500 IO pins. The library used is a Cadence Generic
45nm library using 9 routing layers. The block implementation Rapid Adoption Kit (RAK)
introduces you to EDI System and walks you through the basic steps in the implementa-
tion flow .This is a flat implementation flow which can be applied to chip level designs as
well as blocks.
Duration 4 months
Challenges 1. Analysing all possible timing paths and resolving setup and hold violation.
2. Analysing of Design Rule violation (max transition ,max and min capacitance,max
fanout).
3. Concept of NDR (non default routing) for CTS (clock tree synthesis) and understanding
how the generated clocks are handled during CTS.

3. Project title
Synthesis and performing static timing analysis
Institute name RV-VLSI Design Center, Bangalore.
Description 1. Understanding STA concepts such as Timing arcs, Input constraints, Max transition,
Clock skew, Critical path, slack, Multi-cycle path, False path, Useful skew, etc.
2. Analysing all four possible timing paths such as Input-Reg, Reg-Reg, Reg- Output and
Input-Output.
3. Applying timing constraints and timing exceptions as per the timing paths.
4. Generating reports of STA for different timing paths and observing violating
paths of setup and hold to meet timing closure.
5. Understanding the techniques to fix setup violation: Gate sizing, Buffering
(increasing drive strength of cell), Cloning, Replacing cells with LVT cells in
data path.
6. Understanding the techniques to fix hold violation: Buffering, Replacing cells with
HVT cells in data path, Restructuring of capturing flop.
Tool Used Primetime from Synopsys
Project title Multi-sensor Image Fusion by combining Wavelet (idwt) and PCA
Institute name Basaveshwar Engineering College, Bagalkot
Description The image fusion is done between different images which are not clear and which are
blurred,image fusion is done by combining WAVELET(idwt) and PCA(principal component
analysis)by this we will get clear and clean image.
Tool Used Matlab
Challenges Responsible for creation of methodology of IMAGE FUSION by combining the PCA and
WAVELET.