1. Karnika Sharma E-703, Neelpadam-1
Sector-5, Vaishali, Ghaziabad
DOB: March14,1990 |karnika.sharma14@gmail.com| +91-8285737732
Career
Objective
Seeking a challenging position in Semi-Conductors / EDA sector that will enable to utilize
my experience & organization skills in enhancing overall efficiency of related activities
thereby contribute towards business excellence.
Work
Experience
Current:
Organization: ATRENTA (I) Pvt. Ltd.
1st
October 2014 - Ongoing
Position: Software Engineer Trainee
Job Description:Workingina Research& Developmentteam forSpyglassPhysical Tool asa
Software Engineer.
Professional
Summary
6+ monthsof technical experience asa Software Engineer.
Working experience in analyzing requirements and design solutions.
Proficient in HDL languages (Verilog, System Verilog) along with VLSI main concepts.
Working experience on Project Version management using GIT tool.
Workingexperience inusingdifferentEDA tools SynopsysDesignCompiler, ICCcompiler,
Mentor GraphicsIC station, Spyglass,SpyglassPhysical,CadenceEDI,Primetime andsimulators
like ModelSim,NCSim.
In-depthknowledge inLow powerVLSIdesigning,CMOSdesignprocess, Physicaldesign
algorithms,StaticTimingAnalysis,ASICFlow,RTLDesigning.
Workingexperience inTCL,shell,Perl and Python scripting and C, C++ programming language.
Developing,testing,troubleshootinganddebuggingof the application.
Technical
Exposure
Software/Hardware
Languages
C, VerilogHDL,VHDL,C++, Basicsof SystemVerilog
OperatingSystems Unix/Linux/Solaris,Windows
Tools
Tanner Tools v13.1, ModelSim6.4a, XILINX ISE Design suite,Mentor
Graphics IC Station, COMSOL 4.3b, MATLAB, Spyglass Physical,
Synopsys Design Compiler.
Scripting language Shell Scripting,TCL, Perl,Python.

2. Project
Experience
Academic
Projects
Project Name:SPYGLASSPHYSICAL TOOL
Organization: Atrenta
Team Size:15
Role: Software Engineer
Role & Responsibilities:
Responsible forthe followingtasks:
 Involved in the process of requirements gathering and solution design.
 Developingand defining Spyglass Physical tool’s rules and its required parameters.
 Testing and troubleshooting the application.
 Workedon Multi Vddconcepts, Multi thresholdconcepts, Librarycharacterization
usedinsynthesis.
 Considerationof multiple voltage domains/Power domains using UPF/CPF formats.
 Pgpin and Tech layers classification in slf and lef files.
 Vtgroupanalysis(Librarygroupthresholdmappingandcell groupthresholdmapping).
Project Name: Implementation of ROM-less Architecture of direct digital frequency
synthesizer using Pipelined accumulation
Duration: January 2014 – July2014
Team Size:2
Role:Verilogcoding,synthesisandverificationof equationsusingMATLAB
Technologies:ModelSim, Xilinx ISEDesignSuite,MATLAB2013a
Description:
Periodic signals are generated digitally at desired input clock frequencies using phase
accumulation (including pipelining), rather using the memory usage for phase to amplitude
conversion, approximation techniques are employed. This results in area and time efficient
hardware. Implementation is done using Verilog HDL and MATLAB 2013a and synthesis is
carried out on Xilinx ISE 14.3.
ProjectName:FPGAImplementationofMontgomerymodularexponentiationforpublickey
Cryptography
Duration: June 2013 – December2014
Team Size:2
Role:Verilogcoding&implementation
Technologies:ModelSim,Xilinx ISEDesignSuite
Description:
Montgomerymodularmultiplicationisthe basisof modularexponentiationusedin several
public key cryptosystems. The goal is to implement an efficient and less time consuming
Montgomeryalgorithmforfastcomputations.The implementationiscarriedoutusingVerilog
HDL. Synthesis was done by the help of Xilinx ISE Design Suite.

3. Strengths A spirited teamplayer
Verygood leadershipand motivational skills
An appetite forlearning new thingsandtechnologies
An abilitytounderstandclientrequirementandprovide the bestsolution
A keenobserverand fast learner
Achievements GATE – 2012 in EC (Score / AIR): 434 / 7981 (Out of: 176944)
Secured2nd Rankin Uttar Pradeshand 11th Rank inall overIndiain International Informatics
Olympiad (2006)
Presented a Research Paper in National Conference on recent technologies in Electronics
(NCRTE-11) on the title Recent Advancement in DBIST
Education Master of Technology
Centre of DevelopmentandAdvancedComputing(CDAC),Noida.
2012-14 | 82.5%
Bachelor of Technology
Gautam BuddhTechnical University,U.P
2007-11 | 77.5%
XII (C.B.S.E Board)
D.A.V PublicSchool,Meerut,U.P
2006-2007 | 86.8%
X (C.B.S.E Board)
D.A.V PublicSchool,Meerut,U.P
2004-2005 | 85%
Personal
Details
Email ID : karnika.sharma14@gmail.com
Status : Single
DOB : 14-March-1990
Address : E-703, Neelpadam-1,Sector-5,Vaishali,Ghaziabad.
Contact No: +91-8285737732
LinkedIn :in.linkedin.com/pub/karnika-sharma/76/82/74/
Declaration:
I hereby declare thatthe above-mentionedinformationistrue tothe bestof my knowledge.
KarnikaSharma