This document contains a summary of Iyyappan B's resume. He has over 2 years of experience in FPGA and RTL design. He has skills in Verilog/VHDL, Xilinx tools, C/C++, and has worked on projects involving motor control, solar tracking, health monitoring, and cryptography. He has a B.E. in ECE and is currently working as a VLSI Programmer/Engineer.

1. IYYAPPAN B
2 years 5 month Experience in FPGA and RTL Design
15/9, Arul prakasham st, Gandhi Nagar, Mobile: +91-8015101161
Ekkattuthangal, Chennai-600032. Email: iyyappan551@gmail.com
Objective
Seeking a position with an organization where I can contribute my skills as a Design Engineer in
VLSI for organization’s success and synchronize with new technology while being resourceful, innovative
and flexible.
Summary
• Around 2.5 years of experience in Digital system Design and RTL Design using Verilog HDL
• Good experience writing coding with Verilog/VHDL language
• Expertise in working with Xilinx, Modelsim, Tanner EDA and HFSS by Ansoft.
• Working knowledge of programming C and C++.
• Very good experience in Xilinx ISE, Xilinx EDK, Xilinx system generator, Schematic CMOS
Design, IP cores, Digital Signal Processing Systems and RF Antenna Design using HFSS.
• Hands on experience in working on field-programmable gate array such as Spartan 3, Spartan3E and
communication protocols like SPI, I2
C, UART.
• A highly motivated and strategically focused performer
• An effective, innovative professional with strong analytical and problem solving skill
• An excellent multitasking ability with outstanding organizational skills
• Comfortable and self-confident in a diverse population
• A passion for professional ethics and adherence to organization’s core values
• Excellent people handling skills
Skill Set
 Software Suites : Xilinx (ISE, System generator, EDK), ModelSim,
Tanner EDA and Altera FPGA Design Tools.
HFSS by Ansoft, MATLAB (Beginner).
 Programming Languages : Verilog, VHDL, C and C++.
 Communication Protocols : UART, SPI, I2
C.
 Platforms : Windows xp, 7, 8 and 8.1.
 Hardware Expertise : FPGA Spartan 3, Spartan 3E, Spartan 6, Altera DE2
Board.
Professional Experience:
Vee Eee Technologies solution Pvt. Ltd, Chennai Nov 2013-Sep 2015
VLSI Programmer/Engineer
Vee Eee Technologies solution Pvt. Ltd is a well-known company involved in Design & Manufacture of
all Electrical, Electronics, Mechanicals and all Computers based projects and all software projects in and
around the country.
• Focused on Full Life Cycle of VLSI Devices Development. Trained and practiced numerous design
and programming strategies, which include the FPGA programming and CMOS schematic and
Layout designing.
• Design and development in the areas of Communication, Image Processing, Low Power Design,
Peripheral Devices Interfacing with FPGA.
Currently working as a VLSI Programmer/Engineer at Modinx Technologies Solution Pvt Ltd,
Thirunelveli from Oct-2015 to till date.

2. Academic Profile
Secured 70.5% in B.E., ECE at E G S Pillay Engineering College, it applied to Chennai Anna University.
Projects Handled
1. Speed Control of BLDC Motor Using Fuzzy Logic in Fpga
This project is a Wheel chair controlled system for physically disabled persons using FPGA. In this
the BLDC motor is used for the locomotion and accelerometer sensor for finding the position of the patient.
The speed of the BLDC motor is controlled by using the Hybrid Fuzzy logic PI controller. The accelerometer
sensor is used as fall detection sensor.
Responsibilities:
• Developed Hybrid Fuzzy logic and PI Control system using Verilog.
• Developed I2
C communication program in Verilog for accelerometer.
• Keypad interface for input set speed.
Tools used:
Spartan 3E (XC3S100E), Xilinx 12.4, BLDC motor of 100rpm and accelerometer.
2. Solar Panel Tracking System using FPGA
In this project, LDR’s focus the light intensity of the sun and its direction. By using LDR’s assumes
the sun direction and switch the relay to control the motor’s the direction of rotation. The ADC MCP3208
used to find the value of LDR.
Responsibilities:
• Developed RTL code of solar panel tracking.
Tools used:
Spartan 3E (XC3S100E), Xilinx 12.4, ADC MCP 3208, DC motor and LDR’s.
3. Health Monitoring System Using Fpga
Developed a user friendly health monitoring system for patients. This system monitors the patients
ECG, blood pressure, Heart beat and Temperature and it transmits the patient’s condition through the GSM
modem and that can be monitored using LABVIEW.
Responsibilities:
• Developed a QRS complex detection algorithm using the VHDL, and sensor interfacing for
Heartbeat, temperature and blood pressure to FPGA.
• GSM Modem interfacing for automatic messaging system.
Tools used:
Spartan 3E (XC3S100E), Xilinx 13.2, GSM Modem, Serial communication and Lab view.
4. Crypto cores
Implementation of crypto cores which consists of Advanced Encryption Standard (AES), Data
Encryption Standard (DES). Each has different input lengths as 128 bits and 64 bits. AES has operations Sub-
Bytes, Shift rows, Mix-Columns, Add Round. DES consists Initial Permutation, Function operation, Inverse
Permutation. The core which operates both Encryption and Decryption depend upon user. All the blocks
developed in Verilog.
Responsibilities:
• Developed RTL code of AES, AES Blocks, DES, and DES Blocks using Verilog.
• Simulation and implementation on Fpga Saprtan 3E using Xilinx ISE.
Tools used:

3. Spartan 3E (XC3S100E), Xilinx 12.4 and Modelsim.
5. DSP Cores
Design and implementation of three SoC cores, which implement the DSP functions: FIR filter and
FFT. The inputs and outputs are represented in fixed point representation. The three cores are compatible with
the SoC bus, and they were described using generic and structural Verilog. In-system hardware verification
was performed by using a SoC synthesized on a Xilinx FPGA. Tests showed that the designed DSP cores are
suitable for building SoC based on the processor and the bus.
Responsibilities:
• Developed RTL code of FIR filter and FFT using Verilog.
• Synthesis and implementation on Fpga Saprtan 3E using Xilinx ISE
Tools used:
Spartan 3E (XC3S100E), Xilinx 12.4, Modelsim,
Co-Curricular Activities:
 Presented a Paper titled ’FIR Filter Design’ at International conference Organized by Dept. of
E.C.E. E G S pillay Engineering college.
 Published a paper titled “High Speed and reduced area 16 bit Vedic multiplier using CSLA” in
IJARET.
 Published a paper titled “High Efficient FIR filter with Advanced Vedic Multiplier used
reduced CSLA” in IJAER.
 Digital system design using VHDL conducted by NG technologies.
Personal Strengths
 Hard working and good at team work.
 Rapid at learning things and having innovative ideas.
Personal Details:
Date of Birth : 27th
Nov 1990.
Gender : Male.
Languages Known : English, Tamil.
Father’s Name : V Balasubramaniyan.
I hereby declare that the above mentioned details are accurate and true to the best of knowledge.
Date:
Place: Chennai B.Iyyappan