1. SHAH HET
email: hetshah8891@gmail.com
contact num: +917411682612
Overview:
 Currently,working at eInfochips with 1 year 10 months of relevant
experience.
 Worked on a top level chip design at eInfochips with job responsibilities including floor
planning,power planning,slew fixing,timing cleaning, LVS, ESD protection, DRC, CPF,
LEC, clock structure optimization, antenna checks and offgrid checks and developing
perl and tcl scripts to improve the flow.
 Completed project on physical design of two projects at eiTRA( from RTL to timing
closure using Design Compiler,ICC and Prime Time).
Educational qualifications.
Examination University/Board CPI Year
B.E GTU 8.8 2013
H.S.C G.H.S.E.B 82.3% 2009
S.S.C G.H.S.E.B 89.7% 2007
Proffesional skills:
 RTL to netlist conversion (Design Compiler)
 Placement and routing(ICC,Encounter)
 Prime time
 Voltage Storm (Power analysis)
 GDS merging and editing(Laker)
 LVS and DRC (Calibre)
 Conformal Low Power tool
 Perl and TCL
 Verilog,

2. Project title : FSC0AA086A
Specifications : 45nm project with 0.245GHz highest clock frequency and 28 macros,5 clocks.
Role: Design engineer
Team Size : 5
Synopsys : This is a toplevel chip with transreceivers requiring manual routing for certain
analog signals due to timing criticality and heavy loading. The major challenges were to
freeze the floorplan and clean congestion.
Roles and Responsibilities :
 Floorplanning and proper IO pad placement taking care of different power domains.
 Designing the power structure and meeting IR drop analysis.
 Reducing the congestion in the core area.
 Meeting timing requirements.
 Fixing slew in the design.
 Analog net routing to reduce net length
 Maintaining global skew at 7ns.
 Generating “cover cell” and giving suggestions for the changes in GDS generation flow.
Project title : CICADA
Specifications : 90nm technology with 100 Mhz frequency,1 PLL,40 macros and 4 sub blocks.
Role:Design engineer
Team Size : 5
Synopsys : This was a full chip project where we had 4 blocks.The major challenges were LVS
and timing for certain IPs in the chip.
Roles and Responsibilities :
 Cleaning LVS
 Analysing ESD flow debugging ESD issues and passing ESD.

3. Project title : FSC0AA008A
Specifications :65nm technology,2.08M instances,270 macros,3 PLL,5 DDR,58 clocks (0.7GHZ
max freq)
Role:Design engineer
Team Size : 5
Synopsys : This is a project where we are trying to see the results with 70% utilization and 80%
utilization. The major issue is the localized congestion in the floorplan.
Roles and Responsibilities :
 Changing the floorplan without touching the analog blocks to reduce the congestion in
design.
 Proper power planning to reduce the dynamic IR drop in the design.
 Preparing the script to place the user specified levels of flipflops within user specified
distance from its IO pins.
Project title : Mosquito Low Power
Specifications :90nm low power, 1.4M gate count,4 DDR, 5 PLLs and 1 DLL,77 clocks (max
freq 1 Ghz)
Role:Design engineer
Team Size : 5
Synopsys :
FZC0ZA024A is a low power chip with two power domains one of which can be switched off as
and when required. It had 7 metal layers and the major challenges faced was of ESD protection
and reducing the power mesh resistance. Also designing the CPF file for two digital domains
with analog devices on chip was a challenging task.

4. Roles and Responsibilities :
 Power planning at the full chip level and reducing the effective resistance of the power
grid.
 Passing LVS,DRC,ESD,LEC,offgrid checks,antenna checks.
 Also worked to modify the clock tree specification file for proper clock structure.
 Worked on the CLP flow to ensure that the design met CPF file requirements and made
modifications as required.
 Reduced the resistance of the analog supply given to the IP in the design
Project title :- POWER PC
SYNOPSYS: A project at eiTRA for physical design of POWER PC chip. POWER PC
which is designed using IC compiler at 90nm technology, contains 15k standard cells and a
clock of 200 MHz frequency.The placement of a single large macro in an entire chip gave a
good learning experience of how placement effects routing and timing.
Roles and Responsibilities:
 Generating the verilog netlist from RTL code using Design Compiler.
 Proper macro placement,power planning,CTS generation, routing and meeting the timing
requirements.
Project title :- Chiptop
SYNOPSYS: A project at eiTRA for physical design of Chiptop chip. It contains 64 macros
and 10k standard leaf cells. It has been designed at 90nm technology with a clock frequency
of 142 MHz.

5. Roles and Responsibilities:
 Generating the verilog netlist from RTL code using Design Compiler.
 Proper macro placement,power planning,CTS generation, routing and meeting the
timing requirements.
 Also designing a proper SDC for the project to decide at what highest frequency the
chip can work.
Tools used: Design Compiler,ICC
Project title :- ALU design
Hardware Description Language: Verilog
SYNOPSYS: A project at eiTRA in a group of three in which we designed an ALU with two
8 bit inputs,3 selection lines,8 bit output and 8 different logical and arithmetic functions.
Project title: Verilog to System C conversion.
Scripting Language: Perl
SYNOPSYS: A project at eiTRA in a group of three in which we designed a perl script that
reads a verilog design and converts it to a system C file using various regular expressions.
Project title: Automatic control of street lights using ZigBee
SYNOPSYS: This was a final year project in which using an AT89C51 microcontroller we
designed an automatic system that could switch lights through a laptop using ZigBee module
and switch lights as per ambient light intensity.Also designed a software in VBA to control
the lights from a laptop.
Achievements.
 Got 2 awards for good execution of project.
 Leaded as the head of the technical events of E.C department in college
techfest.21’Fahrenheit.
 Co-ordinated and managed a microcontroller event in the college techfest.

6. Personal Information.
Name: Het Atul Shah
Recent address: T5,Sri Krishna P.G,
Opposite Kormangala Police station,
8th block,Kormangala.
Bangalore -560034.
Date of birth: 8th
Aug,1991.
Hobbies: reading magazines, playing strategic games and chess.
Languages known: English, Hindi, Gujarati.