Tulika Gupta is seeking a professional growth opportunity in an established organization. She has over 5 years of experience in DFT engineering roles. Her experience includes tasks like logic equivalence checking, ATPG pattern generation, test vector validation, simulation, and more. She has worked with tools from Cadence and Synopsys on various chip projects with technologies ranging from 28nm to 40nm. Tulika holds a PGDM in Marketing Management and a B.Tech in ECE. She is proficient in English, Hindi, and Marathi.

1. Tulika Gupta
tulika_s.gupta@yahoo.co.in; tulika8002@gmail.com
+91-8237387268, +91-8735070970,
20-H, Ejipura, Bangalore, Karnataka -560047
~~~~~~~~~~ PERSONAL STATEMENT ~~~~~~~~~~
Self-motivated, Hard-working, seeking for opportunity of professional growth in a well-
established organization having strengths other than technical.
o Good to communicate and co-ordinate with cross functional Team.
o Organized & can handle multiple tasks simultaneously.
o Able to Mentor Junior engineers.
o Good at business Communications.
o Good at customer relationship management.
o Good Management skills though learning is in progress.
o Having knowledge and skills for devising implementable industrial marketing
strategies.
o Good at service management and Marketing.
~~~~~~~~~~~ WORK EXPERIANCE ~~~~~~~~~~~~
Total ~5 years of Experience
o Multiple successful tape-outs.
o Hands on Experience on SHS Tools From Synopsys.
o Hands on Experience on generation of SHS wrapped cores, and Integration.
o Hands on Experience on SHS Pattern generation using yield accelerator.
o Experience in RC compiler, DFT Compiler, Tetramax, VCS, Verdi
o Experience in JTAG patterns generation with BSD compiler as well as manually
o Experience in test vectors validation with or without timing
o Experience in simulation of test and functional pattern through VCS
o Experience in debug simulation through DVE
o Experience in LEC with Encounter Conformal and Formality both
o Experience in MBIST insertion and Pattern generation with Nebula
o Basic work done in scan insertion
o Rich experience in ATPG pattern generation/Compression with Tetramax
o Rich experience in ATPG pattern generation with Encounter-Test.
o Experience in EVCD/VCD patterns generation and IP test validation.
o Experience in IP test validation using real timings( With SDFS)
o Experience of both Cadence & Synopsis tools
~~~~~~~~~~ EMPLOYMENT HISTORY ~~~~~~~~~~
o Working as DFT Engineer at Sasken Communication. Ltd from June 2015 –till
Present
o Worked as DFT Engineer at e-Infochips Pvt LTD, Ahmedabad Since Mid Oct, 2012-to
June-2015
o Worked as DFT Engineer at Wipro Technologies Pvt Ltd. Pune from May 2011 to Mid
Oct, 2012.
~~~~~~~~~~~~~~ EDUCATION ~~~~~~~~~~~~~~~~
• PGDM: Marketing Management (Exec.) 2015-16 –( SIBM, Pune ) – 8.24 cgpa

2. • B.Tech (ECE): RTU, Kota -- 72.9%.
• CBSE – IISCE -- 79.8%
• CBSE – IISE -- 79.6%
~~~~~~~~~~~~~~~ KEY SKILLS ~~~~~~~~~~~~~~~
Operating Systems Linux/UNIX, Windows
Programming Languages C,C++
HDL Language Verilog, VHDL
HVL System Verilog
Scripting languages Perl, XML, Tcl
EDA Tools
RC/DC compiler, DFT Compiler, DFTMax, VCS-MX, Formality, EC, Encounter
Test, GT/PT, NC verilog, TETRAMAX, BSD-compiler, Nebula, Simvision, DVE,
LEC,
Languages
English | Hindi | Marathi (Proficient) | Kannada (Beginer)
Project #1
Project Chip1, chip2 ,Chip3,Chip4,Chip5,Chip6,
Technology 28nm, >100X compression, ~11M gate count
Role Test and Validation Team Member
Description
• Tasks handled during the project :
1. Logic Equivalence Check
2. ATPG SSA and TR coverage targets 99% and 85%
3. DRC cleanup, Pattern validation
4. Tester support for Silicon bring up
5. Design team interaction for Coverage and Validation
Tools used TETRAMAX, VCS, Verdi, EC- LEC; DVE, Client specific utility,
Project #2
Project Chip7
Technology 40nm
Description
6. DFT task handled during the project :
7. MBIST pattern generation and Validation.
8. Generation of MBIST diagnostic test vectors and validation.
9. Pattern Validation of MBIST and other IP with or without timing.
10. Timing check simulation and debugging for MBIST test vectors.
11. Logic Equivalence Check ( Pre DFT Vs Post DFT netlist.)
12. Logic Equivalence Check ( Pre BISTed Vs Post BISTed netlist.)

3. 13. JTAG Pattern generation and Simulation.
14. Promotion of Block level STIL Patterns to the top level STIL Pattern.
15. Perl scripting for promotion and other tasks.
16. Chip level mapping of USB - IP test pins.
17. Perl Scripting for SOC pin map generation in client flow.
18. STIL conversion of IP level test vectors to SoC level.
19. Test pattern validation for USB – IP with or without Timing.
20. Timing checks and debugging of USB test vectors.
Tools used BSD compiler, VCS-MX, Nebula, Design vision-DVE, NDM flow of client,
vcs, EC-LEC,
Project #3
Project Chip8
Technology 40nm
Description
• DFT task handled during the project :
1. Mixed IP test bench generation and validation.
2. IP test using SHS Star Hierarchal System.
3. IP test environment using STAR builder and Integrators.
4. Pattern generation using SHS yield accelerator.
5. ATPG test pattern generation using Encounter Test.
6. Test vectors simulation using NCV and debug with Simvision.
7. EVCD Pattern generation.
8. Test validation and debug with real timings.
9. RTL test as well as Gate level test of IPs and design.
10. Regression, VPlan etc.
Tools used NCverilog, Encounter Test, Simvision, SHS-YA, Eplanner,
Project #4
Project Chip9
Design spec. Around 6 million gates
Role Team member handling the Individual block
Description
• DFT tasks handled during the project :
1. DFT Implementation, Scan Implementation and Synthesis, BIST Synthesis.
2. XML and SDC generation.
3. JTAG Implementation.
4. MBIST implementation & synthesis.

4. 5. Pre-layout STA.
6. Achieving 100% Scan-ability and > 86% clock gating.
7. Merging ( achieving > 96% merging of Single bit register to multibit register )
8. LEC (pre and post DFT verification).
Tools used RC compiler, GT, EC, BSD Compiler, Aprisa
Project #5
Project Chip10
Technology 40nm
Role Team Member/ Block Owner
Duration 3 months
Description
• DFT task handled during the project :
1. Scan Insertion & Implementation.
2. DRC fixing and achieving coverage of 99.1%.
3. ATPG and test vector generation with TetraMax.
4. Test Pattern compression.
5. Test vector Validation.
Tools used VCS-MX, DC/DFT compiler, TETRAMAX, Design vision-DVE
~~~~~~~~~~~~~ ACHIEVEMENTS ~~~~~~~~~~~~~
• Core Value Awards for disciplined execution and delivery of projects.
• Best Team Award for Avago.
• Pat on the back multiple times.
~~~~~~~~~~ PERSONAL INTERESTS ~~~~~~~~~~
Gardening | Reading | Web Surfing | Cooking |