1. Suhruth pallerla
+91-7022570446
pallerlasuhruth08@gmail.com
Objective: To acquire a challenging position in physical design domain, where I can utilize my skills and
education.
Experience Summary:
 Currently working with Broadcom as IC Design Engineer.
 1.3 years of experience in Physical Design.
Work Experience :
Broadcom Corporation, Bangalore
Design Engineer, Infrastructure and Networking Group
 Have ownership of a physical design block in 16nm chip and responsible for complete closure on all
aspects of PD/STA/LEC/PV and power signoff requirements.
 Actively supported in Tcl scripting for 16nm FF+ physical design team.
 Worked on timing and congestion aware placement .
 Built Clock Tree with proper CTS constraints to have the better clock skew and latency.
 Performed block level timing closure and chip level cross talk, noise analysis.
 Effectively worked with all the individual block designers to fix their respective ends of the timing paths
and made recommendations on various types of timing fixes.
 Performed IR/EM checks on design and solved the design issue with respect to IR and EM.
 Performed Formal equivalence check (LEC) at block level by using Cadence’s conformal tool in between
pre P&R and post P&R netlist.
Summary of Skills:
 Worked on all aspects of "Netlist-to-GDSII" which includes floor-planning, Placement, CTS, routing,
STA, power analysis, formal verification and Physical Verification related activities.
 Thorough understanding of ASIC backend design methodologies and verification flows.
 Exposure to technology node 16nm and have experience with EDA tools from ATopTech, RedHawk,
Mentor graphics, Synopsys and Cadence Conformal.
 Have sound knowledge on PD, STA and Physical Verification.
 Responsible for fixing setup and hold violations and managed the timing closure of all the paths in that
unit before tape-out.
 Have good work exposure in multi-million gate implemention.
 Worked on multi clock domain, multiple instantiated blocks and rectilinear blocks.
 Managed to work on more than 3 designs at a time.
Areas of Expertise
 Physical Design.
 STA signoff timing closure.
 Power Analysis.
 Physical Verification.
 Good at scripting in Tcl and Perl.

2. Academic Project Details:
 Project Title : Glitch Free Clock IP in VLSI.
 Duration and Place : 2014 December – 2015 May (6 months) at Broadcom Corporation, Bangalore.
 Description : For avoiding the malfunctioning of blocks in IC design, a switching circuit is proposed that
operates at 100 MHz with 17 uw power consumption known as Glitch Free Clock IP in 16nm
Technology node.The design is done with complete PNR flow starting from "Netlist-to-GDSII"
which includes floor-planning, placement,CTS, routing, STA, power analysis, formal verification
and Physical Verification related activities.
Education:
 Bachelor of Technology from CVR College of Engineering, JNTU, Hyderabad, 2015 (85%).
 Intermediate (10 + 2) from CV Raman Junior College, 2011 (95.3%).
 S.S.C from Sri Krishnaveni talent school, 2009 (91%).
Academic Achievements:
 Secured 153rd rank in state level competitive exam APRJC after my 10th standard.
 Secured state level 8th position in intermediate 1st year.
 Topper of school in 10th class.