1. RESUME
Basavanthrao A. M
#26/16, 2nd
Floor,
2nd
Main Road, Marenahalli,
Vijaynagar,
Bengaluru- 560040
brao78@gmail.com
Mobile: 9481776326
Objective: To work in cutting edge technologies in VLSI industry and to contribute to the
success of projects with best working methodologies.
Primary Technical Skills
Languages VHDL, Verilog, C, PSL, e, System Verilog, C++
Scripting TCL, Perl, Shell, Make
Tools
VCS, Modelsim, Mesa, Specman, Design Compiler, NcVerilog,
Incisive Formal Verifier, SixthSense ,ClearCase, SVN, Microsoft
Visual Safesource, PerForce
Domain
Knowledge
I2
C, I2
S, APB, AHB, AXI 3.0, AXI 4.0, AIB2, PCI, OCP, PCMI, Flash
memory , SD-DDR RAM, Video encoder, Gigabit Ethernet, CGMI,
XGMI, MAC
OS Linux, Windows
Methodologies eRM, Fusion (IBM), UVM
Current
Designation
Lead Engineer at Sevitech Systems Pvt. Ltd
Qualification B.E (Electronics & Communication Engineering)
Experience
Summary
• 10+ years of experience in VLSI Front-End design, Functional
Verification using VHDL, Verilog HDL, C++, ‘e’ and SystemVerilog.
• Hands-on experience in Formal Verification in IP/SOC using PSL.
• Used verification methodologies such as eRM, Fusion, UVM
• Currently working as Lead Engineer at Sevitech Systems Pvt. Ltd
since April 2014.
• Worked as Staff R&D Engineer at IBM since June 2011.
• Worked as Senior R&D Engineer at Mirafra Technologies Pvt. Ltd
since May 2010.
• Worked as Module Lead at MindTree Ltd since December 2005 to
April 2010.
• Worked as Design and Verification engineer at iFlect Technologies
from 2004 May to November 2005.
2. Projects Executed
Project GH16 SOC
GH16 is a system on chip for mobile phones.
Tools Ncsim Simulator
Languages System Verilog, Perl
Role • NOC RTL integration and Testbench setup from scratch.
• Architecting and coding of performance logger in System Verilog to
get bandwidth, dynamic bandwidth, latencies across module
boundaries.
• Architected and coded Perl scripts to process and facilitate the
performance parameters for seem integration to web based reporting.
Project NOC studio
NOC studio (Network on Chip) is a tool that delivers a RTL configuration
by connecting different versions AXI, AHB, APB bridges as per the
customer inputs. It has a database of all possible bridges (RTL) which it
uses to rig up. It also creates a Testbench to do a sanity check. This
overall setup helps in faster to market goal of VLSI products
Tools Ncsim Simulator
Languages System Verilog, Perl
Role • Specification study of AMBA protocols
• Specification study of AXI to APB and AXI to AXILITE bridges,
• Functional coverage and code coverage for AXI to APB bridge,
including review plan and coding. Identify holes and specify new test
to achieve 100 % coverage
• Take ownership of AXI to AXILITE bridge unit level Testbench for
updating and maintaining. New feature addition for randomization of
more variables
• Port tests from APB bridge and modify to AXILITE Bridge.
• Micro-architecting end-to-end checker for AXI to AXILITE bridge and
coding and verification
• Update environment scripts to include these bridges in NOC level
verification
Project Programmable Sequencer Element (PSE)
PSE is a sub block of Kraken chip which is a I/O for Z processors. PSE is
a mini-processor which helps Kraken in off-loading I/O functions from Z
processors
Tools Mesa Simulator,
Languages C++ , Fusion Methodology
Role • Specification study of Kraken and PSE
3. • Ramp up on C++ and Fusion methodology
• Feature identification and Testplan preparation for GMP
• Testbench frame work creation from scratch and regression setup
• Review Testplan items
• Owning Register modeling and verification strategy, coding
• Writing tests for Instruction Verification MOV,ALU, STORE,LOAD
• Running and debugging the failures.
• Error Injection and checking architecture and frame work. Defining
components and dependency.
Project Magnus Verification
Magnus is a 136 link to 136 link chip router with complex arbitration logic,
highly optimized quad based hardware by using Time Slice concept, a
timer based winner selection. It accommodates various errors scenario
correction, handling and reporting.
Tools Mesa Simulator, Sixthsense
Languages C++ Fusion Methodology, Perl, PSL
Role • Specification study of Magnus.
• Feature identification and Testplan preparation
• Review Testplan items
• Writing tests for various GMP/BMP.
• Running and debugging the failures
• Code coverage closure
• Defined strategy, coded environment, checkers and verified packet
Arbiters using SixthSense Formal tool
Project 100G/120 G MAC Verification
CMAC is a single port MAC for interfaces running at 100G/120Gb/s.
CMAC interfaces to three WarpCores through the External MLD module.
CMAC can operate in either CGMII mode (8 byte SOP alignment) or
XGMII mode (4 byte SOP alignment) for the defined rates of 100G/120G
Tools VCS
Languages System Verilog, Perl
Role • Specification study of 100G, 120G XGMII protocol.
• Study the specification 40G MAC specification and changes for
100G/120G
• Checker updates, BFM updates, test configuration updates
• Running and debugging the failures
• Code coverage closure
Project Gigabit Ethernet eVC
This eVC supports MII, GMII, XGMII interfaces in active and passive
modes
4. Tools Specman, Perl, Ncsim, SVN
Languages e, Perl
Role • Specification study of MII, GMII, XGMII protocols
• Understand pre-existing environments for MII, GMII, XGMII
• Verification plan and architecture for a combined eVC.
• Unified eVC by doing the necessary changes and addition to the
existing code
• Functional coverage plan updation and cover points implementation
• Verification environment for eVC usage with a DUT
• Running the tests and debug
• Coverage Closure
Project GEMAC VIP
A gigabit Ethernet verification VIP solution to verify Medium Access
Control DUT
Tools VCS
Languages SystemVerilog, Perl
Role • Specification study of GEMAC
• Identifying the Functional Cover points.
• Coding the cover points in System Verilog
• Running the tests to achieve 100 % Functional coverage
Project Digital RF Processor (DRP)-is dominantly digital CMOS 3G transceiver. It
is a standalone transceiver with on chip power management in 45 nm
CMOS technology.
Tools Modelsim, Specman, Clearcase, ‘ FLOW 3’ flow followed
Languages ‘e’
Role • Verification of Script Processor(SCR), both module level and top level
• Update environment for SCR(DRPu) from SCR(DRPe)
Project AXI Verification IP creation in System Verilog
AXI VIP is a verification solution for IPs/SOC using AXI compliant DUT to
speed up the verification process.
Tools VCS
Languages System Verilog, Perl
Role • Specification study of AXI v1.0
• Involved in creation of Verification plan
• Overall architecture of the AXI VIP
• Architecting and coding of BFM
• Scoreboards for Master/Slave configuration for VIP testing on a DUT
• Verification and debug
• Coverage Closure
5. • Add new/modified monitors/checkers
• Test case modification/debug for modified features from DRPe to
DRPu.
• Add new Test case/update for new features
• Update ARM (Cortex) image files.
• Achieve 100 % code coverage for SCR.
• Simulator profiling for Modelsim
• Test Plan for Radio Packet Handler (RPH)
Project NL5500
This is an SOC consisting of Bluetooth, FM, GPS IP wrapped with a glue
logic (configurability) and power management block.
Tools Modelsim, Specman, Incisive formal verifier (Cadence), ClearCase ,
‘FLOW 3’ flow followed
Languages e, PSL, VHDL
Role • Re-use Bluetooth IP level Test cases at top level and verify SOC glue
logic
• Verify Power and Reset Muxing block using formal tool with PSL
Project AHB assertion IP
A set of assertions written in SystemVerilog to validate any component
said to adhere AHB-2.0
Tools VCS
Languages SystemVerilog
Role • Write assertion plan
• Code the assertions using SystemVerilog Assertions and test
Project I2S controller
A controller with I2S, APB and FIFO interface to cater the needs in audio
applications
Tools Ncsim
Languages Verilog, SystemVerilog
Role • Understand the existing ‘ATL’ environment
• Study the I2S, APB specification.
• Convert ‘ATL’ test cases into verilog and validate the conversion
• Built a well defined verification environment using SystemVerilog and
validated the same
Project KITE
A PCI based image solution consisting of SDRAM, JPEG compressor
chip, with standard video interface such as CCIR 656 and NTSC.
Tools VCS
Languages Verilog, Make
Role • Define micro-architecture for video interface, image trimming blocks
6. • RTL coding
• Verification of the blocks and fixing the RTL
Project Video Encoder for Qwikard
Compress real time video using proprietary algorithm.
Tools Modelsim
Languages VHDL
Role • Micro-architecture of ‘SUM OF DIFFERNCE BLOCK’
• RTL coding
• Verification of this block’s results with software computed values with a
module level setup
Project Nand Flash memory controller for Qwikard
A controller to store data, images into Nand Flash
Tools Modelsim
Languages VHDL
Role • Define micro-architecture for ECC algorithm blocks
• RTL coding
• Verification of the block’s result with software computed values with a
module level setup
Soft skills:
• Effective communication/client interaction demonstrated during various projects.
• Worked as team player and as individual owning responsibilities.
Academic Credentials:
• BE (ECE) from University of Gulbarga, Gulbarga in 2000 with 68% aggregate.
• PUC II in 1996 with 77.5 % and X in 1994 with 78.12% from SBR Composite School,
Gulbarga.
Personal Details
Father Name : Amrutrao Malkapgouda
Mother Name : Karunadevi Malkapgouda
Date of Birth : 19-08-1978
Passport Number : F9470695
Permanent Address : c/o Amrutao Malkapgouda
H.No 8-1305/128/40
