1. KEYANG FU
keyangfu@usc.edu, (213)-806-0232, 645 W 23rd St, Apt 2, Los Angeles, California 90007, USA
SUMMARY
To obtain a full time position working as a Hardware Engineer in summer 2016
Master student in Electrical Engineering, graduating in May, specializing in RTL coding (Verilog & VHDL), ASIC
design, Synopsys tools, and Cadence Virtuoso, and skilled in circuit diagnosis using C/C++/Perl.
EDUCATION
University of Southern California 08/14 - 05/16
Master of Science, Electrical Engineering (VLSI), School of Viterbi GPA3.5
Xidian University, Xi’an, Shaanxi, CHINA 08/10 - 07/14
Bachelor of Engineering, Electronic and Information Engineering GPA3.5
EXPERIENCE
USC Project: DDR3 Memory Controller Design 9/15-12/15
Designed a memory controller using Verilog. It handles various instructions from a processor at 625 MHz.
Synthesized the controller with Synopsys tools ensuring no violation.
Post-synthesized to verify functions.
USC Project: Out-of-Order Processor Design based on Tomasulo Algorithm 5/15-8/15
Designed ROB, CFC, Dispatch Unit, BPB, Issue Unit, and FRL, etc. using VHDL.
Emulated on FPGA, sent and verified data packages using UART.
USC Project: Full Custom General Purpose Multi-Cycle CPU Design & Layout 1/15-5/15
Designed a 512-bit SRAM, a 16-bit ALU, and a multi-port instruction memory.
Designed a row decoder, a pre-charge circuit, a write/read circuit, a 6T SRAM cell, and a sense-amplifier.
Sized transistors using Hspice, explored the 6T-SRAM sizing & sense-amplifier, reached the minimum
write/read access time, ensured no setup/hold time violation in specific period, got noise margin of bit line.
Simulated & verified function automatically using Perl: generated non-stalling test-vectors & calculated results
by Perl, simulated schematic & layout by Virtuoso, captured write-back data in simulation result exported from
Virtuoso, verified the captured data with the computed data by Perl.
USC Project: Testing Tool of Circuit Defects Design 10/15-12/15
Designed a tool for circuit defects diagnosis using C-language.
Generated test vectors as ATPG using D-algorithm & PODEM, and designed parallel/deductive simulators.
Detected all the defects.
USC Project: Typical Microprocessor Enhancement 1/15-5/15
Explored a baseline processor by analyzing its bottlenecks, and enhanced its speed by 58.2%.
Used SimpleScalar simulator, Cacti simulator and Real Estate Estimator to archive highest MIPS.
Simulated and recorded automatically using Perl.
RELATED COURSE
EE457 Computer Systems Organization EE477 VLSI Circuit design
EE557 Computer Systems Architecture EE577a&b VLSI System design
EE658 Diagnosis and Design of Reliable Digital Systems CSCI570 Algorithms
EE560 Digital System Design Tools & Techniques
SKILL
Languages: C/C++, MATLAB, Assembly language, VHDL, Verilog HDL, Perl
Software: Altium Designer, Altera Quartus II, Modelsim, Cadence Virtuoso, Simvision, Xilinx ISE designer