1. SRIRAM KRISHNA KAKARLA GNR RESIDENCY, BALAGARY
RD, NEAR VARTHUR POLICE
STATION
VARTHUR, BANGALORE,
KARNATAKA.
Mobile: +91-9741806212.
SUMMARY
Sr.Physical Design Engineer over the 6+ years of experience, having different roles: IC
Physical Design Engineer (RTL to GDSII), CAD STA, Layout Design Automation and
Corporate Design Solution. Apart from work, like to watch movies, conducting team building
activities and playing chess.
CAREER OBJECTIVE
To seek challenging assignment and responsibility with an opportunity for implementation of
high performance and low power SOC. Looking for a long term career with Technology
Company where I can give my 100% dedication and knowledge to design the cutting edge
integrated chip.
SKILL SET
 Designed optimal floorplans enabling a smooth work flow for the rest of the section.
 Took blocks through placement, clock tree synthesis, and routing.
 Closed timing for block and section level
 Implemented physical verification for blocks and section.
 Analyzed and implemented low power techniques using CLP (conformal low power).
 Executed physical and logical ECO for block and section level.
 Wrote Tcl scripts for common tasks to improve work efficiency
 Layout Drc Cleaning (Manual & Automation).
 Layout Quality Checks.
 Technology nodes worked on 32nm, 22nm, 14nm, 10nm.
 Tools worked on ICC, Innovus(EDI), DC compiler, Prime Time.
E-mail1: srk.kakarla88@yahoo.co.in
E-mail2: srk.kakarla@gmail.com

2. PROFESSIONAL EXPERIENCE
Qualcomm India Pvt. Ltd. (May’15 to till date)
 STA:
Roles & Responsibilities: Responsible to deploy, timing fixes and enhancement to
PT flow for the project.
• Involved in PT technology readiness for 14 & 10 nm projects. It is one of the
challenge making sure all derates and their versions are properly updating in the
flow.
• Enabled robust merged reporting structure across the sites which improves the
capability of tracking signoff metrics.
• Developed floor plan aware budgeting flow with proportionate slack allocation
• Developed utility for serpentine path reports.
• Developed PT based EM critical nets and passes through redhawk which
improved TAT time for the project execution.
 Mobile CPU(14 & 10nm):
Roles & Responsibilities: Place and route Execution for OHM, Low Power
Verification and Formal Verification checks for CPU blocks.
CLP checks was crucial due to PNR flow was not with power intent. Power intent
correction done based on CLP feedback. CLP is very critical and complicated to CPU
block which has more than 8 power domains and multiple power modes.
• Developed CPF aware power domain connectivity utility which helped to fix
cross power domain violations with in fraction of seconds.
Intel Technology India Pvt. Ltd. (SEP’10 to May’15)
 Next Generation Micro server & Server.
Roles & Responsibilities: Place and route Execution and Section Timing Owner for CBO.
 Cache Controller: CBO from RTL synthesis to till DRC cleaned GDSII.
CBO is a challenging block for timing and routing due to high frequency design
especially in servers. CBO are ring slice controllers, control the flow of message
between cores, cache slice and no core section of those chips. CBO has 3 partitions
and each partition having around 1.5M gates. CBO is timing complex block in servers
due to having latches to achieve high frequency.
• RTL to GDSII on CBO comprises of Logical synthesis, floor planning,
clock tree synthesis, Routing, STA, DRC & LVS and Section timing
sign off.
• Worked on CBO section for three server projects which are 14nm.
 Repeaters & Level Shifters: Repeaters are required for a signal passing over a
long distance in full chip at regular intervals, Level shifters are used to shift the signal
power domain.
• RTL to GDSII on Repeaters & Level Shifters comprises of Logical
synthesis, floor planning, clock tree synthesis, Routing, STA, DRC and
LVS.
• Worked on Full chip Repeaters & Level Shifters for one server project
which is 32nm.

3.  Strategic Initiatives:
• Developed reduction of buffer tree algorithm, during physical
synthesis, feed through paths are creating long length of buffer tree. Reduction
buffer tree algorithm removes and recreate minimum number of buffer tree
without fev issues.
• Automated eco change list generation script, developed to meet timing
for OCV (On Chip Variation) impact which came very late in design cycle.
Eco change list comprises of upsizing cell, downsizing, low leakage, ultra-low
leakage and nominal conversions without changing footprint of the standard
cell with minor physical drc’s.
• Created staple power grid by utilizing gaps between signals to decrease
RF layout routing congestion. Tracks may not be available for power when
signal routing is given high priority. Min Via density areas are then addressed
by placing power vias/float vias.
 Next Generation Low powered CPU
Roles & Responsibilities: Parade & Genesys tools development and support for custom layouts.
 Design Automation: Provided support to both fub and section flows for Intel
layout custom edit Tools Genesys and Parade over the 8 months.
 Stratagic Initiatives:
• Developed an efficient tool with in the parade to enable large floorplan
changes which came very late in design cycle. This reduced days of manual
effort by improving TAT to minutes. This tool is simple to use, yet clean and
efficient.
• Developed a track sharing utility which helps during cleanup stage.
This utility will free up a track for congested area by reassigning small chunks
with heuristic algorithm.
ACHIVEMENTS
 Got Divisional Recognition Award for CBO section timing closure along with
developing automated Macros.
 Got Divisional Recognition Award for Reduction of 75% manual effort for
Global Clock Distribution Network.
 Four Spontaneous Recognition Awards and many more Goodie Awards.
 Got Qualstar Diamond Award for the CLP CPU signoff having more than 8
power domains and multiple modes.
INTERNSHIPS
Intel Technology India Pvt. Ltd. (Sept’10-May’11)

4.  Provided a solution to convert internal database files to MW database. This involves
creating an intermediate ICC-TCL script from Intel Layout tool and sourcing it in the
ICC environment.
Tools: Intel Backend Tool, IC Compiler
Language: ITCL
 Developed “Partitioning algorithm” for Verilog netlist based on module instances
instead of gates with help of move edge algorithms. In this method, first the netlist is
built in hierarchical way and then level based partitioning is applied on it. Each level
is partitioned with initial nonrandom partition followed by KL algorithm in order to
ensure that final partition matches with Floor Plan. Converging speed has increased
considerably as it takes advantage of hierarchy.
Language: Perl
 Developed automation to provide one click net extension, which extends the
unconnected nets to nearest pin.
ACADEMIC PROJECTS
M.Tech: Clock Spine Layout Synthesis for High Frequency designs
o Developed automation to create a clock spine layout from the Verilog spine
netlist. This involves creating Slice layout using the slots available in the library and
porting the nets from the netlist appropriately. Placement of slices and routing
completion with drc cleaned spine layout.
MINI PROJECTS
1. Asic Based Automatic Solar Battery Controller:
Language: VERILOG
Environment: Linux
The idea behind this is when the battery is fully charged, solar panel conversion is waste
so making automatic controller which changes conventional power to renewable power
and again when low battery, conventional power becomes active.
Tools used are LOGIC SYNTHESIS by RTL COMPILER CADENCE 6.10 & Layout by
MENTOR GRAPHICS.
2. STANDARD CELL AOI32: AOI32 makes as ASIC Standard cell using FULL
CUSTOM IC DESIGN Approach, schematic simulation and layout simulation done
using TANNER S-EDIT and L-EDIT.
EDUCATION
2009-2011 M.Tech, VLSI DESIGN, VIT, Tamil Nadu, INDIA
VIT UNIVERSITY, VELLORE
2005-2009
B.Tech, ELECTRONICS & COMMUNICATION ENG., JNTU,
A.P,INDIA

5. ST.ANNS COLLEGE OF ENG&TECH. CHIRALA
2003-2005 BOARD OF INTERMEDIATE, A.P, INDIA
SRI VIDYA JUNIOR COLLEGE, CHIRALA
2002-2003 BOARD OF SECONDARY SCHOOL, A.P, INDIA
ADITHYA PUBLIC SCHOOL, CHIRALA
Declaration
I bear the responsibility for the correctness of the above-mentioned particulars.
Date: 17-11-16

6. ST.ANNS COLLEGE OF ENG&TECH. CHIRALA
2003-2005 BOARD OF INTERMEDIATE, A.P, INDIA
SRI VIDYA JUNIOR COLLEGE, CHIRALA
2002-2003 BOARD OF SECONDARY SCHOOL, A.P, INDIA
ADITHYA PUBLIC SCHOOL, CHIRALA
Declaration
I bear the responsibility for the correctness of the above-mentioned particulars.
Date: 17-11-16