1. Career Objective:
To work in an esteemed organization where i could give my best through my oriented approach & work for the betterment of the organization.
Professional Qualification:
Course : Master of Technology
Major : VLSI Systems and Technology
University : SHIV NADAR UNIVERSITY
CGPA : 8.02
Year of passing : 2014
Academic Qualification:
 B.E.-2011 (ECE) from University: R.G.P.V BHOPAL
With 78.63 %
 XII-2006 from MPBSE with 74.8%
 X-2004 from MPBSE with 78.8%
Technical Skills:
OPERATING SYSTEM: WINDOWS XP, 7, 8
Software Packages: TSPICE, L-Edit, S-Edit, W-Edit,
MODELSIM6.4, ELDO, CADENCE, Xilinx14.5
Language: VERILOG HDL, System VERILOG, Basics of C
Area of Interest: VLSI Domain
Academic Project:
M.tech Major Project:
Project: Synthesis and power analysis of Ring Based Network-on chip Architecture
Description: Ring Based NOC Architecture is commonly used to establish communication in today's data communication networking. The project involves VERILOG Hardware Description Language (HDL) description, design modeling, testing, functional and logical verification, Synthesis, place and Route and Power Analysis of Design Architecture. In this project, a NOC Architecture is designed based on low power synthesis technique at the Logic and Circuit level minimization and the Implementation of design on FPGA at software level.
NEHA JAIN Contact Address: Noida, NCR Email id: -neha.jain2u@gmail.com Phn.no-09555391491 Father’s name: Mr. NIRMAL KUMAR JAIN Date of Birth: 28-12-1988 PANCARD NO- AOUPJ1887L Strengths:  Optimistic  Quick Learner  Industrious

2. Software Package Used for Implementation: MODELSIM 6.4, XILINX 14.5, X-Power Analyzer, PLAN -AHEAD, VIRTEX -4 FPGA
Operating System: Windows7 and Windows8
M.tech Minor Projects:
Project 1: RTL Design Modelling of Successive Approximation Register (SAR)
Description: A SAR is an operational register that is a component of successive approximation analog- to-digital converter .The Algorithm is binary search that requires one iteration (clock cycle) to determine each bit of the result. The project involves VERILOG Hardware Description Language (HDL) description, design modeling, testing, functional and logical verification to show the actual behavior of the register and its internal process.
Software Package Used for Implementation: MODELSIM 6.4
Operating System: Windows7
Project 2: High Speed Design of SRAM-CELL
Description: The six-transistor (6T) static random access memory process. It has been used as a technology driver or test qualification vehicle, with which the derivation of the defect density is the primary concern. Despite that there are many works discussing the parameter variations in 6T SRAM bit cells, most of them are based on Monte-Carlo simulations. The project involves analysis of process parameter like write margin, read margin, Monte-Carlo analysis, discharge rate of SRAM Cell by using ELDO simulation tool.
Software Package Used for Implementation: ELDO
Operating System: Windows7
Project 3: RTL Analysis of Reed Solomon Encoder
Description: Reed-Solomon codes are block-based error correcting codes with a wide range of applications in digital communications and storage. The project involves the simulation, synthesis, timing analysis, place and route, floor planning by using cadence tool to analyze the behaviour of encoder.
Software Package Used for Implementation: Cadence
Operating System: Windows7
Training
Summer training in ST-MICROELCTRONICS: Studied VDT and MDT Also worked on tools: ELDO and CADENCE, and also done the project on VDT-RTL analysis on REED SOLOMON ENCODER and MDT-low voltage design of SRAM cell

3. Experience
 Works as Design and Verification Engineer at Incise Infotech Pvt. Ltd: From JULY 2014 to till now.
 Works as Teaching Associate in SHIV NADAR UNIVERSITY (U.P) :Interested in Digital Domain, Taking care of Tutorial Classes of Digital Electronics of B.Tech Courses for 2 Year (2012-2014).
Honors & Activities:
● Participated In Workshop on AUTONOMOUS ROBOTICS Conducted By MANIT Bhopal.
 Participated In National Level Technical Paper Presentation on Wireless and mobile
Conducted by THAKRAL College of Technology, Bhopal.
Declaration:
I hereby declare that the above-mentioned information is correct up to my knowledge and I bear the responsibility for the correctness of the above-mentioned particulars, and willing to relocate.
Place: NOIDA (NEHA JAIN)