1. Abdelrahman Abdallah Abdelfatah Elskhawy
41 Elkawmeya Elarabiya street, Mashaal, El- Haram,
Giza, Egypt
elskhawy.a@gmail.com
(+2) 0109-28-60-220
Military status: Exempted
OBJECTIVE A challenging opportunity in the

2. eld of Digital Design , embedded systems to build
upon and utilize my academic background, besides improving communication and
leadership skills.
EDUCATION 2008{2013 BSc: Cairo University, Cairo, Egypt.
Department of Electronics and Communication, Faculty of Engineering.
Elective Modules: Analog & Digital VLSI, and Industrial Electronics.
Cumulative grade: very good (79 %).
Graduation Project: Design of 64-bit IEEE standard Modal Interval binary Float-
ing point Adder/Subtractor with Decorations using Verilog.
The design targeted Stratix III FPGA family, and 65nm TSMC ASIC tech-
nology. Synthesis were done using Altera Quartus-II, and Synopses Design
Compiler respectively.
Noteworthy this is the 2nd hardware implementation of this unit and the 1st
implementation with the Decorations feature complying with the draft stan-
dard IEEE-P1788.
Presented at SCAN 2014 conference, University of Wurzburg, Germany in
September 2014, and will be published in Springers LNCS.
Winner of the 1st place inTarek Gamal El Din annual competition for grad-
uation projects in EECE dept., Faculty of Engineering, Cairo University.
Supervised by Prof. DR/ Hossam A.H. Fahmy, member of IEEE P1788 work-
ing group. Graded with Excellent.
Projects 18 Instruction simple Microprocessor using VHDL.
Design and layout of 8-bit ripple-carry adder chip.
Remote Terminal Unit (enrolled in EEDs projects).
Data acquisition system using
ash memory and PIC microcontroller.
MCQ grading system using a microcontroller, PC serial interface, and a Java code.
Technical skills
Knowledge
Maintaining very good knowledge for Digital, Analog, and MEMS design con-
cepts, layouts, and problems.
Very good command of using Cadence, Modelsim, Quartus, Synopses Design
Compiler, Pspice, Dip trace, ARES, L-Edit, and Proteus.
Very good experience in FPGA/ASIC design
ow.
Experienced in Verilog, and VHDL RTL design, simulation, synthesis, analysis,
and low power design.
Good knowledge of embedded C-programming, Microcontroller architecture,
and real time design.

3. Maintaining good knowledge of Digital communication systems and its imple-
mentation using Matlab.
Very good experience in Object-oriented programming, C++, TCL scripting,
Perl, and Java.
Computer Architecture, Data structures, Linux OS.
Implementation of test benches using simulators.
EXPERIENCE Embedded systems developer June{July 2014
Edge Technology for Automation solutions, Cairo, Egypt.
Providing support for the systems implemented using Atmel micro-controller,
GPRS modules, and Ts-7260 Arm processor board, maintenance of imple-
mented systems, and development of new systems based on the old ones.
Freelancer Technical Editor Translator March 2013{Dec 2014
Internship
Experience
PCB Egypt factory July 2010
{ Full training on PCB manufacturing techniques, and new technologies.
BTC networks July 2011
{ Telephone and networks systems, practical training on banks and hotels systems.
CBI-Lummus August 2011
{ DCS, site hazards, PID charts, PLC, Company management system.
Security Meter September 2011
{ Linux Administration, System programming, and File system management.
Language
pro

4. ciency
Arabic: Mother Tongue English: (Read-Written-Spoken: Very good)
EXTRA-
CURRICULAR
ACTIVITIES
IEEE CUSB graphics head, and HR member 2008{2012
Chairman of a campaign of Ethics. 2010{2011
Member of Resala charity organization 2010{2014
Moderator at Unimasr.com educational website 2010{2011
Space Systems Technology laboratory 2011-2013
Egyptian Engineering Day participant 2012-2012
Personal Skills Tactful and patient communicator.
A team player with strong soft skills.
Success motivated, and quick learner.
Perfect at meeting deadlines.
Interests Mixed Martial Arts
Brazilian Jiu-jitsu
Chess
Reading
Personal
Information
Date of birth: Nov, 4, 1991
Nationality: Egyptian
Marital status: Single