1. Kousik Dan Ph. no: 91-8350082818/91-9163552199
(Date of Birth: 5th
November 1989) email: kousikdan9609@gmail.com
OBJECTIVE:
Seeking a position to utilize my skill and abilities in the organization that offers professional growth
while being innovative, flexible and resourceful.
EDUCATIONAL QUALIFICATIONS:
• Pursued M. Tech. in Microelectronics and VLSI design (2013-2015) from National Institute
of Technology, Calicut (Kerala) with 8.08 CGPA.
• Pursued B.E. in Electronics and Communications Engineering (2007-2012) from RCC
Institute of Information Technology, Kolkata with 8.07 CGPA.
• Cleared Higher Secondary from W.B.C.H.S.E in Maths-Science stream in 2007 with 81.2%
aggregate.
• Cleared High School from W.B.B.S.E in 2005 with 84% aggregate.
TECHNICAL SKILLS:
HDL: VHDL,Verilog
HVL: SystemVerilog
Verification Methodology: UVM
Bus Protocols: AMBAAXI3, AXI4, APB
Communication Protocol: UART
Scripting Language: UNIX Shell Scripting
Tools: cadence incisiv, cadence IMC, cadence incisive vManager, Xilinx ISE 13.2
Skills: Functional Verification, Constrained-random verification, Assertion base verification, UVM,
Coverage Analysis, regression mechanism, DES
INTERNSHIP:
 STMicroelectronics, TR&D. from 1st
July, 2014 to 26 June, 2015 [approx 12 months].
Projects:
I. Development of Verification IP (VIP) for AMBA AXI3/AXI4 Protocol based on UVM
(Universal Verification Methodology) in System Verilog.
Verification IP (VIP) is designed based on suitable UVC (Universal Verification Component) structure
for AMBA AXI protocol specified interface. This Bus base VIP acts as mater or slave to validate IP and user
can configure multiple master or slave without testbench modification. All basic UVC components like driver,
sequencer, monitor, agent, scoreboard, env etc. are designed. Various test cases are generated that provide
satisfactory functional coverage using constraint random verification. A sophisticated scoreboard supports
parallel checking of slave memory. Regression management of test cases fulfills the targeted coverage within
deployment.
II. Development of Protocol Checker for AMBAAXI using SVA (System Verilog Assertions).
Testbench contains separate assertion base verification module that verify protocol specification at
interface level and enhances functional or protocol coverage. Activation of this protocol checker module can be
done partially or fully in a more flexible way.
III. Generic and automatic test cases generation on a common verification platform using
STBus VIP RAL access.
A well-documented test specification is converted to sequences that need to be accessed using test case.
STBus UVM RAL access setup the configuration of IP (DUV) before run a test and automatically
generated test cases verify the DUV of all available bus interfaces.
IV. Design Slave VIP for AMBAAPB based on UVM in SystemVerilog
A slave verification IP is designed to support master type DUV verification through APB interconnect.
This slave VIP has checked by a golden master UVC that exists in testbench.

2.  Technology : UVM, AMBAAXI, APB, Functional Coverage, Assertion base verification, Regression Mechanism
 Tools : Cadence incisiv, Cadence IMC, Cadence incisive vManager
 HVL: SystemVerilog
ACADEMIC PROJECTS:
 M.Tech 1st
semester
 FPGA Implementation of DES Encryption and Decryption using RS232 Interface in VHDL
Description: Data Encryption Standard (DES) is a symmetric-key algorithm for the encryption of electronic
data. RTL logic for encryption and decryption is developed and place it onto FPGA board. Original data and key
is processed and generated encrypted data that is retrieve back into original data with the same key by
decryption logic. UART protocol is used for interfacing the data communication
 M.Tech 2nd
semester
 Antilogarithm logic with multi-base implementation in VHDL
Description: Antilogarithm is reverse operation of logarithm. An algorithm is set up that computes
antilog of a fixed number (Positive as well as negative). Selection of base for antilog operation is under the
control of user. FPGA implemented RTL model required 8 bit input to execute antilog process and generate 13
bit output that is up to 9 bit precision.
 B.Tech Final year
 Single Electron Transistor & its application
Description: Single Electron Transaction (SET) and its characteristics are analysed. SET consume less
power than that of conventional CMOS. A suitable parameterised CMOS model that is mimics SET
characteristics is design and checks its performance as a frequency divider (T flip-flop) circuit.
PUBLICATIONS:
 “Evolution of Conventional Anti-logarithmic Approach and
Implementation in FPGA through VHDL”
IEEE, ICACCI 3rd
International Conference, September 26, 2014
Description: Efficient hardware implementation approach of Antilogarithm is implemented in FPGA.
Power consumption, chip area requirement and operation speed, these three key points is in focus for
optimization of RTL. Again accuracy limit of proposed algorithm is negligible. Multi-base mode configuration
can be achieved.
Author & Presenter: Kousik Dan
CO-CURRICULAR AND EXTRA CURRICULAR ACTIVITIES:
 Presented a seminar on On-Chip Antenna at National Institute of Technology, Calicut.
 Presented a seminar on Cloud Computing at RCC Institute of Information Technology.
 Summer training at WEBEL (30 days) on “NETWORK CONVERGENCE & STATIC ROUTING”
Languages Known & Hobbies:
Languages: English, Hindi, Bengali.
Special Interests: Novel Reading, solving Sudoku, picture sketching.
DECLARATION
I hereby certify that the information given in my resume is correct and complete to the best of my
knowledge and understanding
Place: Greater Noida
Date: Jun 09, 2015. Kousik Dan