1. Curriculum Vittae
LAVANYA J Email : lavanya.vlsi@gmail.com
Mobile : +91-9148791339,
+91-8125220991.
CAREER VISION
To work in a challenging environment demands all my skills and efforts to explore myself in VLSI industry and
realize my potential where I get the opportunity for continuous learning.
PROFESSIONAL SUMMARY
 1+ years of Experience in RTL code Developing for the designs.
 Currently verifying the RTL code of the individual modules of the ARINC 818 TX as per the DO-254
policy norms.
 Worked on ARINC 818 integration for Spatan6 FPGA’s.
 Developed a parameterized custom Native FIFO.
 Worked on HDL Designer tool to map the design according to the board level and DO-254 policies with
the help of design rule checker and other policies along with the coverage report as a part of project norms.
 Worked on ReqTracer tool to verify the Requirements of ARINC 818 Transmitter by writing low and
high level requirements along with verification plan.
 Designed Video capture 24bit to 32 bit conversion block, packetizer block, data handler block, data length
handler block modules for ARINC 818 Transmitter.
 Worked on Header Generation, Payload Generation for ARINC 818 Transmitter Design.
 Designed Ethernet Packet Generation & Basic Pattern Generation Using Temac 5.5 Version and MII
Receiver.
 Good exposure on Spartan3E and Spartan6 FPGAs.
 Good exposure on System Verilog.
 Having good understanding on Hardware Description Languages (HDLs).
EXPERIENCE
 November 2015 to till Date: Currently working as a Project Scientist in National Aerospace
Laboratories, Bangalore since November.
 July 2014 to December 2014: Completed Professional Development Course in VLSI System at
Sandeepani School of VLSI and Embedded system design, Bangalore.

2. EDUCATIONAL QUALIFICATION
 M.Tech in VLSI (Very large scale integration) With Distinction grade from Sathyabama University
(Chennai).
 B.Tech in E.C.E (Electronics and Communications Engineer) from G.V.R & S College of Engineering &
Technology affiliated to Nagarjuna University.
 Intermediate in MPC from Nalanda Junior College Vijayawada affiliated to Board of Intermediate
Education, Andhra Pradesh, in 2007.
 SSC (10th
) from P.R.G.G.High School, Kakinada affiliated to Board of Secondary Education, Andhra
Pradesh, in 2005.
TECHNICAL SKILLS
Programming Languages : VHDL, Verilog, and System Verilog.
Tools : Xilinx ISE Simulator, Xilinx Plan Ahead
Model Simulator, Questa Simulator, ReqTracer, HDL Designer.
FPGA Boards : Spartan.
Operating System : Windows XP, Windows 7, Windows 8.
PROJECT EXPERIENCE
Project 1: At National Aerospace Laboratories
Project Title: Design & Verification of Avionics Digital Video Bus Protocol (ARINC 818).
Description: The Video Capture 24 bit to 32 bit Conversion,Packetizer,Data handler, Data length handler modules
are as part of the transmitter block generates the User defined data along with the Video data as per the standards
and sends these User defined data along with the Video data to the receiver.
Role : RTL code developing for the modules of the ARINC 818 Transmitter Block.
Tools : Xilinx ISE, ReqTracer, HDL Designer.
Language: VHDL for RTL Coding.
ACHIEVEMENTS & PARTICIPATION
 XILINX Certified Training Program, Conducted by Coreel Technologies.
 Presented a paper in VIDURA'10, A National Level student paper contest on the topic “Digital
bike operating system sans key”.

3. PERSONAL DETAILS
Gender : Female.
Date of Birth : 28-03-1990.
Nationality : Indian.
Marital Status : Married.
Languages Known : Englishs, Telugu.
DECLARATION
I do here by declare that all the above statements are true to the best of my knowledge and belief.
Place: Bangalore. Signature
Date: LAVANYA J